基于形态学的十字目标定位方法研究

为了提高微操作系统的装配精度,提出了一种基于形态学腐蚀算法和Hough变换的十字目标亚像素中心定位方法。首先通过选取适当的结构元素,分别对组成十字图像的垂直、水平方向的直线段进行腐蚀处理,得到含有十字中心信息的水平和垂直的两条行、列像素,行、列的相交点即为十字图像特征的中点;然后选取适当参数空间,对行、列进行Hough变换并将结果记入参数空间累加器,最后对区域内点进行加权平均处理,得到十字图像亚像素中心定位。实验结果表明：该方法具有定位速度快,定位精度高的优点。     

基于FPGA的二维提升小波变换IP核设计

提出了一种高效并行的二维离散提升小波(DWT)变换结构,该结构只需要7行教据缓存,即可实现行和列方向同时进行滤波变换.采用一种基于CSD编码和优化的移位加操作实现常系数乘法器,整个小波变换插入多级流水线寄存器,加快了处理速度.用VHDL设计可自动验证的testbench,通过matlab+modelsim联合仿真能方便有效地对IP核进行验证.此IP核具有3个可配置参数,分别为图像尺寸、位宽、小波变换的级数,可方便重用.该IP核已经在XC2VP20 FPGA上实现,并能稳定工作在60MHz时钟频率下,其处理512512 8bil图像的速度可达240帧/s,完全能满足高速图像实时处理要求.     

一种基于小波变换的快速图像编码算法

在传统的图像小波变换中,首先需要对每行进行小波变换,等所有的行变换完成后再进行列小波变换,然后再进行嵌入式量化和编码,这就需要足够的存储容量保存这些变换结果,而且运算速度也慢。该文提出了一种基于小波变换的快速编码方法。在行变换中,仍然使用传统的提升结构,在列变换中,使用基于因果系统的低存储容量的提升结构。一旦有小波系数输出,就进行相应的量化、编码。该方法不仅压缩效果较好,而且在运算时间上得到大大提高。     

航天器图像压缩小波变换的FPGA设计

为了实现基于FPGA的CCSDS图像压缩算法,在提升小波变换结构的基础上,提出了一种改进的基于行的并行3级2-D整数9/7小波变换实现结构.结构充分利用流水线设计技术,对于每一级2-D DWT,结构包含2个行处理器同时处理2行数据,借助10个行缓存存储变换的中间数据,实现了行、列变换的并行运算.同时对于3级小波变换,也采用了流水线结构,减少了存储器的使用量和对其访问造成的时间延迟,提高了变换速度.本结构完成分辨率为N×N灰度图像的3级小波分解所用的时钟周期约为O(N2/ 2).采用Altera的Stratix II FPGA实验,结果表明,本整数小波变换结构具有较高的吞吐率和变换速度,可以工作在86.5MHz的频率下,实现1024×1024灰度图像100fps的图像实时变换.     

小波滤波器低功耗并行的VLSI结构设计

提出一种基于行和提升算法,实现JPEG2000编码系统中的小波正反变换(discretewavelettransform)的低功耗、并行的VLSI结构设计方法·利用该方法所得结构一次处理两行数据,分时复用行处理器,使行处理器内以及行、列处理器实现并行处理,且最小化行缓存·对称扩展通过嵌入式电路实现,整个结构采用流水线设计方法优化,加快了变换速度,增加了硬件资源利用率,降低了功耗,效率几乎达到100%·小波滤波器正反变换结构已经经过FPGA验证,可作为单独的IP核应用于正在开发的JPEG2000图像编解码芯片中·     

高性能二维9/7离散小波变换VLSI结构

为了降低二维小波变换中的存储消耗并同时提高电路处理速度,提出了一种二维并行的VLSI结构。通过充分挖掘二维变换中行变换和列变换之间的关系,优化了行变换核和列变换核的并行数据扫描输入方式,将9/7小波变换的中间存储降低至4N。同时,采用基于翻转格式的流水线技术,将电路的关键路径缩短至一级乘法器延时,有效地提高了电路处理速度,并通过伸缩电路合并的优化方法将乘法器个数降低至10个,从而有效地减少了硬件资源消耗。     

二维离散小波提升变换算法的并行结构设计

提出了一种二维离散小波提升变换（2DDWT）的2×2并行结构。该结构充分利用了2DDWT算法固有的行并行、列并行、行列并行的三种并行性,有效提高了算法执行速度,同时显著降低了硬件存储需求。处理N×N图像的时间为N2/4+N/2+1,系统存储需求为3N。FPGA实现结果证明了本设计的正确性和有效性。     

基于轻量型AES加密算法的浮空器平台数据传输方案

针对浮空器平台在数据传输过程中受到自身处理器性能限制的问题,提出了一种基于轻量型AES加密算法的浮空器平台数据传输方案。首先,方案以AES加密算法为基础,通过寻找轮函数循环的局部最优次数和将状态矩阵行移位变换改为列移位变换实现轻量型AES加密算法;其次,通过字节代换、列移位变换、列混合和轮密钥加四个步骤,设计以七次轮函数循环为核心的轻量型AES加密算法;最后,通过字节填充和矩阵旋转两个操作对过往不同类型的浮空器平台飞行数据进行预处理,并将预处理后的数据作为明文数据源输入对传输方案进行测试和分析,验证了轻量型AES加密算法的安全性和有效性。实验结果表明,该算法与AES加密算法相比,在保证数据安全传输的同时提高了算法运行速度,可以较好地应用于浮空器平台。     

基于三维小波变换的视频散列算法

针对视频水印系统的安全性问题,提出一种基于三维小波变换的视频散列算法。该算法对预处理后的三维视频序列依次进行行方向一维小波变换、列方向一维小波变换和时间方向一维小波变换,完成视频序列的一层三维离散小波变换,并给出散列计算结果。仿真实验证明,该算法对帧内像素移动攻击及随机帧抖动攻击具有较强的鲁棒性。     

一种资源共享的快速加解密AES算法的实现

针对AES算法的特点,提出一种适用于在FPGA上实现的快速加解密资源共享的AES算法。对传统的AES加解密的s_box进行变换,使用一张查找表实现了加解密过程的资源共享,有效的节省了硬件实现面积。并对AES加解密的列混合变换进行了改进,从而达到资源共享,节省资源。本方案对轮密钥扩展,列混合变换及其逆变换等操作进行了优化处理,并在加密计算及解密计算中对S-盒,列混合变换等关键计算部件进行了复用,并且采用AES轮内流水结果和密钥并行处理,可在一块芯片上同时支持128位、192位、256位三种密钥长度的加解密算法。实验结果表明本设计相比于其他设计具有更高的性能。     

一种用于JPEG2000的小波变换VLSI结构设计方法

为了快速地进行小波变换,提出了一种应用于JPEG2000的基于提升格式5/3,9/7统一的离散小波滤波单元;同时对于行列并行滤波,提出了一种控制机制,其在缓存5行的条件下,可完成高速行列并行滤波操作。该方法在保证精度条件下,可以取得较高的硬件利用率,且中间数据暂存空间需求低。然后在提升结构基础上,完成了硬件模块设计,并进行了仿真和FPGA实现。最后用Verilog HDL对系统进行了硬件描述,并在Altera DE2的验证板上的cyclone2 EP2C35FC672芯片上,在Quartus 6.0环境下实现了该结构功能。     

二维提升小波变换的FPGA结构设计

根据提升小波的框架结构，提出了一种基于JEPG2000的二维多级提升小波变换核的FPGA设计。 采用分时复用和流水结构，充分利用FPGA片内存储资源，实现了行列变换的并行执行。在保证精度的前提下采用优化的移位加操作代替浮点乘运算，加快了运算速率，减小了电路规模。同时通过乒乓操作完成FPGA和片外SDRAM间数据的无缝缓冲处理，保证了多级变换的高效实时并行，从而达到各级小波系数的快速并行输出。系统经验证完全满足图像实时处理的要求，为后续实时压缩编码和传输提供了有利条件。     

FPGA implementation of highly scalable AES algorithm using modified mix column with gate replacement technique for security application in TCP/IP

Field Programmable Gate Arrays (FPGA) offers a faster, increasingly adjustable arrangement. Earlier Data Encryption Standard (DES) algorithms have been developed, however it could not keep up with advancement in a technology and it is no longer appropriate for security. With this motivation, this work developed an efficient FPGA implementation of Advanced Encryption Standard (AES) targets to investigate a huge number of security processes followed in the TCP/IP protocol suite and to suggest a novel new architecture for the existing version. The first contribution of the studies turned into to provide the safety for packages of the utility layer protocols. The AES cryptographic encryption, decryption and key management set of rules to for the safety of transmission control protocol/internet protocol (TCP/IP) protocol suite turned into carried out. AES is one of the maximum famous cryptographic algorithms used for records safety. The cost and consumption of power in the AES can be decreased substantially by way of optimizing the structure of AES. This research article projects an implementation based on modification in Mix column in AES techniques which gives a compact structure with efficient mix column Boolean expression the usage of resource sharing architecture and gate replacement method. The ON-chip power utilization and area overhead of the proposed hardware implementation outperforms the preceding work performed in this area. The proposed architecture have been carried out on the most latest virtex 6 lower power Field programmable gate array (FPGA), whereas overhead and on-chip utilization of power are compared with the previous works and it is proved that proposed method has lower area utilization and ON-Chip utilization of power.     

A novel hardware-oriented Kohonen SOM image compression algorithm and its FPGA implementation

Kohonen self-organizing map (K-SOM) has proved to be suitable for lossy compression of digital images. The major drawback of the software implementation of this technique is its very computational intensive task. Fortunately, the structure is fairly easy to convert into hardware processing units executing in parallel. The resulting hardware system, however, consumes much of a microchip’s internal resources, i.e. slice registers and look-up table units. This results in utilising more than a single microchip to realize the structure in pure hardware implementation. Previously proposed K-SOM realizations were mainly targetted on implementing on an application specific integrated circuit (ASIC) with low restriction on resource utilization. In this paper, we propose an alternative architecture of K-SOM suitable for moderate density FPGAs with acceptable image quality and frame rate. In addition, its hardware architecture and synthesis results are presented. The proposed K-SOM algorithm compromises between the image quality, the frame rate throughput, the FPGA’s resource utilization and, additionally, the topological relationship among neural cells within the network. The architecture has been proved to be successfully synthesized on a single moderate resource FPGA with acceptable image quality and frame rate.     

二维寻址与数据置换嵌入的多媒体存储体系

针对多媒体处理算法存储访问的特点,提出了一种新的多媒体扩展存储体系。该体系采用二维字节寻址,支持行访问和列访问;将数据置换操作与存储器访问操作相融合,通过数据置换来实现复杂的地址变换。基于此体系设计了指令系统和硬件原型。通过H.264算法测试表明,所述体系可以减少平均约32.0%的存储器访问率以及25.4%的时钟周期数。     

Reconfigurable address generator for multi-standard interleaver

This paper presents low-complex and novel techniques for designing reconfigurable architectures for multi-standard address generator and interleaver. The emphasis of this work is on hardware re-use, but it also focuses on optimizing the hardware to support multiple standards. A low-cost reconfigurable architecture for address generator and interleaver is proposed which operates in WLAN (802.11a/b/g and 802.11n), WiMAX (802.16e) and 3GPP LTE standards. A simple algorithm and a reconfigurable architecture that eliminates the computationally intricate mod function for LTE, and floor as well as mod function for WLAN/WiMAX, are proposed to reduce the hardware cost as well as implementation complexity. Novel architectures are also proposed to select the increment values for 16-QAM and 64-QAM schemes. A unique configurable subtracting sub-block for each modulation scheme is also presented. Software simulation is carried out to authenticate the functionality of the algorithm. The proposed reconfigurable architectures are realized on FPGA and tested on board. Synthesis results on Spartan-3 FPGA display 66% reduction in FPGA resource utilization and 74% increase in operating frequency compared to the cited address generators. Implementation results on Kintex UltraScale FPGA display a reduction of 34% in resource utilization and 20% in total on-chip power compared to the cited interleavers. This design is also implemented using 45 nm CMOS standard cell technology, and ASIC synthesis results of the reconfigurable address generator exhibit 76.4% improvement in data rate and 52.23% decrease in latency compared to the state-of-the-art address generators. The proposed multimode interleaver also exhibit 60.28% reduction in hardware complexity.     

两段式虚拟网络功能硬件加速资源部署机制

设计硬件加速机制,解决软件定义网络/网络功能虚拟化（SDN/NFV）架构中虚拟网络功能（VNF）的性能受限问题,成为当前的研究热点。在引入VNF硬件加速资源后,如何实现对加速资源的统一管理和部署,是亟待解决的问题。为此,首先提出了基于服务器端加速卡和OpenFlow交换机的VNF加速资源的统一管理架构;在此基础上,对加速资源部署问题进行建模,通过分析VNF加速资源对服务链映射的影响,提出了VNF加速资源部署策略的评价指标;最后,设计了两段式的加速资源部署算法求解该问题。实验结果表明,与只考虑节点单一属性的部署算法（SARD）和均匀部署算法（UARD）相比,所提机制能够优化部署加速资源,加速资源承载的流量和加速资源的利用率分别提升41.4%和14.5%。     

Hardware implementation of CMAC neural network with reduced storage requirement.

The cerebellar model articulation controller (CMAC) neural network has the advantages of fast convergence speed and low computation complexity. However, it suffers from a low storage space utilization rate on weight memory. In this paper, we propose a direct weight address mapping approach, which can reduce the required weight memory size with a utilization rate near 100%. Based on such an address mapping approach, we developed a pipeline architecture to efficiently perform the addressing operations. The proposed direct weight address mapping approach also speeds up the computation for the generation of weight addresses. Besides, a CMAC hardware prototype used for color calibration has been implemented to confirm the proposed approach and architecture.     

A hybrid PC/PLC architecture for manufacturing-system control—theory and implementation

This paper presents a novel and generic PC/PLC-based software/hardware architecture for the control of flexible manufacturing workcells. The proposed implementation methodology is based on the utilization of any one of the available formal discrete-event-system control theories in conjunction with state-of-the-art industrial programmable-logic controllers (PLCs). The methodology has been illustrated to be a viable technique through its actual implementation in our laboratory using a robotic-workcell testbed. The specific control theory used is a combination of Extended Moore Automata and Ramadge-Wonham Automata that has been developed by our research group. The modular control software architecture has been developed for MS-Windows environments (running on one PC interfaced to the PLCs) and allows the use of different formal control theories as well as different commercial PLC hardware. The effective graphical user interface provides a transparent programming environment, where users are not expected to have a full knowledge of the formal control theory used.