带有静电自检测功能的高灵敏度加速度传感器

研究了一种带有自检功能的在平面内自限制压阻式加速度传感器.为实现该加速度传感器,提出了一套新的体硅微机械工艺,使用普通硅片取代SOI硅片来制作器件.传感器采用在深槽侧壁(悬臂梁弯曲的表面)制作压阻的方法,灵敏度比在硅表面上制作压阻的传统器件高近一倍.传感器利用集成在内的静电驱动器,实现电自检测功能.     

基于MEMS的硅微压阻式加速度传感器设计

硅微加速度传感器是MEMS器件中的一个重要分支,具有十分广阔的应用前景。由于硅微加速度传感器具有响应快、灵敏度高、精度高、易于小型化等优点,而且该种传感器在强辐射作用下能正常工作,因而在近年来发展迅速。文章首先对传感器结构及工作原理进行了简单介绍,给出了一种基于MEMS技术制作的压阻式硅微加速度传感器的结构和工艺,并对制作的加速度传感器样品进行了动态测试,测试结果表明与理论设计值基本吻合。     

低温漂过载加速度传感器

过载加速度传感器,是采用了最新的MEMS技术与微电子技术研制的一种新型硅压阻加速度传感器,集加速度敏感元件、信号放大、饱和控制及温度补偿等于一体,对传统的电桥放大电路和温度补偿电路进行了改进,使得传感器温漂更小且具有可编程补偿温度和增益调整等功能.     

横向加速度传感器设计及特性研究

一般微机械加工的梁──岛结构加速度传感器，梁的平面都是与器件平面平行的，因此只能测量器件平面法向的加速度分量．我们提出了一种制作梁平面与器件平面相垂直的梁──岛结构的微机械加工方法，并用以设计和制造了一种可测量平行于器件平面的加速度分量的横向加速度传感器，为研制三维加速度传感器提供了新思路．     

一种半岛型结构谐振梁压力传感器

提出了一种新型结构压力传感器，器件由上下两硅片键合而成，上硅片制作半岛型结构氮化硅谐振梁，下硅片制作矩形压力膜。应用有限元软件对器件结构及灵敏度进行了计算机模拟分析，器件利用MEMS技术研制并采用电热激励压阻拾振方式进行了测试。实验及理论模拟分析结果证实新型结构可以大大提高压力传感器灵敏度。     

MEMS压阻加速度传感器阻尼特性研究

研究了空气阻尼对MEMS压阻加速度传感器性能的影响,建立了传感器动力学模型和空气阻尼模型,分析了空气间隙大小与传感器阻尼系数的相互关系,通过控制空气间隙可以达到控制加速度传感器阻尼的目的。根据分析结果设计了三明治结构封装的传感器,应用有限元仿真软件,对传感器的应力和应变进行了仿真计算,完成传感器结构参数设计;采用MEMS体硅加工工艺和圆片级封装工艺,制作了MEMS压阻加速度传感器。测试结果表明,采用三明治结构封装形式,可以控制压阻加速度传感器的阻尼特性,为提高传感器性能提供了途径。     

基于SOI的集成硅微传感器芯片的制作

为满足小体积、多参数测量的要求,采用SOI硅片,设计了一种测量三轴加速度、绝对压力、温度参数的单片集成硅微传感器,其中加速度、绝对压力传感器基于掺杂硅压阻效应,温度传感器基于掺杂硅电阻温度效应.根据集成传感器的结构,制定了相应的制备工艺步骤.针对芯片上各电阻间金属引线的可靠性问题和加速度传感器质量块吸附问题提出了有效的改进方法.最后给出了集成传感器芯片的性能测试结果.     

3255系列新型加速度传感器

<正> 本文介绍的3255系列新型压阻式加速度传感器,是美国EG＆G集团IC传感器公司的新产品,主要用于汽车正面及侧面防冲击气袋系统、军用保险系统、工业振动监控记录仪器等。 结构与原理 该系列传感器由两块芯片组成:一是由硅片经微细加工     

用于汽车的硅压力和加速度传感器

用于汽车的硅压力和加速度传感器张传忠许多压力和加速度传感器都是以硅微电子学技术为基础的。由于硅传感器可作为敏感元件与表面电路集成在同一基片上，所以硅压力传感器广泛地用来检测歧管绝对压力。与普通的应变现传感器相比，硅的机械和弹性特性要好得多。它作为一种...     

基于SOI的集成硅微传感器芯片的制作

为满足小体积、多参数测量的要求,采用SOI硅片,设计了一种测量三轴加速度、绝对压力、温度参数的单片集成硅微传感器,其中加速度、绝对压力传感器基于掺杂硅压阻效应,温度传感器基于掺杂硅电阻温度效应.根据集成传感器的结构,制定了相应的制备工艺步骤.针对芯片上各电阻间金属引线的可靠性问题和加速度传感器质量块吸附问题提出了有效的改进方法.最后给出了集成传感器芯片的性能测试结果.     

One-mask process for silicon accelerometers on Pyrex glass utilising notching effect in inductively coupled plasma DRIE

A one-mask process technology is proposed to fabricate silicon capacitive accelerometers using comb drive structures. A doped silicon wafer is anodically bonded on Pyrex glass substrate. High aspect ratio silicon accelerometer structures are micromachined using deep reactive ion etching (DRIE) and released from the glass substrate by further DRIE due to its notching effect.     

一种具有“8悬臂梁-质量块”结构的新型硅微加速度计

提出了一种具有"8悬臂梁-质量块"结构的新型三明治式硅微机械电容式加速度计,用微机械加工工艺在(111)硅片上制作出了具有信号输出的器件.该加速度计的惯性质量块由同一(111)硅片上下表面对称分布的8根悬臂梁支撑.这些悬臂梁是利用(111)硅在KOH溶液中的各向异性腐蚀特性结合深反应离子刻蚀(DRIE)实现的,其尺度精确可控,保证了结构的对称性.该加速度计的谐振频率为2.08kHz,品质因子Q为21.4,灵敏度为93.7mV/g.     

一种微机械压阻式加速度传感器及其设计优化

给出了一种新型的微梁直拉直压的微机械压阻式加速度传感器的工作原理。该设计能同时提高传感器的灵敏度和自由振动频率。基于分析模型 ,本文还给出了传感器的结构优化和各种量程的设计规则。采用SOI硅片和深反应离子刻蚀 (DRIE)工艺给出了传感器的制造和测试结果     

Prediction of the thickness for silicon wafers sawn by diamond wire saw

A higher yield and lower processing cost for the production of the silicon wafer can be realized by reducing the sliced thickness. However, a larger fracture probability is accompanied with the thinner silicon wafer, which limits the wafer thickness to be reduced. The contradiction between reducing wafer thickness and keeping a smaller fracture probability is an important problem for the industrial production of the silicon wafer. This paper investigates the influences of silicon wafer size and machining defects on the fracture probability in order to understand the essential relationship between damage information and fracture probability adequately. A theoretical model of the fracture probability for silicon wafer is proposed based on the probabilistic fracture mechanics to determine a proper thickness for wafers with different size. Furthermore, one method of predicting a proper thickness for silicon wafers sawn by diamond wire saw is developed. The thickness of 450-mm silicon wafer obtained by this proposed method is 920 µm, which is comparable with the value 925 µm specified by the International Technology Roadmap for Semiconductor. The comparison of these two values reveals the feasibility and correctness of this proposed method. The proposed model in this paper can be used to evaluate the fracture probability and predict a proper thickness for silicon wafers with different size, which is benefit to optimize the processing technology and decrease the breakage ratio for the wafer production.     

集成微型自适应加速度测试仪研究

提供了一种采用硅微加速度计和ＡＳＩＣ构成的自适应采集和存储测试加速度信号波形的集成微型测试仪。该测试仪有１２８种采样频率随被测信号实时自适应改变，最高采样频率为１０ＭＨｚ，存储容量可达１Ｍ字节，单电源５Ｖ供电，采集时功耗５０ｍＷ，保存数据时的功耗为２０μＷ，测量范围±５００ｇ，抗过载能力为３０倍量程，具有系统自检功能，自带微机接口，而其整体体积仅有２．４ｃｍ３。     

Development of a microelectromechanical system pressure sensor for rehabilitation engineering applications

Based on computer finite-element analysis ANSYS 5.3 and microelectromechanical systems (MEMS) technologies, a micropressure sensor was designed and fabricated. The sensor can be used to measure the distribution of normal stress between soft tissues on an above-knee amputee's skin and the contacting surface of a rehabilitation device. A square membrane with dimensions 2400 µm × 2400 µm × 80 µm is formed by backside photolithography and wet etching of an n-type ?100? monolithic silicon wafer. On the middle of the membrane edge, an X-shaped silicon wafer was implanted with boron ions and then enhanced by diffusion to form a piezoresistive strain gauge. In the design process, a finite-element method is used to analyse the effects of pressure sensitivity and its temperature coefficients. The developed micropressure sensors, which have smaller weight and volume than a conventional machine type, perform well and fit our design specifications.     

Modeling the Well-Edge Proximity Effect in Highly Scaled MOSFETs

The well-edge proximity effect caused by ion scattering during implantation in highly scaled CMOS technology is explored from a physics and process perspective. Technology computer-aided design (TCAD) simulations together with silicon wafer experiments have been conducted to investigate the impact of this effect. The ion scattering model and TCAD simulations provided a physical understanding of how the internal changes of the MOSFETs are formed. A new compact model for SPICE is proposed using physics-based understanding and has been calibrated using experimental silicon test sets     

Three-Dimensional Integration Technology Based on Wafer Bonding With Vertical Buried Interconnections

A three-dimensional (3-D) integration technology has been developed for the fabrication of a new 3-D shared-memory test chip. This 3-D technology is based on the wafer bonding and thinning method. Five key technologies for 3-D integration were developed, namely, the formation of vertical buried interconnections, metal microbump formations, stacked wafer thinning, wafer alignment, and wafer bonding. Deep trenches having a diameter of 2 mum and a depth of approximately 50 mum were formed in the silicon substrate using inductively coupled plasma etching to form vertical buried interconnections. These trenches were oxidized and filled with n+ polycrystalline silicon or tungsten. The 3-D devices and 3-D shared-memory test chips with three-stacked layers were fabricated by bonding the wafers with vertical buried interconnections after thinning. No characteristic degradation was observed in the fabricated 3-D devices. It was confirmed that fundamental memory operation and broadcast operation between the three memory layers could be successfully performed in the fabricated 3-D shared-memory test chip     

Relationship between wafer fracture reduction and controlling during the edge manufacturing process

Given the trend towards wafers of a larger diameter, microelectronics circuits are driven by modern IC manufacturing technology. Silicon wafer breakage has become a major concern of all semiconductor fabrication lines because silicon wafer is brittle and high stresses are induced in the manufacturing process. Additionally, the production cost is increasing. Even a breakage loss of a few per cent drives up device costs significantly if wafers are broken near completion, but wafer breakage even near the beginning of the process is significant.In this paper, we first point out the approach for the characterization of silicon wafer failure strength empolying a simple drop test, thereby providing a better understanding of the stress accumulated in wafer bulk before failure.This study also presents a brand new method using a charge coupled device (CCD) to capture the cross-section image of the wafer at the wafer edge; the data measured at the edge can be used to diagnose overall wafer strength. Analysis of the image of the wafer edge is used to characterize silicon strength and a simple drop test is conducted to elucidate wafer failure, improving our understanding of the accumulation of stress in wafer bulk before failure.This work presents an approach for characterizing silicon wafer failure strength using a simple drop test, to improve our understanding of the stress accumulated in wafer bulk before failure. However, this work will describe many of the improvements that have resulted in the virtual elimination of wafer breakage due to unknown reasons. According to an analysis based on the material mechanical theory for the bevel lengths (A1, A2), the edge length and the bevel angle (θ) are optimized to design the edge profile of the produced wafer, to prevent wafer breakage. Restated, when proper material and process control techniques are utilized, silicon wafer breakage should be prevented. This work is the first to demonstrate the importance of understanding wafer strength using a simple mechanical approach.