Origin and Control of Material Defects in Silicon VLSI Technologies: An Overview

Very large-scale integrated circuits impose stringent demands on the quality of silicon wafers required for their fabrication. This paper is an overview of the interrelationships among silicon characteristics, processing, circuit performance, and crystal growth. The relationship between circuit performance and defects in the substrate is described, particularly the effects resulting form the transition from LSI to VLSI. The defect-generation process is then discussed in terms of as-grown silicon characteristics and crystal-growth conditions that control them. The interdependence of material parameters, internal gettering procedures used to reduce the effect of defects on device performance, and resistance to the warpage of silicon wafers is reviewed, with special emphasis on the current and future requirements of bipolar, MOS, and CCD processes.     

Fundamental modification of gate silicon dioxide layer as a result of lateral gettering of electrically active centres

The method of the lateral gettering of the ionised donor centres from the gate oxide layer is presented. This method is based on the capture of the excess hydrogen from the gate oxide peripheral regions by the point defects in the lateral oxide layer. The additional generation of the point defects in the lateral oxide layer in the process of Ar⁺ ion bombardment was found to intensify the lateral gettering processes. The most effective passivation of the electrically active centres in the gate oxide layer was found to occur in the structures with a high perimeter/area ratio, particular to the MOS device of the VLSIC.     

Spatially inhomogeneous oxygen precipitation in silicon

A theoretical model for point-defect precipitation in crystals, which is a generalization of the well-know Ham model, has been proposed. The equations obtained are helpful in describing the kinetics of oxygen precipitation in silicon, and in determining the kinetics of variation of the mean geometrical dimensions of clusters. A theoretical model of spatially inhomogeneous precipitation has been developed. This model can be used to describe processes of internal gettering and creation of insulating layers in silicon. Fiz. Tekh. Poluprovodn. 33, 1281–1286 (November 1999)     

Latch-up and image crosstalk suppression by internal gettering

Internal gettering can be used to reduce crosstalk in imagers and latch-up susceptibility in CMOS circuits. The internal gettering process forms defects in the bulk of the silicon wafers that are effective recombination sites for minority carriers in the substrate. Experimental and theoretical results are presented for the crosstalk reduction obtained in an area imager. Also, the current gain β of the parasitic lateral n-p-n transistors formed in the substrate in CMOS circuits was considerably lower for the internally gettered wafers. The trigger current needed to initiate latch-up in the n-p-n-p structures increased as 1/β, in accordance with the theory. A Monte Carlo method was developed to calculate the expected lateral transistor current gain. The calculated β's are in excellent agreement with the measured values.     

硅片键合界面的吸杂效应

本文对硅片直接键合界面的吸杂效应进行了研究，根据键合界面存在晶格缺陷、氧沉积物和微缺陷等事实，提出了键盒介面的吸杂试验，分析了其吸杂效应的机理，给出了吸杂方程。理论计算和实验结果得到了较好的吻合。     

Density functional theory calculations for estimation of gettering sites of C,H, intrinsic point defects and related complexes in Si wafers

Very recently, a C₃H₅ cluster ion implantation technique for proximity gettering has been reported with the low energy of around 10¹⁵/cm² dose without recovery heat treatments. The main feature of this technique is that the gettering efficiency is higher than that by C monomer implantation, even though irradiation defects are too small to clarify by TEM observation. In the present work, we evaluate the binding energies of metal atoms with candidate gettering sites of C, H, intrinsic point defects and related complexes in Si wafers induced by C₃H₅ cluster ion implantation or different methods, for example, H implantation etc. by using density functional theory calculations. In addition to C and H atoms, we consider donor P and O atoms contained in an n- CZ-Si wafer for use in a CMOS image sensor. The simplest complexes of substitutional/interstitial C (C_s/C_i), H_i, P_s, O_i, and incorporated intrinsic point defects (vacancy (V) and self-interstitial Si (I)) by C₃H₅ implantation were also considered. We found that C_s–I (= C_i), C_i–C_i, H_i–I, VH_n (n=1–3), and VO complexes are the best candidates for gettering sites. Gettering by C₃H₅ cluster ion implantation is more effective than that by C monomer implantation due to the formation of VH_n (n=1–3) and H_i–I complexes, which provides more effective gettering sites.     

硅片背面激光损伤的吸杂效果

本文介绍了硅片背面激光损伤吸杂实验,用金相显微镜观察证实了高温退火后激光损伤的热稳定性,研究了激光损伤对氧化层错(OSF)和载流子寿命的影响,用中子活化分析法测出了吸杂效果。     

基于3D定位的光纤棒内部缺陷检测方法

为检测和定位光纤预制棒的内部缺陷并提高精度,提出一种光线追踪实现3D精确定位的线激光旋转扫描检测方法。利用光散射原理和暗场成像技术,成像设备采集光纤棒每个旋转角纵截面上缺陷的散射光;原始图像经过图像预处理和图像分割获取缺陷的二维信息;基于折射定律和光线追踪建立缺陷的精确定位模型,消除光纤棒表面折射带来的成像位置偏差;最后经过坐标转换、三维建模和三维连通域提取实现缺陷在光纤棒内部的3D定位。实验结果表明:120 W像素的工业相机在旋转角步长为0.9°的条件下,对大尺寸的光纤棒内部缺陷检测轴向定位精度为0.28 mm,径向定位精度为1.05 mm,可实现准确、自动化地检测和定位光纤棒的内部缺陷,为光纤棒的质检和指导光纤拉丝提供重要依据。     

Latch-up and image crosstalk suppression by internal gettering [in CMOS]

Internal gettering can be used to reduce crosstalk in imagers and latchup susceptibility in CMOS circuits. The internal gettering process forms defects in the bulk of the silicon wafers that are effective recombination sites for minority carriers in the substrate. Experimental and theoretical results are presented for crosstalk reduction obtained in an area imager. The current gain /spl beta/ of the parasitic lateral n-p-n transistors formed in the substrate in CMOS circuits was considerably lower for the internally gettered wafers. The trigger current needed to initiate latch-up in the n-p-n-p structures increased as 1//spl beta/, in accordance with the theory. A Monte Carlo method was developed to calculate the expected transistor current gain. The calculated /spl beta/s are in excellent agreement with the measured values.     

Determination of the diffusion length of minority charge carriers in a semiconductor from the dynamic nonequilibrium I–V characteristics of MIS structures

A method for determination of the diffusion length L _de of minority charge carriers in a semiconductor from the dynamic nonequilibrium I–V characteristics of metal-insulator-semiconductor (MIS) structures is proposed. The method makes it possible to exclude the effect of bulk generation in a semiconductor on L _de and decrease the temperature of measurements. The possibility of investigating the effective L _de profile in the semiconductor surface layer is shown for the case of nonuniform depth distribution of electrically active defects in a material. The values of L _de in MIS structures on silicon used in integrated-circuit technology are investigated. The effect of the internal gettering of defects in silicon and the irradiation of MIS structures by low-energy electrons (10–30 keV) on the effective L _de profiles in the surface layer of a semiconductor is considered.     

Origin and control of material defects in silicon VLSI technologies: An overview

Very-large-scale integrated circuits impose stringent demands on the quality of silicon wafers required for their fabrication. This paper is an overview of the interrelationships among silicon characteristics, processing, circuit performance, and crystal growth. The relationship between circuit performance and defects in the substrate is described, particularly the effects resulting form the transition from LSI to VLSI. The defect-generation process is then discussed in terms of as-grown silicon characteristics and crystal-growth conditions that control them. The interdependence of material parameters, internal gettering procedures used to reduce the effect of defects on device performance, and resistance to the warpage of silicon wafers is reviewed, with special emphasis on the current and future requirements of bipolar, MOS, and CCD processes.     

热处理气氛对直拉硅单晶中体缺陷的影响

研究了五种不同的热处理气氛对直拉硅中氧沉淀及其诱生缺陷的影响.实验结果表明,经过低-高退火处理的硅片继续在五种不同的气氛中高温退火,氧沉淀会部分溶解,其溶解量与热处理气氛没有明显的关系,但不同气氛中处理的硅片中体缺陷(BMDs)的分布不同.并对此现象的机理进行了讨论,认为热处理气氛影响了硅片中点缺陷的分布从而影响到BMDs的分布.此研究对集成电路生产中内吸杂工艺的保护气氛的选择有指导意义.     

Efficiency-limiting defects in silicon solar cell material

The precipitation rate of intentionally introduced iron during low-temperature heating is studied among a variety of single-crystal and polycrystalline silicon solar cell materials. A correlation exists between the iron precipitation rate and the carrier recombination rate in dislocation-free as-grown material, suggesting that diffusion-length-limiting defects in as-grown material are structural defects which accelerate iron precipitation. Phosphorous diffusion gettering was found to be particularly ineffective at improving diffusion length after intentional iron contamination in materials with high iron precipitation rates. We propose that intragranular structural defects in solar cell silicon greatly enhance transition metal precipitation during cooling from the melt and become highly recombination-active when decorated with these impurities. The defects then greatly impair diffusion length improvement during phosphorus gettering and limit carrier lifetimes in as-grown material.     

Low-angle radar tracking

The problems of low-angle tracking over the earth's surface are explored in the light of rough-surface scattering theory. A detailed model of diffuse scattering is constructed which agrees with available test data and which permits the power distributions in radar coordinates to be estimated. Using this model, the potential performance of various techniques proposed for avoidance of multi-path is evaluated, Several are found effective in maintaining tracks of reasonable accuracy down to one-fourth beamwidth above the horizon, but no generally practical solution to height measurement below that angle appears available.     

Evaluation of the influence of an embedded porous silicon layer on the bulk lifetime of epitaxial layers and the interface recombination at the epitaxial layer/porous silicon interface

Porous silicon plays an important role in the concept of wafer‐equivalent epitaxial thin‐film solar cells. Although porous silicon is beneficial in terms of long‐wavelength optical confinement and gettering of metals, it could adversely affect the quality of the epitaxial silicon layer grown on top of it by introducing additional crystal defects such as stacking faults and dislocations. Furthermore, the epitaxial layer/porous silicon interface is highly recombinative because it has a large internal surface area that is not accessible for passivation. In this work, photoluminescence is used to extract the bulk lifetime of boron‐doped (10¹⁶/cm³) epitaxial layers grown on reorganised porous silicon as well as on pristine mono‐crystalline, Czochralski, p⁺ silicon. Surprisingly, the bulk lifetime of epitaxial layers on top of reorganised porous silicon is found to be higher (~100–115 µs) than that of layers on top of bare p⁺ substrate (32–50 µs). It is believed that proper surface closure prior to epitaxial growth and metal gettering effects of porous silicon play a role in ensuring a higher lifetime. Furthermore, the epitaxial layer/porous silicon interface was found to be ~250 times more recombinative than an epitaxial layer/p⁺ substrate interface (S ≅ 10³ cm/s). However, the inclusion of an epitaxially grown back surface field on top of the porous silicon effectively shields minority carriers from this highly recombinative interface. Copyright © 2013 John Wiley & Sons, Ltd.     

局域铂掺杂寿命控制快恢复二极管的研究

利用质子辐照感生的局域高浓度空位缺陷对样品表面层预生成的铂硅合金中的铂原子进行汲取,形成与感生缺陷分布相似的局域铂分布,首次实现了具有局域铂掺杂的快恢复二极管中的局域寿命控制技术.报告了改变质子注入剂量对二极管反向恢复时间和反向漏电流等参数的影响.结果表明,当辐照剂量较低时,随着辐照剂量的增加,电活性铂浓度不断提高,器件性能不断优化.而辐照剂量增加到一定程度,有效区电活性铂杂质的浓度会趋向饱和,二极管反向恢复时间基本上不再继续减小.     

硅中缺陷的透射电镜观察

随着集成电路制造工艺技术的不断进步,器件线宽不断减小,硅材料中缺陷的危害越来越不可忽视.通过TEM观察了硅中氧沉积、工艺诱生缺陷等并对之进行了分析.     

Solar cells with 11% efficiency on ribbon-growth-on-substrate (RGS) silicon

Solar cells have been prepared on Bayer ribbon-growth-on-substrate (RGS) crystalline silicon. This low-cost material contains a fair amount of impurities and crystal defects whose adverse effect on solar cell performance may be significantly reduced by gettering and bulk passivation treatments. This is demonstrated in solar cells by having a mechanical surface texturization, an aluminium gettering as well as a hydrogen passivation step which led to an open circuit voltage V_oc of 538 mV, a short circuit current density J_sc of 28·5 mA cm⁻², a fill factor of 72·4% and a confirmed record efficiency β of 11·1% (2×2 cm²). Strong improvements in the diffusion length could be observed after the hydrogen treatment. © 1998 John Wiley & Sons, Ltd.     

Surface gettering of background impurities and defects in GaAs wafers

The first data on surface gettering of background impurities and defects from the bulk of single-crystal undoped GaAs(111) wafers are reported. The wafers were 1.6 mm thick, with an initial electron density of (1–3)×10¹⁵ cm^?3 and a mobility of 1500–2000 cm²/(V s) at room temperature. The wafers were cut from single crystals grown by the Czochralski method from a nonstoichiometric As-enriched Ga-As melt. Gettering was carried out during thermal treatment of the wafers in hydrogen at 400–850°C, with the preliminary deposited layer of Y or SiO₂ 1000 Å thick. As a result of gettering, the charge carrier density decreased to 10⁸–10¹⁰ cm^?3, while the mobility increased to 7000 cm²/(V s).     

Improvement of multicrystalline silicon solar cells by a low temperature anneal after emitter diffusion

The influence of an annealing step at about 500 °C after emitter diffusion of multicrystalline solar cells is investigated. Neighboring wafers from a silicon ingot were processed using different annealing durations and temperatures. The efficiency of the cells was measured and detailed light beam induced current measurements were performed. These show that mainly areas with high contents of precipitates near the crucible walls are affected by the anneal. An efficiency increase from 14.5 to 15.4% by a 2 h anneal at 500 °C was observed. The effect seems to be more likely external than internal gettering. Copyright © 2010 John Wiley & Sons, Ltd.