Cascadable current mode instrumentation amplifier

In this paper, a Current Mode Instrumentation Amplifier (CMIA) is presented. The proposed circuit employs two Extra X Current Controlled Current Conveyors (EX-CCCII) and a single grounded resistor. The circuit offers a wide differential-gain bandwidth, wide CMRR bandwidth, and electronically tunable differential gain. The circuit offers cascadibility feature with input impedance of 2.167 kΩ which is very small in comparison to the output impedance of 2.17 MΩ. Simultaneously, a Transresistance (TR) instrumentation amplifier is also obtained with the features of electronically tunable high differential gain and wide bandwidth. The effect of non-idealities of EX-CCCII on the circuit performance is also analysed. The validity of the proposed circuit is verified through PSPICE simulations using 0.25 µm parameters with a supply voltage of ±1.25 V. Also, the circuit is verified by experimental results.     

High-performance current differencing transconductance amplifier and its application in precision current-mode rectification

A CMOS-based circuit for realization of high-performance current differencing transconductance amplifier (CDTA) is demonstrated. The proposed circuit offers the advantages of a wide frequency bandwidth and very small input terminal impedance. The results of circuit simulations and an application example are given to illustrate the advantages of the proposed circuit for precise high-frequency signal rectification.     

一种基于传输线理论的新型GHz共模噪声抑制电路

基于传输线理论提出一种新型GHz宽阻带共模噪声抑制电路。利用双线传输线模型建立奇、偶模等效电路,在宽频带范围内准确预测了该电路结构的性能。实验结果表明:在1.9-4.5GHz频段内共模噪声抑制深度超-10dB,共模阻带相对带宽达81%;在dc-6GHz频段内差模插损小于3dB且差模信号群时延抖动较小,表明该结构可以很好地保证差模信号传输的信号完整性,性能优良。     

激光扫描仪接收系统的峰值保持电路设计

针对激光扫描仪接收系统对信号窄脉宽、高重频、大带宽的设计要求,提出2种保持时间可调的峰值保持电路的设计方法。一种利用跨导型放大电路实现峰值保持,单稳态触发器实现保持时间控制;一种利用FastFET运算放大器和与门延时实现保持时间可控的峰值保持电路。通过软件仿真对2种设计方法进行对比分析,选择更适合激光扫描仪接收系统的跨导型峰值保持电路。经实验验证,该电路可对15 ns脉宽、200 kHz重频和50 MHz带宽的信号有效保持,且保持时间可调。     

Application of optical frequency comb generation with controlled delay circuit for managing the high capacity network system

The generation of optical frequency comb (OFC) with novel controlled delay circuit is presented in this study. The proposed OFC is based on a single laser source which is cascadingly connected with three modulators; all the modulators are tailored by RF signal while incorporating no phase shifter or electrical/optical amplifier. The proposed OFC is used as a source at optical line terminal (OLT) of WDM-PON setup, which serves multiple users with a single laser source making OLT side very cost effective. 41 comb lines with over 40 dB tone to noise ratio and high side mode suppression ratio, least amplitude difference of under 0.3 dB, with cost effective setup is an attractive source for WDM-PON system. The frequency spacing is 32 GHz between OFCG lines which provides enough bandwidth for data transmission, the overall bandwidth provided by this scheme is 1.2 THz. Using DPSK modulation technique across each frequency of OFCG, the controlled delay circuit increases the capacity by factor two, whereas by deploying DQPSK modulation technique, it quadrupled the overall capacity in downlink transmission. Thus, the system offers four times increased capacity ∼1.6 Tbps by deploying state of the art technique for modulation and generating OFC with controlled delay. The average power penalty in the downlink and uplink transmission is 2.5 dBm and 3.13 dBm.     

相控阵雷达天线延时技术的发展

介绍了相控阵雷达天线在大扫描角及大瞬时带宽应用场景下延时补偿技术的发展概况。对天线阵列的波束色散现象以及延时补偿技术对天线方向图的影响进行了分析,并介绍了国内外的一些延时方案。依据延时实现架构,将其分为微波延时、表面声波延时、光延时以及数字延时四类。重点对微波延时的几种不同类型的实现形式进行了描述,并根据微波延时线实现载体的不同,分为GaAs 芯片、射频电缆、印制板和微同轴四种。另外,针对延时拓扑电路进行理论推导分析,说明单延时路径在电路设计上的优势,并分析了基态链路对延时路径的幅度、相位补偿和介质材料对延时量的误差引入。对相控阵雷达天线在大扫描角及大瞬时带宽应用场景下的延时补偿技术研究有一定参考价值。     

一种自适应的混合型无线NoC拓扑结构

针对传统大规模片上网络（Network-on-Chip,NoC）远距离核间多跳通信所带来的高能耗与延时问题,提出了一种基于虚Torus的自适应的混合型无线NoC拓扑结构（VT-AWiNoC）．该结构通过引入链路拥塞测度作为感知参数,基于此采用热点无线链路自动探测与带宽动态分配机制,并设计实现发送器动态分配的控制电路模块,以达到根据不同的通信流量模型,于片内自适应地调整拓扑结构及链路带宽的目的．通过建立混合型无线NoC的延时与功耗评估模型,对该结构的无线NoC进行性能评估．实验结果表明,该自适应拓扑与其它混合型无线NoC相比,在随机流量模型下,网络平均延时降低了16．52～23．27％;在20％的热点流量模型下,包平均能耗节省了39．19％;以真实应用FFT作为基准测试,平均延时降低了17．20％～21．68％,并节省了23．49％的包平均能耗．该结构以较小的面积开销获得了更优的性能．     

A new wideband regulated cascode amplifier with improved performance and its application

This paper presents a new high frequency Regulated Cascode (RGC) amplifier with improved performance. The split-length compensation technique is used to increase both the bandwidth and output impedance, and decrease the input impedance of the conventional RGC. The bandwidth of the proposed RGC amplifier is 5.81 GHz, which is about 2.7 GHz larger than that of simple one. The improved performance of the introduced circuit is achieved with no additional passive element and DC power dissipation. In the paper, output impedance and bandwidth of the proposed circuit are derived by using small signal analysis and have also been compared with the traditional one. In addition, a wideband high performance current mirror is designed in the work as an application of the proposed RGC structure. The bandwidth extension ratio (BWER) of the modified wideband current mirror is 1.37. The proposed circuits are designed by using TSMC 0.18 µm CMOS process and BSIM3 Level 49 device model. The circuits are simulated on Spectre simulator of Cadence to validate the analytical results obtained in the paper.     

一种新型的窄带远寄生小型化微带滤波器

设计了一种新型的窄带远寄生小型化微带滤波器,其远寄生特性通过在带通滤波器之后级联低通来实现。其中带通部分采用两阶带有调节支节的含源-负载非相邻耦合新型电路结构,文中给出其相应的拓扑与耦合系数矩阵,并分析了调节支节的作用;对于用于抑制远端寄生信号的低通滤波器,给出其集总参数原型等效电路。基于此,进行建模与仿真,设计了一款工作于S波段的微带滤波器,实测结果与仿真值、理论值有很好的吻合度,实现指标为中心频率3.93 GHz下的相对带宽8%,寄生远于12 GHz,体积27 mm×10.16 mm×7.45 mm,可以满足实际工程应用的需要。该电路结构新颖,产品尺寸小,设计方法简洁实用,适于推广应用。     

一种基于SIW毫米波的自均衡带通滤波器

提出了一种4阶SIW自均衡带通滤波器。该滤波器具有面积小、易集成等优点。采用三维仿真软件HFSS对电路进行仿真,仿真结果表明,滤波器中心频率为f₀=36.3 GHz, 带宽为1.2 GHz,在60%的通带范围内,群时延变化小于0.02 ns,满足设计指标要求。     

Compact band-notched ultra-wideband antenna with parasitic elements

A compact band-notched ultra-wideband antenna with parasitic elements having small dimensions (12.7 x 21.6 x 1.6 mm) is proposed. With the use of a modified half-circular patch and half-wavelength parasitic lines, the proposed antenna has very wide impedance bandwidth measured at 8.6 GHz. By placing a parasitic loop, a band-notched frequency of 5.16 to 5.98 GHz is achieved. The group delay and transmission loss are measured and discussed.     

A miniature UWB planar monopole antenna with 5-GHz band-rejection filter and the time-domain characteristics

A planar monopole antenna with a staircase shape and small volume (25/spl times/26/spl times/1 mm/sup 3/) is proposed in this paper. With the use of a half-bowtie radiating element, the staircase-shape, and a modified ground plane structure, the proposed antenna has a very wide impedance bandwidth measured at about 11.6 GHz (2.9-14.5 GHz, bandwidth ratio about 1:5) below VSWR 2 including the WLAN band notched in the vicinity of 5 GHz. An omnidirectional radiation pattern is obtained. The group delay which is an indication of linearity between two proposed antennas is less than 1 ns. The electrical characteristics in terms of frequency and time domains and physical ones of the proposed antenna make it attractive for use in ultrawideband (UWB) systems.     

PLL-based BiCMOS on-chip clock generator for very high-speedmicroprocessor

Described is a phase-locked loop (PLL)-based BiCMOS on-chip clock generator (PCG), which is used to generate an internal clock synchronized to a reference clock from outside the chip. In order to obtain a very wide operation bandwidth, it is proposed that the PCG include a compensation circuit for voltage-controlled oscillator (VCO) operation. The compensation circuit varies the oscillation bandwidth of the VCO according to the reference clock frequency, preventing the expected oscillation frequency from being outside the oscillation bandwidth. The PCG is designed and fabricated with 1.0 μm BiCMOS technology, and it achieves an operation bandwidth of 3 to 90 MHz     

Virtual fine delay line using one-stage inverter delay

A virtual fine delay line (VFDL) using only two ring oscillators and counters can cover a wide frequency operation range clock without adding any additional delay line stage. The proposed ring oscillator can easily make a unit delay as a one-stage inverter. The VFDL achieves fine resolution of less than 60 ps and small circuit area with two clock cycles lock-in time.     

一种新的高重频宽带相干激光雷达系统研究

该文提出一种新的同时具有高重复频率和大带宽性能的相干激光雷达系统。该系统基于IQ调制器正交调制技术与带宽合成信号处理技术,使得系统能够同时满足大带宽和高重复频率的要求,解决了传统激光雷达宽带信号调制速度慢的问题。该系统能够生成高重频、大带宽的相干线性调频激光雷达信号,在高分辨距离成像、(逆)合成孔径激光雷达成像、距离分辨的振动测量等方面,具有重要的应用价值。文中阐述了宽带高重复频率调制的原理和方法、基于微波域频率步进的带宽合成信号处理方法,并进行光纤环路实验和自由空间实验。作为演示,该激光雷达系统获得了16.7 kHz重复频率、6 GHz带宽,实现了优于2.5 cm距离向分辨率成像及远距离运动目标逆合成孔径激光雷达成像。实验结果证明了该系统与方法的有效性。     

Radio frequency to emitter coupled logic active detector

An active detector circuit is described which is simultaneously capable of wide radio frequency bandwidth and wide detected bandwidth. In appropriate signal circumstances, the detector is capable of directly producing a signal compatible with emitter coupled logic. The circuit, simulations and measured results are described     

Small Signal Circuit Model of Double Photodiodes

The transmission delay of photogenerated carriers in a CMOS- process- compatible double photodiode (DPD) is analyzed by using device simulation. The DPD small signal equivalent circuit model which includes transmission delay of photogenerated carriers is given. From analysis on the frequency domain of the circuit model the device has two poles. One has the relationship with junction capacitance and the DPD‘s load, the other with the depth and the doping concentration of the N-well in the DPD. Different depth of the Nwell and different area of the DPDs with bandwidth were compared. The analysis results are important to design the high speed DPDs.     

一种新型带宽自动校准有源低通滤波器

为了消除工艺、电压、温度(Process,Voltage,Temperature,PVT)波动及老化对片上集成有源滤波器带宽的影响,提出了一种新型带宽自动校准有源低通滤波器.通过时域采样有源低通滤波器对输入的响应,并与参考电压进行比较,算法电路根据比较结果调整滤波器电容大小,自动搜索到最佳的滤波器带宽.为了消除带宽校准过程中电路响应延迟对校准精度的影响,在时钟及其二分频信号控制下分别执行一次校准,然后通过倍乘和减法运算得到最终对P VT波动、老化及电路响应延迟均不敏感的精确的滤波器带宽.在65 nm互补金属氧化物半导体(Complementary Metal Oxide Semiconductor,CMOS)工艺下设计了一款带宽自动校准有源低通滤波器,仿真结果显示其低频增益为67 dB,在8～50 MHz带宽范围内带宽校准误差在0.7％以内.     

High CMRR wide bandwidth instrumentation amplifier using current controlled conveyors

A novel instrumentation amplifier using only current controlled conveyors (CCCIIs) is proposed. The new circuit with no resistors offers a wide bandwidth, a high CMRR, electronically adjustable gain and a good dynamic range. The proposed circuit also provides simultaneously a high impedance output current. The circuit is also analysed for the non-idealities of conveyors. RSPICE simulation results are included to support the proposed theory.     

A wide frequency range delay line for fast-locking and low power delay-locked-loops

A voltage controlled delay cell with wide frequency range is presented in this paper. The delay-line which is resulted by connecting five series of delay cells generating a wide range of delay from 1.9 to 13.24 ns. It can be used in an analog delay locked loop. The linear characteristic of the circuit with respect to the conventional delay line structures is improved, and a better performance of noise is obtained using differential structure. This circuit is designed by ADS software and TSMC CMOS 0.18 μm technology, with supply voltage 1.8 V. By changing control voltage from 0.335 to 1.8 V in delay line, a wide range of frequency from 75.52 to 917.43 MHz will be covered. Simulation results show that the proposed delay line has power consumption of maximum 3.77 mW at frequency of 75.52 MHz. It also shows that increasing of frequency will reduce power dissipation which is the one of the main characteristics of this novel circuit. Moreover, the delay locked loop which uses these delay cells has a very high lock speed so that the maximum lock time in just five clock cycles.