An Optically Clocked Transistor Array for High-Speed Asynchronous Label Swapping: 40 Gb/s and Beyond

We describe the development of an optically clocked transistor array (OCTA) interface device for label swapping high-speed asynchronous burst optical packets. The OCTA integrates the three critical functions of serial-to-parallel (SP) conversion, parallel-to-serial (PS) conversion, and clock-pulse generation into a simple optoelectronic integrated circuit (OEIC) to create a single-chip interface between the input/output baseband optical labels and a CMOS label processor. The result is a high-performance label swapping solution which is compact and low power. In this paper, a detailed investigation of the design and optimization of the circuit is first performed, followed by testing of device stability under subsystem operating conditions. Finally, demonstrations of single-channel switching speeds allowing greater than 100-Gb/s operation, 40-Gb/s SP and PS conversion with an eight-channel OCTA, and error-free label swapping of 10-Gb/s asynchronous optical packets with a prototype label swapper module are described.     

A vertical-cavity surface-emitting laser appliqued to a 0.8-/spl mu/m NMOS driver

An optoelectronic integrated circuit (OEIC) composed of a vertical-cavity surface-emitting laser (VCSEL) appliqued to an NMOS drive circuit was fabricated to form an optical link from the CMOS chip. A custom NMOS circuit was designed and fabricated through the MOSIS foundry service in a standard 0.8-/spl mu/m CMOS process. InGaAs quantum-well VCSELs were grown, fabricated and tested on an n-type GaAs substrate. Next, the VCSELs underwent a substrate removal technique and were appliqued to the NMOS circuitry. The OEIC was tested at the chip level and showed an electrical to optical conversion efficiency of 1.09 mW/V. Modulation results are also discussed.     

Monolithic integration of GaAs MESFET and InP/InGaAsP 2*2 optical switch

An optical switching OEIC (optoelectronic integrated circuit), consisting of a GaAs MESFET and an InP/InGaAsP 2*2 buried waveguide optical switch, is reported for the first time. Fully monolithic integration is obtained by heteroepitaxial GaAs-on-InP growth and photolithographical interconnection. The combined OEIC allows switching voltages of about 1 V with an extinction ratio of -6 dB.<>     

国外光集成／光电集成技术的发展

ＰＩＣ／ＯＥＩＣ是实现长距离大容量光通信网、光用户网、光交换等关键器件。本文主要介绍了最近两年国外半导体材料技术、工艺技术的进展以及ＰＩＣ／ＯＥＩＣ器件的研制状况。     

A 12-Gb/s high-performance, high-sensitivity monolithic p-i-n/HBTphotoreceiver module for long-wavelength transmission systems

A very high sensitivity, high speed, fiber-pigtailed photoreceiver module is described. The OEIC photoreceiver, composed of a p-i-n photodetector monolithically integrated with an InP-InGaAs heterojunction bipolar transistor (HBT)-based transimpedance amplifier, has measured sensitivity of -20 dBm and -17.6 dBm for data rates of 10 and 12 Gb/s, respectively, at a bit error rate of 1×10^-9. These results are the best ever reported for an OEIC photoreceiver at these speeds. In an optical transmission experiment with a low noise erbium-doped fiber amplifier (EDFA) preceding the OEIC photoreceiver, the measured sensitivities were -35.2 and -32 dBm at 10 and 12 Gb/s respectively     

A proposed OEIC receiver using MESFET photodetector

An optical receiver configuration based on the concept of using a single optically gated metal-semiconductor-fieid-effect transistor (MESFET) to perform the function of a photodetector and preamplifier has been introduced. The proposed optoelectronic integrated circuit (OEIC) receiver has been analyzed theoretically. A simplified noise model of the receiver has also been developed. Results have been presented for an OEIC receiver based on InGaAs MESFET supposed to be fabricated with matured InGaAs-InP MMIC technology. Theoretical results based on a simplistic noise model reveal that the proposed OEIC receiver has superior performance characteristics over the existing optical receivers     

4×4 OEIC switch module using GaAs substrate

A compact 4×4 optical switch module consisting of a monolithic 4-channel OEIC receiver chip, a 4×4 GaAs IC chip, and a 4-channel OEIC transmitter chip has been developed for the first time. The module offers good performance, without an optical loss, a bandwidth of more than 600 MHz, and a crosstalk between neighboring channels of less than -20 dB. It has a good switching and distributive performance for high speed optical input signals of 560 Mbit/s. The switch module is attractive for use in high data-rate optical communication systems, particularly in local area networks, CATV systems, and intra-office links     

1.2 Gbit/s, 52.5 km optical fibre transmission experiment usingOEICs on GaAs-on-InP heterostructure

High-performance, long-wavelength OEICs on a GaAs-on-InP heterostructure were fabricated. For the transmitter OEIC, high-speed operation up to 2.4 Gbit/s was achieved, and a receiver sensitivity as high as -26.0 dBm for a 1.2 Gbit/s NRZ signal was realised for the receiver OEIC. To confirm the usefulness of these OEICs for optical fibre networks, a 1.2 Gbit/s optical fibre transmission experiment was successfully carried out over a 52.5 km span     

A monolithically integrated 1-Gb/s optical receiver in 1-μm CMOStechnology

Results of a monolithically integrated Si optical receiver for applications in optical data transmission and in optical interconnects with wavelengths of 638 and 850 nm are presented. The optoelectronic integrated circuit (OEIC) implementing a vertical p-type-intrinsic-n-type photodiode achieves a data rate of 1 Gb/s for 638 nm with a sensitivity of -15.4 dBm at a bit-error rate of 10^-9 . The sensitivity of this OEIC in a 1.0-μm CMOS technology is improved by at least a factor of four compared to that of published submicrometer OEICs. A 25-THz.Ω effective transimpedance bandwidth product of the implemented amplifier is achieved     

Design, modeling, and characterization of monolithically integratedInP-based (1.55 μm) high-speed (24 Gb/s) p-i-n/HBT front-endphotoreceivers

High-speed, long-wavelength InAlAs/InGaAs OEIC photoreceivers based on a p-i-n/HBT shared layer integration scheme have been designed, fabricated and characterized. The p-i-n photodiodes, formed with the 6000 Å-thick InGaAs precollector layer of the HBT as the absorbing layer, exhibited a responsivity of ~0.4 A/W and a -3 dB optical bandwidth larger than 20 GHz at λ=1.55 μm. The fabricated three-stage transimpedance amplifier with a feedback resistor of 550 Ω demonstrated a transimpedance gain of 46 dBΩ and a -3 dB bandwidth of 20 GHz. The monolithically integrated photoreceiver with a 83 μm p-i-n photodiode consumed a small dc power of 35 mW and demonstrated a measured -3 dB optical bandwidth of 19.5 GHz, which is the highest reported to date for an InAlAs/InGaAs integrated front-end photoreceiver. The OEIC photoreceiver also has a measured input optical dynamic range of 20 dB. The performance of individual devices and integrated circuits was also investigated through detailed CAD-based analysis and characterization. Transient simulations, based on a HSPICE circuit model and previous measurements of eye diagrams for a NRZ 2³¹-1 pseudorandom binary sequence (PRBS), show that the OEIC photoreceiver is capable of operation up to 24 Gb/s     

High-sensitivity BiCMOS OEIC for optical storage systems

A new BiCMOS optoelectronic integrated circuit (OEIC) for applications in advanced optical storage systems is presented. It is optimized with respect to high sensitivity and high speed. The photodiode and the amplifier are monolithically integrated on the same substrate in a commercial 0.8-/spl mu/m BiCMOS process. Analytical expressions for the compensation capacitors and for the bandwidth of the OEIC are derived. Neglecting antireflection coating, no process modifications are necessary to produce the integrated photodiodes. A new offset compensation scheme is implemented in the amplifiers to allow for a small chip area and low power consumption. The OEIC shows a sensitivity of 43.3 mV//spl mu/W in combination with a -3-dB bandwidth of 60.2 MHz.     

A 10 Gb/s hybrid-integrated receiver array module using a planarlightwave circuit (PLC) platform including a novel assembly regionstructure

A planar lightwave circuit (PLC) platform for optoelectronic hybrid integration shows potential for achieving 10 Gb/s operation. It uses AuSn bump-type bonding pads on a silica layer to decrease parasitic capacitance, which limited the CR time constant in the optical chip assembly region, and two-layer electrical wiring to reduce parasitic inductance, which caused resonance in the electrical circuit region. An arrayed receiver module fabricated by integrating a two-channel monolithic opto-electronic integrated circuit (OEIC) chip on the PLC platform demonstrated a 3 dB-bandwidth of 8 GHz in both channels, which is equal to the bandwidth of the OEIC chip. This shows the feasibility of using this PLC platform for multichannel 10 Gb/s operation. Furthermore, this PLC platform can combine the versatile optical circuit functions of a PLC, such as an arrayed-waveguide grating wavelength multiplexer, with the high-speed signal processing function of mature electronic IC circuits. Consequently, this platform is a key device that will lead to high-capacity optical signal processing systems using optical wavelength/frequency routing     

光收发器中光电集成接收芯片的实现

针对应用于850nm光通信中的10/100Mbit/s收发器,提出采用0.5μm标准CMOS工艺对其光接收芯片实现Si基单片集成。整体芯片面积为0.6mm2,共集成了一个双光电二极管的(DPD)光电探测器和一个跨阻前置放大电路,功耗为100mW,并给出了具体的测试性能结果。结果表明,在850nm光照下,光接收芯片带宽达到53MHz,工作速率为72Mbit/s。重点介绍了DPD光电探测器的原理和结构,并给出了相应的制造过程和电路等效模型,对整个光接收芯片进行了多种实用性测试,可以满足系统的性能要求。     

A 40-Gb/s Self-Clocked Bidirectional Serial/Parallel Converter for Asynchronous Label Swapping

A novel scheme for self-clocked bidirectional serial/parallel conversion is proposed with an optically clocked transistor array (OCTA). As a result of its internal clock generation, serial-to-parallel (SP) and parallel-to-serial (PS) conversion capability, the OCTA alone realizes a single-chip low-power interface between input-output high-speed asynchronous burst optical packets and complimentary metal-oxide-semiconductor electronics, thus enabling a compact low-power solution for label swapping of optical packets. An eight-channel OCTA demonstrates self-clocked SP and PS conversion at 40 Gb/s     

Reading light-optoelectronics on indium phosphide

In the future every house could be served by a single optical fibre which will carry basic telephony plus a wide range of broadband services such as video, videophone and high definition TV. The author discusses optoelectronic circuits (OEIC) as cheap optical receiver components. The construction and operation of OEIC are described and the use of them in optical receivers is discussed     

400 Mbit/s transmission experiment using two monolithic optoelectronic chips

A successful optical transmission experiment at 400 Mbit/s was carried out with two OEIC modules over 4 km with an optical power margin of 4 dB. The modules with monolithic LD/driver and PIN/amp ICs were fabricated by a new technique to realise compactness and stability.     

Cascadability study for optical label swapping using synchronous phase modulation

We experimentally investigate the cascadability of optical label swapping using a synchronous phase modulation technique without wavelength conversion in a recirculating loop to emulate multihop networks. We find that the power penalties for both label and payload are below 1 dB at 10/sup -7/ bit-error rate after five hops. We also show that a system penalty can be maintained below 1 dB for an accumulated timing mismatch of 20% of bit period using synchronous phase modulation-based optical label swapping. The results show the potential to save up to 80% of wavelength converters in optical packet switched networks applications.     

OEIC technology and its application to subscriber loops

Recent progress in GaAs- and InP-based optoelectronic integrated circuits (OEICs) for use in optical fiber transmission systems is reviewed. OEIC technology and system demonstrations for short-haul and high-speed transmission are described, and the problems arising in practical applications are discussed. Approaches to resolution of these problems are presented, and future OEIC applications, especially with regard to subscriber loops, are predicted     

10 Gb/s OEIC optical receiver front-end and 3.125 Gb/s PHEMT limiting amplifier

A 10 Gb/s OEIC (optoelectronic integrated circuit) optical receiver front-end has been studied and fab ricated based on the φ-76 mm GaAs PHEMT process; this is the first time that a limiting amplifier (LA) has been designed and realized using depletion mode PHEMT. An OEIC optical receiver front-end mode composed of an MSM photodiode and a current mode transimpedance amplifier (TIA) has been established and optimized by simu lation software ATLAS. The photodiode has a bandwidth of 10 GHz, a capacitance of 3 fF/μm and a photosensitive area of 50×50 μm~2. The whole chip has an area of 1511×666 μm~2. The LA bandwidth is expanded by spiral inductance which has been simulated by software HFSS. The chip area is 1950×1910μm~2 and the measured results demonstrate an input dynamic range of 34 dB (10-500 mVpp) with constant output swing of 500 tnVpp.     

光电子集成器件研究的新进展

本文介绍 OEIC 器件,侧重于基于 GaAs 和 InP 材料的、应用于光纤通信的 OEIC 发射器、接收器和中继器的发展现状、器件性能和各种关键新工艺,并探讨了其发展动向。