A 2 GHz variable gain low noise amplifier in 0.18-μm CMOS

This paper describes a 2 GHz active variable gain low noise amplifier (VGLNA) in a 0.18-μm CMOS process. The VGLNA provides a 50-Ω input impedance and utilizes a tuned load to provide high selectivity. The VGLNA achieves a maximum small signal gain of 16.8 dB and a minimum gain of 4.6 dB with good input return loss. In the high gain and the low gain modes, the NFs are 0.83 dB and 2.8 dB, respectively. The VGLNA’s IIP3 in the high gain mode is 2.13 dBm. The LNA consumes approximately 4 mA of current from a 1.8-V power supply.     

2 to 23 GHz BiFET low noise amplifier design flow and implementations in 0.25 μm SiGe BiCMOS technology

Two BiFET LNAs are here reported, implemented in a 0.25 μm BiCMOS technology from ST Microelectronics. First of them, dedicated to WCDMA standard, depicts a 15.5 and 2.85 dB, S₂₁ and noise figure (NF), respectively, under 2 mA current consumption. The second realization operates at 23 GHz for Mini-Link application. It provides a 14 dB gain and 7 dB at 22 GHz NF for an 8.2 mA current consumption under 2.5 V. Both circuits were designed according to a design flow, here depicted, based on input matching, NF and gain optimisation. A large part of the article also deals with high frequency layout considerations. Indeed useful techniques dedicated to integrated microstrip waveguides and RF inter-connections are proposed based on 3D electromagnetic field simulations.     

A high speed, low voltage to high voltage level shifter in standard 1.2 V 0.13 μm CMOS

The design of a high speed, low voltage to high voltage level shifter in a digital 1.2 V, 0.13 μm CMOS technology is presented. The topology uses two differentially switched cascoded transistor ladders. The output signal has an offset of two times the nominal supply voltage of the used technology with respect to the input signal. Oxide stress and hot carrier degradation is minimized since all transistors of the level shifter operate within the voltage limits imposed by the design rules of a mainstream CMOS technology.     

An ultra low power consumption millimeter-wave voltage controlled oscillator in a 65 nm CMOS-SOI technology

This paper presents an ultra low power consumption 65 GHz LC-VCO dedicated to wireless high data rate applications. It is designed in a 65 nm CMOS SOI process, which improves passive devices behavior. The proposed VCO achieves a frequency tuning range (FTR) of 9.7 % and a phase noise of ?110.86 dBc/Hz at 10 MHz of the carrier. All integrated passive components (including transmission lines and a transformer-based balun) are modeled using advanced electromagnetic (EM) field solvers. The power consumption of the proposed VCO is as low as 1.1 mW when biased by a 0.8-V supply voltage. The FoM of this millimeter wave circuit, whose core occupies a silicon footprint of only 0.047 mm², is ?184.07 dBc/Hz.     

A self-duty-cycled 7.2–8.5 GHz IR-UWB receiver for low power and low data rate applications

A self-duty-cycled non-coherent impulse radio-ultra wideband receiver targeted at low-power and low-data-rate applications is presented. The receiver is implemented in a 130 nm CMOS technology and works in the 7.2–8.5 GHz UWB band, which covers the IEEE 802.15.4a and 802.15.6 mandatories high-band channels. The receiver architecture is based on a non-coherent RF front-end (high gain LNA and pulse detector) followed by a synchronizer block (clock and data recovery or CDR function and window generation block), which enables to shut down the power-hungry LNA between pulses to strongly reduce the receiver power consumption. The main functions of the receiver, i.e. the RF front-end and the CDR block, were measured stand-alone. A maximum gain of 40 dB at 7.2 GHz is measured for the LNA. The RF front-end achieves a very low turn-on time (<1 ns) and an average sensitivity of ?92 dBm for a 10^?3 BER at a 1 Mbps data rate. A root-mean-square (RMS) jitter of 7.9 ns is measured for the CDR for a power consumption of 54 µW. Simulation results of the fully integrated self-duty-cycled 7.2–8.5 GHz IR-UWB receiver (that includes the measured main functions) confirm the expected performances. The synchronizer block consumes only 125 µW and the power consumption of the whole receiver is 1.8 mW for a 3% power duty-cycle (on-window of 30 ns).     

A 1.8 V low power 5 Gbps PMOS-based LVDS output driver with good return loss performance

This paper presents a novel design topology of a 5 Gbps PMOS-based low voltage differential signaling (LVDS) voltage mode output driver. The topology is designed to meet the requirements of low power consumption and high data rates applications. The driver consists of an output stage and a pre-driver stage where the driver’s swing and common-mode output voltage are set. The pre-driver and the output stage consume only 13.1 mW of power at 5 Gbps speed while operating from a 1.8 V voltage supply. Further, the design achieved ?21 dB return loss performance at DC. The driver was extracted and simulated using Mentor Graphics CAD tools and implemented in 180 nm CMOS technology. The output signal is fully compliant with the LVDS standard output swing and common-mode voltage specifications.     

Ultra low power frequency divider for 2.45 GHz ZigBee frequency synthesizer

An ultra low power CMOS frequency divider whose modulus can be varied from 481 to 496 is presented. It has been customized to be used in 2.45 GHz Integer-N PLL frequency synthesizers utilized in ZigBee standard. Its based on swallow divider that replaces the swallow counter by a simple digital circuit in order to reduce power consumption and design complexity. Also a low power and high speed divide-by-7/8 is presented. Post layout simulation results exhibit 420 μW power consumption for 4 bit frequency divider in 2.45 GHz ISM frequency band that proves 40 % reduction compared to same previous works. All of the circuits have been designed in 0.18 μm TSMC CMOS technology with a single 1.8 V DC voltage supply.     

A 6-bit 2.5-GS/s flash ADC using comparator redundancy for low power in 90 nm CMOS

A 2.5 GS/s flash ADC, fabricated in 90 nm CMOS utilizes comparator redundancy to avoid traditional power, speed and accuracy trade-offs. The redundancy removes the need to control comparator offsets, allowing the large process-variation induced mismatch of small devices in nanometer technologies. This enables the use of small-sized, ultra-low-power comparators with clock-gating capabilities in order to reduce the power dissipation. The chosen calibration method enables an overall low-power solution and measurement results show that the ADC dissipates 30 mW at 1.2 V. With 63 comparators, the ADC achieves 3.9 effective number of bits.     

CMOS implementation of a 1.6 GHz low voltage low phase noise quadrature output frequency synthesizer with automatic amplitude control

This article presents the design of a 1.2 V CMOS low phase noise quadrature output frequency synthesizer (FS) to be used for a GPS tuner application. Special reference is made to the design of a wide tuning range quadrature output voltage-controlled oscillator which is equipped with an automatic amplitude controller. It exhibits a phase noise response of less than −115 dBc/Hz at an offset of 1 MHz from the carrier and has a tuning range of over 36%. The effect of the automatic amplitude control is shown to improve phase noise at high oscillation frequencies and its noise has a negligible effect on the phase noise response even at low offset frequencies from the carrier. Preliminary analysis is presented showing the negligible effect of a DC–DC converter on the spurious level of the FS, included to permit the use of low sensitivity varactors. Design guidelines for reducing both the loop noise and the AM-to-PM conversion factors of the oscillator are also given. The design was made using the STMicroelectronics 0.13 μm HCMOS9-RF technology design kit.     

Reduced comparator high speed low power ADC using 90 nm CMOS technology

The increasing demand of high speed and low power ADC in serial links, gigabit ethernet, high speed instruments in general and communication technologies such as ultra wide band systems in particular has put tremendous pressure on efficient design of data converters. Presently flash ADC is the architecture of choice with sampling frequency ranging from 2 to 40 GS/s with 4–6 bit resolution, where speed and low resolution is required. However we are forced to compromise between performance and complexity when such ADC is used. In this paper a single channel high speed low power CMOS based 4-bit ADC using reduced comparator and multiplexer based architecture is presented. For improving the conversion rate, both the analog (comparator array) and the digital (encoder) parts of the proposed ADC are fully modified and the architecture uses only 4 comparators instead of 15 as used in conventional flash ADC, thereby saving considerable amount of power. The proposed 4-bit 2 GS/s ADC is designed and simulated in Tanner tools with 1.2 V supply voltage using 90 nm CMOS technology. HSpice simulation result of proposed architecture shows a power dissipation of 23 mW with INL and DNL errors between ±0.4 LSB and ±0.34 LSB respectively. ENOB and SNDR for the proposed architecture are 3.72 and 24.2 respectively.     

Providing trust in wireless sensor networks using a bio-inspired technique

Wireless Sensor Networks (WSNs) are becoming more and more spread and both industry and academia are focusing their research efforts in order to improve their applications. One of the first issues to solve in order to achieve that expected improvement is to assure a minimum level of security in such a restrictive environment. Even more, ensuring confidence between every pair of interacting nodes is a critical issue in this kind of networks. Under these conditions we present in this paper a bio-inspired trust and reputation model, called BTRM-WSN, based on ant colony systems aiming at providing trust and reputation in WSNs. Experiments and results demonstrate the accuracy, robustness and lightness of the proposed model in a wide set of situations.     

Fourth-Order Complex-Lag PWVD for Multicomponent Signals with Application in ISAR Imaging of Maneuvering Targets

The fourth-order complex-lag polynomial Wigner–Ville distribution (PWVD) is extended to generate a high resolution time–frequency distribution for multicomponent signals in this paper. For signals with polynomial phase up to order four, the interferences between different components are reduced by the convolution in the frequency domain of the complex-lag PWVD. The complex-lag PWVD can achieve optimal energy concentration, and it is used in the inverse synthetic aperture radar (ISAR) imaging of maneuvering targets, where high quality instantaneous ISAR images are obtained. Simulated results demonstrate the effectiveness of the method.     

A low power CMOS phase-switching prescaler for 1.8–2.4 GHz wireless communications

A divide-by-31/32 phase switching prescaler with a simple divide-by-4 multi-phase ring counter is presented. By using this divide-by-4 unit, a low power consumption is obtained while a wide range operation is maintained. Fabricated with a standard 0.18 μm CMOS technology, the prescaler can work properly from 1.8 to 3.1 GHz with a maximum current dissipation of 1.3 mA from a 1.8 V supply voltage. It can cover most of wireless communication standards in 1.8/1.9 GHz and 2.4 GHz bands.     

Conception approach of access control in heterogeneous information systems using UML

The development of the information systems should answer more and more to the problems of federated data sources and the problems with the heterogeneous distributed information systems. The assurance of data access security realized in the cooperative information systems with loose connection among local data sources is hard to achieve mainly for two reasons: the local data sources are heterogeneous (i.e. data, models, access security models, semantics, etc.) and the local autonomy of systems does not allow to create a global integrated security schema. The paper proposes to use one common set of access control concepts to support the access control management in security of heterogeneous information systems. The UML (Unified Modeling Language) concepts can be used to define and implement the most popular access control models, such as DAC, MAC or RBAC. Next, the concepts derived from different models can be joined to use one common approach comprehensible for each administrator of each cooperative information system in the federation.     

A 11.2 mW 48–62 GHz Low Noise Amplifier in 65 nm CMOS Technology

In this paper, a wideband low noise amplifier (LNA) for 60 GHz wireless applications is presented. A single-ended two-stage cascade topology is utilized to realize an ultra-wideband and flat gain response. The first stage adopts a current-reused topology that performs the more than 10 GHz ultra-wideband input impedance matching. The second stage is a cascade common source amplifier that is used to enhance the overall gain and reverse isolation. By proper optimization of the current-reused topology and stagger turning technique, the two-stage cascade common source LNA provides low power consumption and gain flatness over an ultra-wide frequency band with relatively low noise. The LNA is fabricated in Global Foundries 65 nm RFCMOS technology. The measurement results show a maximum \(S_{21}\) gain of 11.4 dB gain with a \(-\)3 dB bandwidth from 48 to 62 GHz. Within this frequency range, the measured \(S_{11}\) and \(S_{12}\) are less than \(-\)10 dB and the measured DC power consumption is only 11.2 mW from a single 1.5 V supply.     

A low spur,low jitter 10-GHz phase-locked loop in 0.13-μm CMOS technology

This paper presents a 10-GHz low spur and low jitter phase-locked loop(PLL).An improved low phase noise VCO and a dynamic phase frequency detector with a short delay reset time are employed to reduce the noise of the PLL.We also discuss the methodology to optimize the high frequency prescaler's noise and the charge pump's current mismatch.The chip was fabricated in a SMIC 0.13-μm RF CMOS process with a 1.2-V power supply.The measured integrated RMS jitter is 757 fs(1 kHz to 10 MHz);the phase noise is-89 ...     

A low spur, low jitter 10-GHz phase-locked loop in 0.13-μm CMOS technology

This paper presents a 10-GHz low spur and low jitter phase-locked loop (PLL).An improved low phase noise VCO and a dynamic phase frequency detector with a short delay reset time are employed to reduce the noise of the PLL.We also discuss the methodology to optimize the high frequency prescaler's noise and the charge pump's current mismatch.The chip was fabricated in a SMIC 0.13-μm RF CMOS process with a 1.2-V power supply.The measured integrated RMS jitter is 757 fs (1 kHz to 10 MHz); the phase noise is -89 and-118.1 dBc/Hz at 10 kHz and 1 MHz frequency offset,respectively; and the reference frequency spur is below -77 dBc.The chip size is 0.32 mm2 and the power consumption is 30.6 mW.     

A new worm propagation threat in BitTorrent: modeling and analysis

Peer-to-peer (P2P) networking technology has gained popularity as an efficient mechanism for users to obtain free services without the need for centralized servers. Protecting these networks from intruders and attackers is a real challenge. One of the constant threats on P2P networks is the propagation of active worms. Recent events show that active worms can spread automatically and flood the Internet in a very short period of time. Therefore, P2P systems can be a potential vehicle for active worms to achieve fast worm propagation in the Internet. Nowadays, BitTorrent is becoming more and more popular, mainly due its fair load distribution mechanism. Unfortunately, BitTorrent is particularly vulnerable to topology aware active worms. In this paper we analyze the impact of a new worm propagation threat on BitTorrent. We identify the BitTorrent vulnerabilities it exploits, the characteristics that accelerate and decelerate its propagation, and develop a mathematical model of their propagation. We also provide numerical analysis results. This will help the design of efficient detection and containment systems.     

State-dependent packet scheduling for QoS routing in a dynamically changing environment

The packet scheduling in router plays an important role in the sense to achieve QoS differentiation and to optimize the queuing delay, in particular when this optimization is accomplished on all routers of a path between source and destination. In a dynamically changing environment a good scheduling discipline should be also adaptive to the new traffic conditions. We model this problem as a multi-agent system in which each agent learns through continual interaction with the environment in order to optimize its own behaviour. So, we adopt the framework of Markov decision processes applied to multi-agent system and present a pheromone-Q learning approach which combines the Q-multi-learning technique with a synthetic pheromone that acts as a communication medium speeding up the learning process of cooperating agents.     

A 1.1 V 6.2 mW,wideband RF front-end for 0 dBm blocker tolerant receivers in 90 nm CMOS

This paper presents the design and implementation of a low power, highly linear, wideband RF front-end in 90 nm CMOS. The architecture consists of an inverter-like common gate low noise amplifier followed by a passive ring mixer. The proposed architecture achieves a high linearity in a wide band (0.5–6 GHz) at very low power. Therefore, it is a suitable choice for software defined radio (SDR) receivers. The chip measurement results indicate that the inverter-like common gate input stage has a broadband input match achieving S11 below −8.8 dB up to 6 GHz. The measured single sideband noise figure at an LO frequency of 3 GHz and an IF of 10 MHz is 6.25 dB. The front-end achieves a voltage conversion gain of 4.5 dB at 1 GHz with 3 dB bandwidth of more than 6 GHz. The measured input referred 1 dB compression point is +1.5 dBm while the IIP3 is +11.73 dBm and the IIP2 is +26.23 dBm respectively at an LO frequency of 2 GHz. The RF front-end consumes 6.2 mW from a 1.1 V supply with an active chip area of 0.0856 mm².