Numerical modeling and optimization of laser soldering for Micro‐USB electric connector

The laser soldering process was introduced in Micro‐USB electronic packaging in this paper. Numerical modeling and analysis was used for laser process parameter design, because experimental measurements of peak temperature and soldering stress are expensive and often intractable. Accurate knowledge of the residual stress and distortion is a prerequisite for the reliability of the electric connector. The present work proposes a three‐dimensional transient heat transfer model of Micro‐USB package laser soldering process. The calculated thermal cycles and distribution are subsequently used to calculate the distortion and thermal stresses. Meanwhile, the effect of process parameters on residual stress and pin distortion was discussed, and the tensile strength, microstructure, and residual stresses of laser soldering were tested. It can be concluded that the proper laser soldering parameters and power can improve the mechanical property of solder joints on Micro‐USB connector. Copyright © 2014 John Wiley & Sons, Ltd.     

计及焊层疲劳影响的风电变流器IGBT模块热分析及改进热网络模型

针对不同疲劳寿命时期对风电变流器绝缘栅双极型晶闸管(IGBT)模块结温的影响,分析焊层在不同脱落度下的IGBT模块热阻变化规律,并建立考虑热阻变化的改进热网络模型。首先,依据风电机组变流器IGBT模块的结构和材料属性,建立三维有限元热-结构耦合分析模型,对基板焊层和芯片焊层在不同脱落度下IGBT模块结温和热应力的分布规律进行仿真分析。其次,确定不同焊层脱落度下其热阻增量值,并建立IGBT模块改进热网络模型。最后,将三维有限元模型和改进热网络模型的结温计算结果进行对比分析,验证了所提的改进热网络模型的有效性。     

电子线路板热分析方法研究

采用Flotherm软件对电子线路板进行热可靠性建模分析,通过仿真分析可知:PCB布线对PCB传热有重要影响,因此建模时应尽量考虑;内部到外部热阻小的发热器件可当作简单方块处理;集成芯片在知悉内部热阻的情况下,尽量采用双热阻模型.根据以上推论对某电子线路板进行Flotherm建模与计算,并将计算结果与实验测试数据进行比...     

芯片封装参数对功率模块热特性影响的研究

由于温度分布不均匀以及封装中各层材料之间的热膨胀系数不同,使功率模块在工作中产生交变的热应力,造成焊层疲劳、键合线脱落等失效形式,因此研究模块的热特性尤为重要。热的测量是电力电子系统中最困难的工作之一,对封装结构进行电-热-力精确的仿真分析,能够准确了解对器件不同部位的温度、应力分布。采用基于电-热-力多物理场的有限元仿真,研究了封装材料、封装参数和封装结构对功率器件的温度、热阻、热应力这些热特性的影响,为优化封装设计,最终提高功率模块可靠性提供了一定的参考。     

基于增强现实技术的BGA芯片辅助定位

提出了一种基于增强现实技术的BGA芯片的辅助定位方法。该方法通过图像处理,将定位过程中的待焊芯片用一个重构的透明芯片的图像代替,使操作者在监视屏上可同时看见电路板上的焊盘和BGA芯片底部的焊球,定位操作的直观性和准确性都有了很大的提高。采用VC＋＋与HALCON相结合的方法实现了该系统,实验表明该方法达到了预期的效果。     

Investigation and minimization of underfill delamination in flip chip packages

A generalized plane strain condition is assumed for an edge interfacial crack between die passivation and underfill on an organic substrate flip chip package. C4 solder bumps are explicitly modeled. Temperature excursions are treated as loading conditions. The design factors studied include underfill elastic modulus, underfill coefficient of thermal expansion (CTE), fillet height, and die overhang. Varying underfill modulus and CTE produces a different stress field at underfill/die passivation interface, different stress intensity factor (SIF), and phase angle (/spl psi/) even under the same loading condition. The baseline case uses underfill with elastic modulus of 6 GPa, CTE of 36 ppm//spl deg/C and fillet height equal to half die thickness. Four more cases involving underfill material properties are investigated by varying elastic modulus between 3 and 9 GPa, and by varying CTE between 26 and 46 ppm//spl deg/C. The effect of fillet height is also studied by assuming no fillet and full fillet, i.e., fillet height equal to die thickness. Finally, two cases concerning the influence of die overhang, defined as the nominal distance between outermost solder joint and die edge, are investigated. Fracture parameters, including energy release rate (G) and phase angle (/spl psi/), are evaluated as a function of dimensions. Underfill material properties (elastic modulus and CTE), fillet configuration, and die overhang can be optimized to reduce the risk of underfill delamination in flip chip or direct chip attach (DCA) applications.     

高压大功率芯片封装的散热研究与仿真分析

以工作电压为70V、输出电流为9A的高压大功率芯片TO-3封装结构为例，首先基于热分析软件Flo THERM建立三维封装模型，并对该封装模型的热特性进行了仿真分析。其次，针对不同基板材料、不同封装外壳材料等情况开展对比分析研究。最后研究封装体的温度随粘结层厚度、功率以及基板厚度的变化，得到一个散热较优的封装方案。仿真验证结果表明，基板材料和封装外壳的热导率越高，其散热效果越好，随着粘结层厚度以及芯片功率的增加，芯片的温度逐渐升高，随着基板厚度的增加，芯片温度降低，当基板材料为铜、封装外壳为BeO，粘结层为AuSn20时，散热效果最佳。     

计及内部材料疲劳的压接型IGBT器件 可靠性建模与分析

大功率压接型IGBT器件更适合柔性直流输电装备应用工况,必然对压接型绝缘栅极晶体管（IGBT）器件可靠性评估提出要求。提出计及内部材料疲劳的压接型IGBT器件可靠性建模方法,首先,建立单芯片压接型IGBT器件电-热-机械多物理场仿真模型,通过实验验证IGBT仿真模型的有效性;其次,考虑器件内部各层材料的疲劳寿命,建立单芯片压接型IGBT器件可靠性模型,分析了单芯片器件各层材料薄弱点;最后针对多芯片压接型IGBT器件实际结构,建立多芯片压接型IGBT器件多物理场仿真模型,分析器件应力分布,并对各芯片及多芯片器件故障率进行计算。结果表明,压接型IGBT器件内部的温度、von Mises 应力分布不均,最大值分别位于IGBT芯片和发射极钼层接触的轮廓线边缘;多芯片器件内应力分布不均会导致各芯片可靠性有所差异,边角位置处芯片表面应力最大,可靠性最低。     

Fast 3D thermal simulation of power module packaging

This paper presents a thermal model that uses a Fourier series solution to the heat equation to carry out transient 3D thermal simulation of power device packaging. The development and implementation of this physics‐based method is described. The method is demonstrated on a stacked 3D multichip module. The required aspects of 3D heat conduction are captured successfully by the model. Compared with previous thermal models presented in literature, it is fast, accurate and can be easily integrated with an inverter circuit simulator to model realistic converter load cycles. Copyright © 2012 John Wiley & Sons, Ltd.     

基于2-D彩色图像模型的PCB焊点检测方法研究

提出了一种基于2-D彩色图像模型的PCB焊点检测方法.首先,基于3色LED环形结构光源和彩色数字相机的图像采集子系统获取的彩色PCB图像,分析了片式晶片元器件焊点表面信息与其焊点图像色彩分布规律,建立了片式晶片良品焊点类型的焊点检测模型,其次,给出了反映可接受焊点图像中心感兴趣区域(ROI)色彩分布规律的灰度曲线图.在...     

IGBT模块失效机理及状态监测研究综述

随着电力电子系统性能要求的不断提高,绝缘栅双极晶体管（insulated gate bipolar transistor,IGBT）模块不仅要拥有高功率密度,还要具有良好的热-机械性能,以提高其可靠性。首先介绍了IGBT模块的主要失效模式,对封装中键合线和焊料层失效机理进行了详细阐述,重点介绍了IGBT模块健康状态监测,分别对结温、键合线与焊料层健康状态监测及其量化评估研究进展进行了详细分析。最后,对降低热-机械应力以提高整机可靠性设计和运行工况下在线监测研究的发展前景进行了展望。     

风电-光伏-光热联合发电系统的模糊多目标优化模型

为实现以风光为代表的高比例新能源在电力系统中的友好并网,集成风电场、光伏电站和光热电站为多电源系统,提出风电-光伏-光热联合发电系统的模糊多目标优化模型。利用含储热光热电站良好的可调度性与可控性,为系统提供旋转备用与爬坡支撑,削减风光出力随机性与不确定性,从而实现其削峰填谷功能。以系统并网效益最大和输出功率方差最小为目标建立优化模型,通过定义目标隶属度函数将确定性模型模糊化,并采用最大满意度指标法将多目标优化模型转化为单目标优化模型,利用基于差分进化的粒子群DE-PSO(particle swarm optimization based on differential evolution)算法进行求解。算例系统仿真结果表明:模糊多目标优化能充分利用光热电站优势实现整体运行效果最优,从而验证了所提优化运行模型的可行性和有效性。     

异步电机转子三维温度场及热应力场研究

针对异步电机转子温度场及热应力场难以测量,转子导条经常发生断裂故障等问题,以一台Y100L-2型电机为研究对象,采用有限元法建立电机转子三维导热模型.在理论分析的基础上,结合实验测量,对模型边界条件进行确定,并以此为基础对转子温度场和热应力场进行仿真研究.研究结果显示电机转子温升的高低直接影响热应力大小,温升越高,热应力越大;转子导条热应力的分布在各个方向上并不均匀;在负载电机转子温度较高时,不均匀的热应力将直接影响电机寿命,是转子导条断裂的主要原因之一;负载时,整个转子热应力最大值出现在导条与端环连接处,说明该处最容易发生断裂故障,这一结论也与电机实际情况相符;导条法线方向正热应力要大于剪切热应力,与国内外相关研究结果比较,仿真结果在分布规律上基本一致.     

大功率模块电源的分析和设计

采用模块电源构成电源分布式系统,可提高电源系统供电可靠性和供电质量。采用移相控制零电压开关PWM全桥变换器拓扑和三维叠层封装结构,完成了28V/36A输出的模块电源。建立了模块电源的寄生参数模型,提出改善模块电源电磁兼容性能的措施。对模块电源进行电气性能测试,给出电气性能测试结果。对模块电源进行了损耗分析,运用Flotherm软件对模块电源进行热仿真分析,给出了温度分布仿真结果。三维叠层封装结构实现了良好的热设计。     

计及热惯性及光热电站的综合能源系统优化

传统热电联供联合调度中,燃气轮机(gas turbine, GT)机组“以热定电”的运行模式极大地限制了系统的调峰能力。提出一种光热电站(concentrating solar power, CSP)参与供热的综合能源系统优化调度方法,并在调度过程中考虑供热网络和供热区域的热惯性。首先,构建光热电站参与电热联合系统调节模型,发挥其供能潜力。其次,构建热网管道和建筑物集群的热惯性模型,挖掘其虚拟储能的特性,在满足各项约束的条件下实现两类热惯性与CSP的协同优化运行。在仿真分析中构建5种对比场景,验证了热网和供热区域的热惯性与CSP储热系统(thermal energy storage, TES)相互协调在提升系统运行经济性、风电上网率和降低系统碳排放方面的有效性。     

A 14b 150 MS/s 140 mW 2.0 mm2 0.13µm CMOS A/D converter for software‐defined radio systems

This work proposes a 14 b 150 MS/s CMOS A/D converters (ADC) for software‐defined radio systems requiring simultaneously high‐resolution, low‐power, and small chip area at high speed. The proposed calibration‐free ADC employs a wide‐band low‐noise input sample‐and‐hold amplifier (SHA) along with a four‐stage pipelined architecture optimizing scaling‐down factors for the sampling capacitance and the input trans‐conductance of amplifiers in each stage to minimize thermal noise effect and power consumption. A signal‐insensitive 3‐D fully symmetric layout achieves a 14 b level resolution by reducing a capacitor mismatch of three MDACs. The prototype ADC in a 0.13µm 1P8M CMOS technology demonstrates a measured differential nonlinearity (DNL) and integral nonlinearity within 0.81LSB and 2.83LSB at 14 b, respectively. The ADC shows a maximum signal‐to‐noise‐and‐distortion ratio of 64 and 61 dB and a maximum spurious‐free dynamic range of 71 and 70 dB at 120 and 150 MS/s, respectively. The ADC with an active die area of 2.0mm² consumes 140 mW at 150 MS/s and 1.2 V. Copyright © 2010 John Wiley & Sons, Ltd.     

Reliability of Lead-Free BGA Assembly: Correlation Between Accelerated Ageing Tests and FE Simulations

In 2006, lead was banished in electrical and electronic equipment in Europe, but the reliability of lead-free technology is not yet well known. This paper describes a methodology using experiments and FE simulations that allow us to assess acceleration coefficients (ACs) and to predict assembly lifetimes. Two accelerated ageing tests have been conducted on lead-free ball grid array (BGA) assemblies. During the ageing test, cycles-to-failure have been accurately determined by an event detector from AnaTech. The 3-D nonlinear finite-element model of the BGA assembly has been designed and built using ANSYS software. Thermomechanical simulations have been carried out on this model to compute the strain energy density (SED) that dissipated in the solder joints during the thermal cycles. Then, the correlation between the experimentations and the simulations has allowed us to assess the ACs of two different kinds of thermal cycles and, thus, the cycles-to-failure for another test.      

Flex Cracking of Multilayer Ceramic Capacitors Assembled With Pb-Free and Tin–Lead Solders

In this paper, an experimental study was conducted to study susceptibility to flex cracking of multilayer ceramic capacitors (MLCCs), in which a comparison was made between identical samples which were assembled using either Pb-free (Sn3.0Ag0.5Cu) or eutectic tin-lead (Sn37Pb) solder. Flex testing was performed on MLCCs with different sizes (1812 and 0805) and on different dielectric materials (C0G and X7R) obtained from three different manufacturers. Experimental results showed that MLCCs mounted on printed circuit boards (PCBs) with Pb-free solder crack less with board flexing than those mounted on boards with eutectic tin-lead solder. For 1812-size MLCCs assembled with tin-lead solder, the PCB strain at 10% failure ranged between 1700 and 2000 microstrains. The PCB strain at 10% failure for 1812-size MLCCs assembled with Pb-free solder varied between 2300 and 9600 microstrains, depending on the MLCC manufacturer. C0G MLCCs are more resistant to flex cracking than X7R MLCCs. Out of 96 samples tested, none of the C0G MLCCs showed evidence of flex cracking up to the maximum strain level on board of about 137 000 microstrains. In contrast, in the case of X7R MLCCs, from the same manufacturer, assembled with tin-lead solder, 94 out of 96 capacitors failed.     

Interaction Effect of Voids and Standoff Height on Thermomechanical Durability of BGA Solder Joints

This paper documents simulation studies on the interactive effect of standoff height and void volume on the thermomechanical durability of ball-grid-array solder joints using a 3-D viscoplastic finite element analysis. Surface Evolver software was used to find the optimized shape of the solder joints and standoff height by minimizing the surface energy as voids with different sizes were placed in solder balls. A global–local modeling approach was then utilized to model the thermomechanical durability of voided solder joints. Void-area-fraction ranges of 14%–40% were analyzed. A nonmonotonic behavior of durability versus void area fraction was observed. The results showed that, if the void is completely inside the solder ball and has no interface with the boundaries of the joint, it does not have a detrimental effect and even improves the durability as the void size increases. However, voids located at the interface of the solder joint and copper pads were found very detrimental to durability. Factors such as load bearing area, stress concentration factor, and overall compliance of the structure were found responsible for the nonmonotonic behavior of the joints. An analytical micromechanics approach was used to calculate the compliance of the structure, and a nonmonotonic trend in phase with the durability trend was observed. The stress concentration factor also showed the same nonmonotonic trend. The rise of these two factors for the void interfacing with copper pads in addition to the decreased-load-bearing-area effect resulted in a drastic decrease in durability.      

计及置信容量的光热电站储热容量优化配置

为探索光热电站的容量价值,文中基于光热电站的容量置信度和度电成本,提出一种光热电站集热面积和储热容量优化方法。文中建立光热电站发电效率模型和经济性模型,基于序贯蒙特卡洛方法计算发电系统可靠性,使用粒子群算法计算光热电站置信容量,研究太阳倍数和储热时长分别对光热电站容量置信度和度电成本的影响;并以容量置信度和度电成本作为优化目标,使用加权理想点法建立目标优化函数、熵权法确定指标权重值,对太阳倍数和储热时长进行优化。以西北某地区光热规划为例,使用该地区实际太阳辐照资源数据建立模型,发现随着太阳倍数和储热时长的增加,容量置信度单调递增,而度电成本呈先降后升的趋势,可优化得到约束条件下最佳太阳倍数和储热时长。