可实现DVS的单电感双输出降压型直流-直流转换器

设计了一款单电感双输出(SIDO)的降压型直流-直流转换器,一个输出电压可以进行动态电压转换,在0.725～1.2V直接变化,另一输出电压可实现1.2V和1.8V,两路输出最大可实现500mA负载电流。转换器根据负载的不同在脉冲宽度调制(PWM)和脉冲频率调制(PFM)之间自动切换。采用死区时间自适应调整的技术来提高系统的转换效率,分段开关则用来降低输出端毛刺。基于TSMC0.25μm CMOS工艺,测试结果证明该系统输出电压纹波低、毛刺小,系统峰值效率可达90%。     

一种低功耗、高稳定性的无片外电容线性稳压器

本文研究并设计了输出电压3.3V,最大输出电流为150mA的CMOS无片外电容的低压差线性稳压器(Off-chipcapacitor-free Low-dropout Voltage Regulator,LDO).该LDO采用了NMC(Nested Miller Compensation)频率补偿技术保证了系统的稳定性.另外,采用大电容环路和SRE(Slew Rate Enhancement)电路抑制输出电压的跳变,改善了瞬态响应.电路采用了低功耗设计技术.采用CSMC 0.5μm CMOS混合信号工艺模型仿真表明:整个LDO的静态电流仅为3.8μA;最差情况下的相位裕度约为88.50;在5V工作电压下,当负载电流在1μs内从150mA下降到1mA时,输出电压变化仅为140mV;在负载电流150mA的情况下,当电源电压在5μs内从3.5V跳变至5V时,输出电压变化也仅为140mV.     

一种新的应用于开关电容DC/DC转换器的补偿电路

采用Chartered 0.35μm CMOS工艺,设计实现了输入电压范围2.7～5.5 V,负载电流高达200mA的降压式开关电容型DC/DC转换器.为了在整个输入电压和负载电流范围内稳定输出电压,并且提高输出电压精确度,在对开关电容转换器环路建模分析后,提出了一个新的应用于开关电容DC/DC转换器的频率补偿电路.该...     

一种基于LC振荡器的高效隔离式DC-DC开关电源

设计了一种基于片上变压器的隔离式DC-DC开关电源。通过分析影响开关电源能量转换效率的因素,设计了一种应用于隔离式DC-DC开关电源的LC振荡器,提高了隔离式开关电源的整体效率。采用CSMC 0.35 μm BCD工艺进行设计,并将该振荡器应用于隔离式开关电源。隔离式开关电源的输入电压为3.3 V,输出电压为5 V。仿真结果表明,时钟振荡频率为180 MHz,应用该振荡器的DC-DC开关电源最大输出电流达到62 mA,转换效率提高到35.6%。     

一种无片外电容LDO的稳定性分析

电路如果存在不稳定性因素,就有可能出现振荡。本文对比分析了传统LDO和无片电容LDO的零极点,运用电流缓冲器频率补偿设计了一款无片外电容LDO,电流缓冲器频率补偿不仅可减小片上补偿电容而且可以增加带宽。对理论分析结果在Cadence平台基上于CSMC0.5um工艺对电路进行了仿真验证。本文无片外电容LDO的片上补偿电容仅为3pF,减小了制造成本。它的电源电压为3.5～6 V,输出电压为3.5 V。当在输入电源电压6 V时输出电流从100μA到100mA变化时,最小相位裕度为830,最小带宽为4.58 MHz     

一种简洁高效的单片DC-DC转换器软启动电路

设计了一款用于单片集成DC-DC:转换器的简洁而高效的软启动电路,该电路消除了芯片启动时的过压冲击并有效地降低了浪涌电流.在误差放大器一输入端采用不同时段接入若干电容的方法使输出电压分段线性上升.Spectre仿真表明,对一个输入电压为5 V,输出电压为2.5 V的降压芯片在电感峰值电流为330 mA时,浪涌电流从830 mA降低到550mA,并且持续时间特别短,同时过充电压被完全消除.此电路简单可行,适用于各种DC-DC降压芯片.     

一种用于PCRAM的嵌入式片内电容电荷泵

针对相变存储器小片内电容和低功耗的应用要求,在分析传统升压式电容电荷泵局限性的基础上,提出了一种应用于相变存储单元的嵌入式片内电容电荷泵。该电容电荷泵无需电感器件,存储单元不会受到高电磁干扰,采用了特殊的互补型电荷泵升压方法,具有电源效率高、瞬态响应速度快、面积小、电容可片内集成等优点。在SMIC 40 nm标准CMOS工艺条件下,对设计的嵌入式片内电容电荷泵进行仿真。结果表明,负载电流变化为250 mA/μs时,输出瞬态响应时间为374.2 ns,电源转换效率可达81.65%,静态电流为7.22 μA,输出能力为4 V/2.5 mA。     

一种峰值电流模两相交错Buck转换器

提出了一种降压型两相交错直流转换器。与传统单相转换器相比,该两相转换器具有输出纹波低、瞬态响应快、重载效率高等特性,适合为多核处理器供电。采用峰值电流模式,基于公共电压反馈回路及峰值电流信息,实现两相支路电流的均衡。依据负载电流范围自动选择运行支路个数,保证转换器在整个负载范围内具有高转换效率。基于TSMC 0.18 μm工艺进行设计,电源电压范围为2.7~5 V,支持330 nH~1 μH的小封装电感,最大电流驱动能力为5 A。仿真结果显示,在输入电压为4.2 V,输出电压0.9 V的条件下,整个负载范围内转换器的峰值效率为86%,最大稳态输出纹波低于2 mV,在5 A/1 μs负载瞬变条件下,负载调整率不超过28 mV/A。     

一种快速瞬态响应的无片外电容型LDO电路设计

本文基于SMIC65 nm工艺,设计了一款快速瞬态响应的无片外电容型低压差线性稳压器(low dropout regulator,LDO).采用高增益跨导结构(OTA)的误差放大器,利用局部共模反馈结构(CFRFC),增加了放大器跨导率,提高了放大器的直流增益.同时,引入一个由电容耦合电流镜构成的瞬态检测电路,取代了传统LDO电路中的大电容,便于检测输出的跳变,增大对功率管的充放电能力,提高了环路瞬态响应速度,降低LDO环路的上/下冲电压.缓冲级采用了带电压负反馈的源级跟随器,在一定的静态功耗下,提高了动态电流,将次级点推到更高的频率,提高了电路相位裕度.仿真结果表明,输入电压为2～3 V时,该电路输出为1.2 V,最大负载电流为100 mA;当负载电流在0～100 mA时,LDO输出的最大过冲电压和欠冲电压为23 mV和27 mV,并且在低频时有较高的电源抑制比.     

一种快速瞬态响应的无片外电容LDO

设计了一种快速瞬态响应的无片外电容低压差线性稳压器(LDO)。采用具有摆率增强作用的缓冲级电路,可以在不额外增加静态电流的同时检测输出端电压,在负载瞬间变化时增大功率器件栅极电容的充放电电流。缓冲级电路还引入了简单的负反馈技术,增加了环路的相位裕度。采用SMIC 180 nm的CMOS工艺进行设计和仿真。仿真结果表明,当输入电压为1.4~5 V时,该LDO的输出电压为1.2 V,最大负载电流为300 mA; 负载电流在1 mA和300 mA间变化时,最大过冲电压为76.5 mV,响应时间仅为1.5 μs。     

A Multistage Interleaved Synchronous Buck Converter With Integrated Output Filter in 0.18 μm SiGe Process

The design and analysis of a fully integrated multistage interleaved synchronous buck dc-dc converter with on-chip filter inductor and capacitor is presented. The dc-dc converter is designed and fabricated in 0.18 mum SiGe RF BiCMOS process technology and generates 1.5 V-2.0 V programmable output voltage supporting a maximum output current of 200 mA. High switching frequency of 45 MHz, multiphase interleaved operation, and fast hysteretic controller reduce the filter inductor and capacitor sizes by two orders of magnitude compared to state-of-the-art converters and enable a fully integrated converter. The fully integrated interleaved converter does not require off-chip decoupling and filtering and enables direct battery connection for integrated applications. This design is the first reported fully integrated multistage interleaved, zero voltage switching synchronous buck converter with monolithic output filters. The fully integrated buck regulator achieves 64% efficiency while providing an output current of 200 mA.     

A monolithic current-mode CMOS DC-DC converter with on-chip current-sensing technique

A monolithic current-mode CMOS DC-DC converter with integrated power switches and a novel on-chip current sensor for feedback control is presented in this paper. With the proposed accurate on-chip current sensor, the sensed inductor current, combined with the internal ramp signal, can be used for current-mode DC-DC converter feedback control. In addition, no external components and no extra I/O pins are needed for the current-mode controller. The DC-DC converter has been fabricated with a standard 0.6-/spl mu/m CMOS process. The measured absolute error between the sensed signal and the inductor current is less than 4%. Experimental results show that this converter with on-chip current sensor can operate from 300 kHz to 1 MHz with supply voltage from 3 to 5.2 V, which is suitable for single-cell lithium-ion battery supply applications. The output ripple voltage is about 20 mV with a 10-/spl mu/F off-chip capacitor and 4.7-/spl mu/H off-chip inductor. The power efficiency is over 80% for load current from 50 to 450 mA.     

Full on-chip and area-efficient CMOS LDO with zero to maximum load stability using adaptive frequency compensation

A full on-chip and area-efficient low-dropout linear regulator (LDO) is presented. By using the proposed adaptive frequency compensation (AFC) technique, full on-chip integration is achieved without compromising the LDO's stability in the full output current range. Meanwhile, the use of a compact pass transistor (the compact pass transistor serves as the gain fast roll-off output stage in the AFC technique) has enabled the LDO to be very area-efficient. The proposed LDO is implemented in standard 0.35 μm CMOS technology and occupies an active area as small as 220×320 μm~2, which is a reduction to 58% compared to state-of-the-art designs using technologies with the same feature size. Measurement results show that the LDO can deliver 0-60 mA output current with 54 μA quiescent current consumption and the regulated output voltage is 1.8 V with an input voltage range from 2 to 3.3 V.     

A 233-MHz 80%-87% efficient four-phase DC-DC converter utilizing air-core inductors on package

We demonstrate an integrated buck dc-dc converter for multi-V/sub CC/ microprocessors. At nominal conditions, the converter produces a 0.9-V output from a 1.2-V input. The circuit was implemented in a 90-nm CMOS technology. By operating at high switching frequency of 100 to 317 MHz with four-phase topology and fast hysteretic control, we reduced inductor and capacitor sizes by three orders of magnitude compared to previously published dc-dc converters. This eliminated the need for the inductor magnetic core and enabled integration of the output decoupling capacitor on-chip. The converter achieves 80%-87% efficiency and 10% peak-to-peak output noise for a 0.3-A output current and 2.5-nF decoupling capacitance. A forward body bias of 500 mV applied to PMOS transistors in the bridge improves efficiency by 0.5%-1%.     

Frequency tunable low ripple and fast response on-chip DC–DC converter for DVFS

Dynamic voltage and frequency scaling (DVFS) is an efficient method to reduce the power consumption in system on-chip. To support DVFS, multiple supply voltages are generated based on different work load frequencies and currents using on-chip DC–DC voltage converter. In this paper a frequency tunable multiple output voltage switched capacitor based dc–dc converter is presented. An analog to digital converter and phase controller is used in the feedback to change the switching frequency and duty cycle of the converter. An input voltage of 1.8 V is converted to 0.6 and 0.8 V for low and high signal frequency respectively. The proposed 2-phase switched capacitor architecture with gain setting of 1:2 is designed with the 90 nm technology. An output ripple of 45 mV is observed and the maximum transient response time of the converter is 17.3 ns (= 58 MHz).     

High-accuracy current sensing circuit with current compensation technique for buck–boost converter

A novel on-chip current sensing circuit with current compensation technique suitable for buck–boost converter is presented in this article. The proposed technique can sense the full-range inductor current with high accuracy and high speed. It is mainly based on matched current mirror and does not require a large proportion of aspect ratio between the powerFET and the senseFET, thus it reduces the complexity of circuit design and the layout mismatch issue without decreasing the power efficiency. The circuit is fabricated with TSMC 0.25 µm 2P5M mixed-signal process. Simulation results show that the buck-boost converter can be operated at 200 kHz to 4 MHz switching frequency with an input voltage from 2.8 to 4.7 V. The output voltage is 3.6 V, and the maximum accuracy for both high and low side sensing current reaches 99% within the load current ranging from 200 to 600 mA.     

单芯片高效率降压DC-DC芯片设计

介绍了一种单芯片DC-DC转换器IC设计与电路实现,其特点是宽负载电流条件下具有较高效率.芯片的设计和仿真基于上华0.6 μm双阱、混合信号CMOS工艺.芯片的工作电压范围为2～5 V,可以使用于一般的电池供电设备.对提高芯片效率的方法以及效果进行了详细的讨论分析.仿真结果表明,芯片可以产生稳定的1.8 V输出电压,并提供大于500mA的输出电流,而纹波电压却小于5 mV.芯片可以获得93.8%的最大转换效率,而且在5～500 mA的负载电流范围内,效率始终高于86.2%.     

一种PWM/PFM的同步整流升压转换器设计

文章介绍了一种工作在PWM/PFM双模式下的同步整流升压转换器设计,剖析电路的工作原理,采用0.35μmn阱CMOS工艺流片。通过SPECTRE仿真器模拟,结果显示该电路在输出负载电流是1mA时,输入电源电压0.9V启动,在关机模式下静态电流小于1μA,输出电压调节范围2.5V～5V,输入电压1V～5V,固定频率1.4MHz,允许采用外形扁平而小巧的电感器和陶瓷电容器,从而极大地节省了PCB板的面积,效率高达92%,可以从单节AA电池产生3.3V/260mA的输出或从双节AA电池产生3.3V/600mA的输出。该器件包括驱动管NMOS和同步整流管PMOS,具有斜率补偿的电流模式PWM设计,减少了外部元件的数量。抗振铃电路通过在不连续工作模式下对电感器进行阻尼来抑制EMI。在轻负载情况下工作在PFM模式,重负载情况下工作在PWM模式。     

GaAs switched capacitor DC-to-DC converter

A switched capacitor DC-to-DC negative converter fabricated in GaAs MESFET technology is introduced in this paper. The converter has an oscillator that runs at 250 kHz, and requires two external capacitors, 0.1 and 1 μF. The converter runs off a wide range of supply voltage, 2 to 10 V, and has a typical output impedance of 75 Ω. A typical open circuit voltage conversion efficiency of 99.6% is achieved. The circuit can be integrated with other GaAs circuits to provide an on-chip negative supply. Measured, simulated and analytical results are introduced in this paper     

A 1.0 V differential VCO in 0.13 μm CMOS technology

A differential complementary LC voltage controlled oscillator(VCO) with high Q on-chip inductor is presented.The parallel resonator of the VCO consists of inversion-mode MOS(I-MOS) capacitors and an on-chip inductor.The resonator Q factor is mainly limited by the on-chip inductor.It is optimized by designing a single turn inductor that has a simulated Q factor of about 35 at 6 GHz.The proposed VCO is implemented in the SMIC 0.13μm 1P8M MMRF CMOS process,and the chip area is 1.0×0.8 mm~2.The free-running frequency is from 5.73 to 6.35 GHz.When oscillating at 6.35 GHz,the current consumption is 2.55 mA from a supply voltage of 1.0 V and the measured phase noise at 1 MHz offset is -120.14 dBc/Hz.The figure of merit of the proposed VCO is -192.13 dBc/Hz.