A programmable gain amplifier with a DC offset calibration loop for a directconversion WLAN transceiver

A high-linearity PGA(programmable gain amplifier) with a DC offset calibration loop is proposed.The PGA adopts a differential degeneration structure to vary voltage gain and uses the closed-loop structure including the input op-amps to enhance the linearity.A continuous time feedback based DC offset calibration loop is also designed to solve the DC offset problem.This PGA is fabricated by TSMC 0.13μm CMOS technology.The measurements show that the receiver PGA(RXPGA) provides a 64 dB gain range with a step of 1 dB,and the transmitter PGA(TXPGA) covers a 16 dB gain.The RXPGA consumes 18 mA and the TXPGA consumes 7 mA (I and Q path) under a 3.3 V supply.The bandwidth of the multi-stage PGA is higher than 20 MHz.In addition,the DCOC(DC offset cancellation) circuit shows 10 kHz of HPCF(high pass cutoff frequency) and the DCOC settling time is less than 0.45μs.     

CMOS linear-in-dB VGA with DC offset cancellation for direct-conversion receivers

A low-power high-linearity linear-in-dB variable gain amplifier(VGA) with novel DC offset calibration loop for direct-conversion receiver(DCR) is proposed.The proposed VGA uses the differential-ramp based technique,a digitally programmable gain amplifier(PGA) can be converted to an analog controlled dB-linear VGA. An operational amplifier(OPAMP) utilizing an improved Miller compensation approach is adopted in this VGA design.The proposed VGA shows a 57 dB linear range.The DC offset cancellation(DCOC) loop is based on a continuous-time feedback that includes the Miller effect and a linear range operation MOS transistor to realize high-value capacitors and resistors to solve the DC offset problem,respectively.The proposed approach requires no external components and demonstrates excellent DCOC capability in measurement.Fabricated using SMIC 0.13μm CMOS technology,this VGA dissipates 4.5 mW from a 1.2 V supply voltage while occupying 0.58 mm~2 of chip area including bondpads.In addition,the DCOC circuit shows 500 Hz high pass cutoff frequency(HPCF) and the measured residual DC offset at the output of VGA is less than 2 mV.     

64dB二进制增益控制带有DCOC和AB类buffer的可编程增益放大器

本文设计了一款二进制增益控制,带有直流失调消除（DCOC）电路以及AB类输出buffer的可编程增益放大器。该放大器采用二极管连接负载的差分放大器结构,电路性能对温度变化及工艺偏差不敏感。根据测试,通过6位数字信号控制,电路可以实现-2dB ~ 61dB的增益动态范围,增益步长1dB,步长误差在 0.38dB以内,最小3dB带宽为92MHz,在低增益模式下,IIP3可达17dBm,1dB压缩点可达5.7dBm。DCOC电路可使该放大器应用于直接变频接收机中,而AB类输出buffer则降低了电路的静态功耗。     

应用于多模接收机的低功耗可编程增益放大器

针对多模接收机的应用,提出了引入一条闭环伪通路技术结构的可编程增益放大器,在保持一定的线性度及噪声性能的基础上,以较低的功耗实现较大的带宽.该电路增益步长为2 dB,增益变化范围1～39 dB.电路中内嵌了直流失调消除模块防止直流漂移引起的阻塞.芯片采用SMIC 0.13 μm 1P8M RF CMOS工艺实现.测试结...     

65nm工艺下20Gb/s无电感限幅放大器设计与分析

本文设计了一款能工作在20Gb/s速率下的无电感限幅放大器。限幅放大器包括三各部分：带直流失调消除的输入匹配级,增益级和输出驱动级。本设计采用交叉负反馈技术,使得放大器在获得高带宽的同时拥有较为平坦的频率响应。直流失调消除环路中增加了误差放大器来保证直流失调消除效果。放大器在65纳米工艺下成功流片,芯片面积为0.45 × 0.25平方毫米（不包括PAD）,测试结果显示放大器的差分增益为37dB,带宽为16.5GHz,在高达26.5GHz的频率内Sdd11和Sdd22分别小于-16dB和-9dB。除了驱动级,整个放大器在1.2V的电源电压下消耗50mA的电流。     

Wideband CMOS variable gain amplifier with decibel-linear gain control characteristic

This paper presents a wideband variable gain amplifier (VGA) featuring a decibel-linear gain control characteristic. The decibel-linear gain control function is realized using two VGA cells and a control signal converter. The bandwidth is extended using cascode architecture together with active inductive load. To achieve small parasitic and low area, direct current (DC) coupling is adopted in the circuit while a DC offset cancellation circuit (DCOC) is introduced to cancel the DC offset. Fabricated in a 0.18 μm complementary metal oxide semiconductor (CMOS) process, the chip occupies an area of 0.53 mm × 0.48 mm (including pads) and draws a total current of 9 mA from a 1.8 V supply. The measurement results show that the gain of the VGA varies from -40 dB to 18 dB while the control voltage varies from 0 to 1.8 V, resulting in a total gain control range of 58 dB. The 3 dB bandwidth of the VGA is larger than 260 MHz at maximum gain.     

A 36 V Programmable Instrumentation Amplifier With Sub-20 $mu$V Offset and a CMRR in Excess of 120 dB at All Gain Settings

A 36 V capable programmable gain instrumentation amplifier (PGA) is presented with sub-20 $muhbox{V}$ offset, sub-0.2 $muhbox{V}/^{circ}{hbox{C}}$ offset drift and a common-mode rejection (CMRR) that exceeds 120 dB at all gain settings without any trimming. It is the first 36 V capable precision PGA implemented in a high-voltage CMOS process, which, in addition, incorporates several additional functions, such as the detection of input and output fault conditions, provisions for improving system-level settling time and an input switch network. All op-amps used in the PGA employ chopper stabilization with a notch filter that removes chopping glitches, leading to low offset and drift and no $1/f$ noise. The PGA has a total of 22 gain steps (binary steps between 1/8 to 128, each with an optional multiplying factor of 1 or 1.375) with better than 0.1% gain accuracy, $≪$0.001% nonlinearity and sub-2 ppm/C gain drift. The input switch network, in addition to acting as a 2-channel multiplexer, also enables various system-level diagnostic features. The PGA is implemented in a 0.35 $muhbox{m}$ CMOS process with a 36 V extension, has a 3.6 $times$ 2.4 mm chip area and consumes a total quiescent current of 3 mA.      

一种基于BiFET工艺的高输入阻抗运算放大器

针对CMOS运算放大器存在的输入失调电压高、噪声性能差等问题,提出了一种基于双极结型场效应晶体管(BiFET)工艺的高输入阻抗运算放大器。采用P沟道JFET差分对作为输入级,实现了pA量级的极低输入偏置电流/失调电流和nV/Hz量级的极低输入噪声电压谱密度。采用双极晶体管构成的共集-共射增益级和互补推挽输出级,实现了100 dB的开环增益、10 V/μs的输出电压转换速率和10 MHz的带宽。该运算放大器适用于对微弱模拟信号的采集和放大。     

A low power mixed signal DC offset calibration circuit for direct conversion receiver applications

A low power mixed signal DC offset calibration(DCOC) circuit for direct conversion receiver applications is designed.The proposed DCOC circuit features low power consumption,fast settling time and a small die area by avoiding the trade-off between loop response time and the high pass frequency of the DCOC servo loop in conventional analog DCOC systems.By applying the proposed DC offset correction circuitry,the output residue DC offset voltages are reduced to less than 38 mV and the DCOC loop settling time is less than 100μs.The DCOC chip is fabricated in a standard 0.13-μm CMOS technology and drains only 196μA from a 1.2-V power supply with its chip area of only 0.372×0.419 mm~2.     

InGaP/GaAs heterojunction bipolar transistor and RF power amplifier reliability

Electrothermal stress on advanced InGaP/GaAs heterojunction bipolar transistors (HBTs) was carried out experimentally. It showed a long-term stress-induced base current instability and a decrease in the DC current gain. A class-AB RF power amplifier (PA) was also considered to study the stress effect on the amplifier’s RF performance. The SPICE Gummel–Poon (SGP) model parameters were extracted from the pre- and post-stress HBT data and used in Cadence SpectreRF simulation. The amplifier’s post-stress RF characteristics, such as the output power and power-added efficiency (PAE), remained almost unchanged even though the post-stress HBT’s DC current gain had dropped to 73.6% of its initial value.     

GaInP/GaAs HBTs for high-speed integrated circuit applications

The use of GaInP/GaAs heterojunction bipolar transistors (HBTs) for integrated circuit applications is demonstrated. The discrete devices fabricated showed excellent DC characteristics with low V_ce offset voltage and very low temperature sensitivity of the current gain. For a non-self-aligned device with a 3-μm×1.4-μm emitter area, f_T was extrapolated to 45 GHz and f_max was extrapolated to 70 GHz. The measured 1/f noise level was 20 dB better than that of AlGaAs HBTs and comparable to that of low-noise silicon bipolar junction transistors, and the noise bump (Lorentzian component) was not observed. The fabricated gain block circuits showed 8.5 dB gain with a 3-dB bandwidth of 12 GHz, and static frequency dividers (divide by 4) were operable up to 8 GHz     

一种Doppler/FMCW双模式雷达模拟基带设计

基于55 nm CMOS工艺,设计了一种应用于24 GHz Doppler/ FMCW双模式雷达系统的模拟基带电路(ABB)。低通滤波器由两个改进型Tow-Thomas二阶节级联而成,实现了增益和带宽独立调节。采用一种基于7 bit可编程电流型数模转换器(IDAC)的两步逐次逼近型直流失调消除电路(SAR DCOC),可在Doppler模式10~600 Hz极低中频条件下,对混频器输出和基带自身直流失调进行消除。在IDAC和两级运放中混合使用BJT管,减小闪烁噪声,获得良好的低频噪声性能。后仿真结果表明,在2.5 V电源电压、模拟基带消耗电流4.9 mA下,两种模式增益范围均为6~62 dB,最大线性输入幅度(IP 1 dB)为10 dBm;62 dB增益时,Doppler模式、FMCW模式下的噪声系数分别小于42 dB、27 dB。蒙特卡罗仿真结果表明,当输入存在400 mV、200 mV直流失调时,基带输出直流失调仅为21.3 mV和16.4 mV。     

一种用于射频接收机的模拟基带电路

设计了一种无线传感网射频接收机中的基带电路,包括滤波器和可变增益放大器(VGA)。滤波器采用5阶切比雪夫型有源RC结构,带宽可调,具有自动调谐功能,能适应制造工艺与环境条件的变化。VGA由2阶放大器与1阶缓冲器组成,每阶放大器拥有一个DCOC环路,用来抑制直流失调,减小增益瞬态变化的稳定时间。采用TSMC 130 nm CMOS工艺进行流片。测试结果表明,供电电压为1.3 V时,滤波器能够涵盖8种带宽。自动调谐模块的调谐范围为±20%,调谐精度为2%。接收机的IIP3为28 dBm,双边带噪声为3 dB。VGA的增益变化范围为-12~56 dB。当VGA的增益瞬态变化量为32 dB时,DCOC的稳定时间小于100 ns。     

A Current-Feedback Instrumentation Amplifier With 5 $mu{hbox{V}}$ Offset for Bidirectional High-Side Current-Sensing

This paper describes an instrumentation amplifier for bidirectional high-side current-sensing applications. It uses a multipath indirect current-feedback topology. To achieve low offset, the amplifier employs a combination of chopping and auto-zeroing in a low frequency path to cancel the offset of a wide-band amplifier in a high frequency path. With a 60 kHz chopper clock and a 30 kHz auto-zero clock, this offset-stabilization scheme results in an offset voltage of less than 5 $mu{hbox{V}}$ , a CMRR of 143 dB and a common-mode input voltage range from 1.9 to 30 V. The input voltage-to-current (V-I) converters required by the current-feedback topology are implemented with composite transistors, whose transconductance is determined by laser-trimmed resistors. This results in a less than 0.1% gain inaccuracy. The instrumentation amplifier was realized in a 0.8 $mu{hbox{m}}$ BiCMOS process with high voltage transistors, and has an effective chip area of 2.5 ${hbox{mm}}^{2}$ .      

A compact low noise operational amplifier for a 1.2 μm digitalCMOS technology

A compact low noise operational amplifier using lateral p-n-p bipolar transistors in the input stage has been fabricated in a standard 1.2 μm digital n-well CMOS process. Like their n-p-n counterparts in p-well processes, these lateral p-n-p transistors exhibit low 1/f noise and good lateral β. The fabricated op amp has an area of only 0.211 mm² with E_n=3.2 nV/√(Hz), I_n=0.73 pA/√(Hz), E_n and I_n 1/f noise corner frequencies less than 100 Hz, a -3 dB bandwidth greater than 10 MHz with a closed loop gain of 20.8 dB, a minimum PSRR (DC) of 68 dB, a CMRR (DC) of 100 dB, a minimum output slew rate of 39 V/μs, and a quiescent current of 2.1 mA at supply voltages of ±2.5 V. The operational amplifier drives a 1 kΩ resistive load to 1 V peak-to-peak at 10 MHz and has been used as a versatile building block for mixed-signal IC designs     

一种低功耗混合信号直流失调消除电路

设计了一种应用于直接变频接收机的低功耗混合信号直流失调消除(DCOC)电路。该电路采用混合信号的方式消除直流失调电压,避免了传统模拟域直流失调消除系统环路响应速度与高通带宽之间的折中,具有功耗低、建立时间快、面积小等优点。采用该DCOC后,直接变频接收机的输出剩余直流失调电压小于37mV,直流失调消除环路的建立时间小于200μs。电路采用0.13μm CMOS工艺实现,芯片尺寸为0.372mm×0.419mm,工作于1.2V电源电压时,消耗电流仅为196μA。     

High-temperature characterisation and analysis of leakage-current-compensated,low-power bandgap temperature sensors

This paper presents a low-power, high-performance current-feedback instrumentation amplifier (CFIA) for portable bio-potential sensing applications. Noise analysis is performed to assign an optimized current for the input stage of the amplifier. Analysis on selecting nested chopping frequencies is performed, further reducing 1/f noise and the residual offset. Enhanced power efficiency is achieved by sharing cascode branches and using a Class-AB output stage. Through these methods, a good balance between noise performance and other parameters such as output ripples and power consumption of the ripple reduction feedback loop (RRFL) is achieved. The amplifier is developed using a 1-poly 6-metal 0.18 μm CMOS process. Three gain stages with a gain-boosting input stage provide a low-frequency, open-loop gain >250 dB. When configured to a closed-loop gain of 60 dB, the amplifier achieves a noise voltage density of 18 \({\text{nV}}/\sqrt {{\text{H}}z}\) and a 1/f noise corner of 3 Hz. With a current of 75 μA and a supply voltage of 3.3 V, a CMRR of 110 dB and a PSRR of 120 dB are achieved, with an average input offset of about 6.5 μV. The amplifier achieves a state-of-art noise efficiency factor of 4.2. Practical application of the CFIA is demonstrated with an in vivo electrocardiogram detection.     

A 60-dB linear VGA with novel exponential gain approximation

A CMOS variable gain amplifier (VGA) that adopts a novel exponential gain approximation is presented.No additional exponential gain control circuit is required in the proposed VGA used in a direct conversion receiver.A wide gain control voltage from 0.4 to 1.8 V and a high linearity performance are achieved. The three-stage VGA with automatic gain control (AGC) and DC offset cancellation (DCOC) is fabricated in a 0.18-μm CMOS technology and shows a linear gain range of more than 58-dB with a linearity error less than ± 1 dB. The 3-dB bandwidth is over 8 MHz at all gain settings. The measured input-referred third intercept point (IIP3) of the proposed VGA varies from -18.1 to 13.5 dBm, and the measured noise figure varies from 27 to 65 dB at a frequency of 1 MHz. The dynamic range of the closed-loop AGC exceeds 56 dB, where the output signal-to-noise-and-distortion ratio (SNDR) reaches 20 dB. The whole circuit, occupying 0.3 mm2 of chip area, dissipates less than 3.7 mA from a 1.8-V supply.     

A MOS switched-capacitor instrumentation amplifier

Describes a precision switched-capacitor sampled-data instrumentation amplifier using NMOS polysilicon gate technology. It is intended for use as a sample-and-hold amplifier for low level signals in data acquisition systems. The use of double correlated sampling technique achieves high power supply rejection, low DC offset, and low 1/f noise voltage. Matched circuit components in a differential configuration minimize errors from switch channel charge injection. Very high common mode rejection (120 dB) is obtained by a new sampling technique which prevents the common mode signal from entering the amplifier. This amplifier achieves 1 mV typical input offset voltage, greater than 95 dB PSRR, 0.15 percent gain accuracy, 0.01 percent gain linearity, and an RMS input referred noise voltage of 30 /spl mu/V/input sample.     

Integrated Amplifier Circuits for 60 GHz Broadband Telecommunication

Wide frequency bandwidth has been internationally allocated for unlicensed operation around the oxygen absorption frequency at 60 GHz. A power amplifier and a low noise amplifier are presented as building blocks for a T/R-unit at this frequency. The fabrication technology was a commercially available 0.15 m gallium arsenide (GaAs) process featuring pseudomorphic high electron mobility transistors (PHEMT). Using on-wafer tests, we measured a gain of 13.4 dB and a +17 dBm output compression point for the power amplifier at 60 GHz centre frequency when the MMIC was biased to 3 volts V_dd. At the same frequency, the low noise amplifier exhibited 24 dB of gain with a 3.5 dB noise figure. The AM/AM and AM/PM characteristics of the power amplifier chip were obtained from the large-signal S-parameter measurement data. Furthermore, the power amplifier was assembled in a split block package, which had a WR-15 waveguide interface in input and output. The measured results show a 12.5 dB small-signal gain and better than 8 dB return losses in input and output for the packaged power amplifier.