集成电路互连线电迁移测试方法与评价

介绍了研究集成电路互连线电迁移的两种方法：加速寿命试验和移动速度试验。对加速寿命试验进行了分析和评价。分析表明,加速寿命试验方法存在高应力条件与正常工作条件下互连线电迁移中金属离子扩散机制不同、BLACK方程的使用范围有限、受试件特殊结构影响和电阻温度系数TCR随温度变化等问题。介绍了一种改进方法。详细介绍了移动速度试验,指出了其在互连线电迁移研究中的应用。     

铜互连可靠性分析

在简要的对铜互连和铝互连进行了比较后,本文从材料特性和集成工艺两方面讨论了铜互连和铝互连对可靠性的不同影响,并详细的分析了一个关键的可靠性失效机理:电迁移(包括通孔损耗和连线损耗).最后讨论了影响铜电迁移的一些工艺要素,如通孔、阻挡层和覆盖层.     

MCM-C基板上的多层互连及厚膜电阻的可靠性研究

重点研究了MCM-C基板中多层互连和厚膜电阻的可靠性.试验采用温度应力和电应力的双应力加速寿命试验.试验发现,温度小于180℃时互连失效在MCM-C基板失效中占主要地位,膜电阻失效相对互连失效可忽略不计.在温度高于180℃时膜电阻失效将起较大作用,即膜电阻比互连温度加速系数要大.重点计算了膜电阻和互连寿命分布及加速系数.     

多层金属化系统中蓄水池效应对电迁移寿命的影响

在W通孔的多层金属化系统中,金属离子的蓄水池效应对其电迁移寿命的影响很大,文中设计制作了12种不同的蓄水池结构,并进行了电迁移实验.着重考察蓄水池面积、通孔位置、通孔数目对互连线电迁移寿命的影响,得出蓄水池的面积是影响电迁移寿命的主要因素.     

多层金属化系统中蓄水池效应对电迁移寿命的影响

在W通孔的多层金属化系统中,金属离子的蓄水池效应对其电迁移寿命的影响很大,文中设计制作了12种不同的蓄水池结构,并进行了电迁移实验.着重考察蓄水池面积、通孔位置、通孔数目对互连线电迁移寿命的影响,得出蓄水池的面积是影响电迁移寿命的主要因素.     

多层金属化系统中的蓄水池效应

对于W通孔多层金属化系统来说,金属离子蓄水池效应对其电迁移寿命的影响很大.设计了12种不同的蓄水池结构,并进行电迁移实验;考察了蓄水池面积、通孔位置、数目及大小等对互连线的电迁移寿命的影响,得出蓄水池的面积是影响电迁移寿命的主要因素.     

MCM-C中厚膜电阻的寿命分布及退化规律的研究

重点研究了MCM-C基板的可靠性，包括厚膜电阻、基板布线以及互连通孔。试验采取加温度应力与电应力的双应力加速寿命试验。试验中发现，厚膜电阻的退化先于基本布线和互连通孔，故厚膜电阻的退化在MCM-C基板可靠性中起主要的作用；重点讨论了厚膜电阻在热电应力下的失效规律及寿命分布，试验结果表明厚膜电阻的寿命分布服从威布尔分布。     

基于失效机理的半导体器件寿命模型研究

微电子技术的发展使得集成电路的可靠性愈来愈重要,为了在较短的时间内得到产品可靠性数据,使用加速寿命试验是十分有效的方法.而使用加速寿命试验进行可靠性分析,关键是能够得到合适的寿命模型.不同的失效机理对器件寿命的影响是不同的.详细考虑了半导体器件的3个主要失效机理:电迁移、腐蚀和热载流子注入的影响因素,介绍了相应的寿命模型,并且通过具体的数据计算所得到的加速因子,对半导体器件在不同状态下的寿命情况进行了比较.     

VLSI金属互连线1/f γ噪声指数与电迁移失效

对VLSI的金属互连线实施高应力下的加速寿命试验和常规应力下的噪声频谱测量,得到了金属薄膜1/f ^γ噪声的频率指数γ在电迁移演化过程中的变化规律,发现γ指数在寿命试验的某个时间点发生突变,从1.0上升到1.6以上.这种突变可以归因于电迁移诱发空洞形成过程的起点,因而是金属薄膜结构开始发生不可逆结构变化的标志.1/ f ^γ噪声指数因子可望成为金属薄膜电迁移损伤程度或寿命的一个表征参量.     

铝硅铜合金和铝铜合金多层结构的电迁移行为

本文给出了由同一工艺线上加工的铝硅和铝硅铜金属互连线的电迁移加速寿命试验结果，后者寿命比前者要高一个数量级，我们对此作了简要的说明，并介绍了铝铜多层结构互连的的民迁移性能。     

Copper interconnect electromigration behaviors in various structures and lifetime improvement by cap/dielectric interface treatment

Copper interconnect electromigration performance was examined in various structures and three low-k materials (k = 2.65–3.6) using advanced BEOL technology. Strong current dependence effect on electromigration lifetime in three levels via terminated metal lines structure was shown. Moreover, different process approach will lead to different EM behavior and related failure mode. Multi-modality electromigration behavior of Cu dual damascene interconnects were studied. Both Superposition and Weak-Link models were used for statistical determination of lifetimes of each failure models (Statistical method). Results were correlated to the lifetimes of respective failure models physically identified according to resistance time evolution behaviors (Physical method). Good agreement was achieved. Various testing structures are designed to identify the EM failure modes. Extensive failure analysis was carried out to understand the failure phenomena of various test structures. The activation energies of failure modes were calculated. The weak links of interconnect system were also identified. A significant improvement of electromigration (EM) lifetime is achieved by modification of the pre-clean step before cap-layer deposition and by changing Cu cap/dielectric materials. A possible mechanism for EM lifetime enhancement was proposed. Cu-silicide formation before cap-layer deposition and adhesion of Cu/cap interface were found to be critical factors in controlling Cu electromigration reliability. The adhesion of the Cu/cap interface can be directly correlated to electromigration MTF and activation energy. Results of present study suggest that interface of Cu interconnects is the key factor for EM performance for advanced BEOL technology design rules.     

Relationship between texture and electromigration lifetime in sputtered AI-1% Si thin films

The relationship among the grain structure, texture, and electromigration lifetime of four Al-1% silicon metallizations produced under similar sputtering conditions was explored. The grain sizes and distributions were similar and the grain structure was near-bamboo for all metallizations. All metallizations exhibited a near-(111) fiber texture, as determined by the pole figure technique. Differences in electromigration behavior were noted. Three of the metallizations exhibited a bimodal failure distribution while the fourth was monomodal and had the longest electromigration lifetime. The electromigration lifetime was directly related to the strength of the (111) fiber texture in the metallization as anticipated. However, whereas the grain size distribution has an effect on the electromigration lifetime when metallization lines are several grains wide, the electromigration lifetime of these near-bamboo metallizations appeared independent of the grain structure. It was also observed that a number of failures occurred in the 8 μm interconnect supplying the 5 μm wide test lines. This apparently reflects an increased susceptibility of the wider interconnect lines to electromigration damage.     

W-plug via electromigration in CMOS process

We analyze the failure mechanism of W-plug via electromigration made in a 0.5-μm CMOS SPTM process. Failure occurs at the top or bottom of a W-plug via. We design a series of via chains, whose size ranges from 0.35 to 0.55 μm. The structure for the via electromigration test is a long via chain, and the layer in the via is Ti/TiN/W/TiN. Using a self-heated resistor to raise the temperature of the via chain allows the structure to be stressed at lower current densities, which does not cause significant joule heating in the plugs. This reduces the interaction between the plug and the plug contact resistance and the time-to-failure for the via chain. The lifetime of a W-plug via electromigration is on the order of 3 × 107 s, i.e., far below the lifetime of metal electromigration. The study on W-plug via electromigraion in this paper is beneficial for wafer level reliability monitoring of the ultra-deep submicron CMOS multilayer metal interconnect process.     

Electromigration under time-varying current stress

Interconnect failure as a result of electromigration is one of the major IC reliability concerns. The continuing trend of scaling-down feature sizes has exacerbated this problem. Electromigration failure under DC stress has been studied for more than 30 years, and the methodologies for accelerated DC testing and design rules have been well established in the IC industry. However, the electromigration behavior and design rules under time-varying current stress are still unclear. In CMOS circuits, as many interconnects carry pulsed DC (local V_CC and V_SS lines) and bidirectional AC (clock and signal lines), it is essential to assess the reliability of metallization systems under these conditions. The goal of this review is to clarify the failure mechanisms by examining different metallization systems (Al–Si, Al–Cu, Cu, TiN/Al-alloy/TiN, etc.) and different metallization structures (via, plug and interconnect) under pulsed DC and AC stress in a wide frequency range (from millihertz to 500 MHz). Based on these experimental results, a defect relaxation model under pulsed DC stress and a damage healing model under AC stress are developed, and electromigration design rules under these circumstances are proposed. This review shows that in the circuit operating frequency range, the “design rule current” is the time-average current for both pulsed DC and AC cases. The pure AC component of the current only contributes to self-heating, while the average (DC component) current contributes to electromigration. To ensure longer thermal migration lifetime under high frequency AC stress, an additional design rule is proposed to limit the temperature rise due to self-joule heating.     

An evaluation of test methods for the detection and control ofinterconnect reliability

A number of fast, wafer-level test methods exist for interconnect reliability evaluation. The relative abilities of four such methods to detect the quality and reliability of the interconnect over very short test times are evaluated in this work. Four different test structure designs are also evaluated, and the results are compared with package-level median time to failure (MTF) results. The isothermal test method combined with standard wafer-level electromigration accelerated test (SWEAT)-type test structures is shown to be the most suitable combination for defect detection and interconnect reliability control over short test times     

Circuit reliability simulator for interconnect, via, and contactelectromigration

A model for predicting Al interconnect and intermetallic contact/via electromigration time-to-failure under arbitrary current waveform is incorporated in a circuit electromigration reliability simulator. The simulator can (1) generate layout advisory for width and length of each interconnect, and the number of contacts and vias at each node in a circuit, and (2) estimate the overall circuit electromigration failure rate and/or cumulative percent failure as functions of time, temperature, voltage, frequency, and previous stress (e.g., burn-in)     

电迁移引起的倒装芯片互连失效

采用倒装芯片组装菊花链器件研究了高电流密度条件下Al互连的失效问题,分析了不同电迁移条件下,由于金属原子的迁移造成的Al互连微结构的变化。在9.7×105A/cm2电流密度强度条件下,钝化窗口位置的Al原子发生电迁移,在电子风力的作用下,Al原子沿电子流方向扩散进入Al互连层下方的焊料中。同时,随着电流加载时间的延长,化学位梯度和内部应力的作用致使焊料成分向Al互连金属扩散,Al互连金属层形成空洞的同时其成分发生变化。     

Electromigration reliability of tungsten and aluminum vias andimprovements under AC current stress

The reliability with respect to electromigration failure of tungsten and aluminum vias under DC, pulse-DC, and AC stressing has been studied using Kelvin test structures. The results indicate that although W-plug vias can eliminate the step coverage problem, this metallization system is not ideal because the intermetallic contact represents an undesirable flux divergence location for electromigration. Al vias are more reliable than W-plug vias with respect to electromigration failure. The unidirectional 50% duty factor pulse-DC lifetime is found to be twice the DC lifetime in the low-frequency region (<200 Hz) and four times the DC lifetime in the normal frequency region (> 10 kHz). The via lifetimes under bidirectional stressing current are found to be orders of magnitude longer than DC lifetimes under the same stressing current density for both W and Al vias. All the observations are in agreement with a vacancy relaxation model     

Electromigration in Double-Layer Metallization

The electromigration of the top stripe in aluminum double-layer metallization systems was investigated. The current density dependence and the activation energy characterization are important in double-layer metallization. The step-coverage and coating effects of SiN is better than that of Si02. New phenomena associated with electromigration have been observed as follows: 1. The mean lifetime is affected by the material of the dielectric layer. This material effect might be related to the hardness of layer. 2. The mean lifetime due to electromigration depends on the magnitude and polarity of the electric field applied between adjacent stripes. Ordinary stress tests for electromigratfon are done where current is conducted only in the top stripe and not in the bottom stripe. Our results show that this situation is realistic under conditions existing in microelectronic circuits. The proposed method for stress testing should be used to simulate actual condition in microelectronic circuits. We emphasize that the stress test method used to disclose this electric field effect is important for accelerated stress testing, especially for metallization in VLSI circuits and multi-layer systems. The failure mechanism due to the electric field effect can be explained in terms of the applied electric field deflecting current-carrying electrons in the metal stripe, and is independent of leakage current between stripes.