基于IEEE 1500标准的嵌入式存储器测试壳的研究

超大规模集成电路和超深亚微米技术的快速发展,促使了系统芯片(System on Chip,SoC)的产生,同时在SoC中也集成了越来越多的嵌入式存储器,因此嵌入式存储器对SoC芯片的整体性能有非常重要的影响;文章针对SoC中的嵌入式存储器的可测试性设计展开研究;文章基于IEEE 1500标准针对DRAM和SRAM设计了具有兼容性的存储器的测试壳结构,并结合BIST控制器,在Quar-tusⅡ平台上,采用硬件描述语言对测试壳在不同测试指令下的有效性和灵活性进行验证,结果表明文章所设计的测试壳结构达到了预期的要求。     

一种能有效降低Memory BIST功耗的方法

随着系统芯片(SoC)上存储器比重的日趋增加和Memory BIST(memory built-inself-test)的广泛应用,对较低测试功耗的嵌入式Memory BIST的设计要求越来越高,因为测试功耗一般为系统正常工作时的两倍多,而过高的功耗会烧毁电路和降低芯片成品率.通过采用按时钟域划分存储器组和串并结合的方法来降低Memory BIST的测试功耗.实验仿真结果表明,用该方法所得的最大功耗只有传统方法的1/14,可见该方法能有效降低测试时的能量损耗.     

一种嵌入式存储器内建自测试电路设计

随着存储器在芯片中变得越来越重要和半导体工艺到了深亚微米(deep-sub-micron,DSM)时代,对存储器的故障测试变得非常重要,存储器内建自测试(memory built—in self—test,MBIST)是一种有效测试嵌入式存储器的方法;给出了一种基于LFSR的存储器内建自测试电路设计,采用LFSR设计的地址生成器的面积开销相当小,从而大大降低了整个测试电路的硬件开销;16×32b SRAM内建自测试电路设计实验验证了此方法的可行性,与传统的方法相比,它具有面积开销小、工作速度快和故障覆盖率高等优点。     

基于March算法的嵌入式存储器BIST技术

随着嵌入式存储器规模的不断增大,BIST成为一种节省存储器测试时间和测试成本的有效手段.March算法是当前MBIST设计中最适合的算法.简要介绍了存储器故障模型和各种重要的March算法,探讨了MBIST的几种实现方式,从速度、面积、灵活性和IP保护等几方面对它们进行了分析比较,提出了未来MBIST技术的发展趋势.     

面向存储器核的内建自测试

存储器内建自测试是当前针对嵌入式随机存储器测试的一种经济有效的途径。它实质是BIST测试算法在芯片内部的硬件实现,形成“片上BIST测试结构999作为E-RAM核与芯片系统其他逻辑电路的接口,负责控制功能,实现片上E-RAM的自动测试。根据一个实际项目,本文介绍了MBIST的整体设计过程,并针对测试开销等给出了定量和定性的讨论。     

针对嵌入式Cache的内建自测试算法

通过分析嵌入式Cache存储器中使用的双端口字定向静态存储器(SRAM)和内容可寻址存储器(CAM)的功能故障模型,提出了有效地针对嵌入式应用的DS-MarchC E和DC—March CE测试算法,解决了以往算法用于嵌入式系统时故障覆盖率低或测试时间长导致测试效率低的问题．利用March CE算法并结合Cache系统的电路结构特点,设计并实现了一套集中管理的内建自测试测试方案．此方案可以并行测试Cache系统中不同容量、不同端口类型的存储器,并且能够测试地址变换表(TLB)的特殊结构,测试部分面积不到整个Cache系统的2％．     

嵌入式SRAM测试算法及其诊断实现

为有效定位和识别嵌入式静态随机访问存储器(SRAM)中的各种故障,改进SRAM的设计和生产流程,提出一种有效的March19N(N表示存储器的深度)测试算法.把故障注入64×8位的SRAM;再将测试算法的读/写操作转化为控制器的控制状态,并设计带诊断支持功能的内建自测试(BIST)模块;最后用该BIST模块测试注入的故障,并对测试数据进行比较与合成,从而实现故障的测试和定位.通过对仿真实验结果的分析,得出了包括固定型故障、开路故障、跳变故障、跳变耦合故障、幂等耦合故障、状态耦合故障和地址译码故障在内的故障字典表;并由此得出各类故障所具有的不同的故障识别标志,表明文中算法具有较高的故障分辨率.     

深亚微米SoC芯片的可测试性设计

深亚微米工艺使SoC芯片集成越来越复杂的功能,测试开发的难度也不断提高。由各种电路结构以及设计风格组成的异构系统使测试复杂度大大提高,增加了测试时间以及测试成本。描述了一款通讯基带SoC芯片的DFT实现,这款混合信号基带芯片包含模拟和数字子系统,IP核以及片上嵌入式存储器,为了满足测试需求,通过片上测试控制单元,控制SoC各种测试模式,支持传统的扫描测试以及专门针对深亚微米工艺的,操作在不同时钟频率和时钟域的基于扫描的延迟测试模式,可配置的片上存储器的BIST操作以及其它一些特定测试模式。     

用于k测试的BIST测试向量生成器

检测CMOS电路中的开路故障通常需要使用测试向量对。内建自测试(BIST)作为一种有效的测试技术可以大大降低测试开销。本文采用一种具有规则性、模块化和层叠结构的自动控制单元(CA)，来构造产生测试向量对的BIST模块。实验证明，该方法用于瞬态电流测试是有效的。     

用于k测试的BIST测试向量生成器

检测CMOS电路中的开路故障通常需要使用测试向量对。内建自测试(BIST)作为一种有效的测试技术可以大大降低测试开销。本文采用一种具有规则性、模块化和层叠结构的自动控制单元(CA)，来构造产生测试向量对的BIST模块。实验证明，该方法用于瞬态电流测试是有效的。     

A programmable BIST core for embedded DRAM

The programmable BIST design presented here supports various test modes using a simple controller. With the March C algorithm, the BIST circuit's overhead is under 1.3% for a 1-Mbit DRAM and under 0.3% for a 16-Mbit DRAM. The BIST design presented for embedded DRAM supports built-in self-diagnosis by feeding error information to the external tester. Moreover, using a specific test sequence, it can test for critical timing faults, reducing tester time for ac parametric test. The design supports wafer test, pre-burn-in test, burn-in, and final test. It is field-programmable; the user can program test algorithms using predetermined test elements (such as march elements, surround test elements, and refresh modes). The user can optimize the hardware for a specific embedded DRAM with a set of predetermined test elements. Our design is different from the microprogram-controlled BIST described by J. Dreibelbis et al. (1998) which has greater flexibility but higher overhead. Because our design begins at the register-transfer language level, test element insertion (for higher test coverage) and deletion (for lower hardware overhead are relatively easy     

嵌入式只读存储器的内建自测试设计

随着存储器件日益向着高速、高集成方向发展,依靠外部设备对嵌入式存储器的测试变得越来越困难,内建自测试是解决这个问题的有效方法;文中详细分析了存储器的故障表现和诊断算法,给出了嵌入式只读存储器的内建自测试的一种设计实现,同时研究了将边界扫描技术与只读存储器的内建自测试相结合、形成层次化系统芯片SoC的设计策略.     

Built-in Self Testing of Embedded Memories

The authors present a built-in self-test (BIST) method for testing embedded memories. Two algorithms are proposed for self-testing of embedded bedded RAMs, both of which can detect a large variety of stuck-at and non-stuck-at faults. The hardware implementation of the methods requires a hardware test-pattern generator, which produces address, data, and read/write inputs. The output responses of the memory can be compressed by using a parallel input signature analyzer, or they can be compared with expected responses by an output comparator. The layout of memories has been considered in the design of additional BIST circuitry. The authors conclude by evaluating the two schemes on the basis of area overhead, performance degradation, fault coverage, test application time, and testing of self-test circuitry. The BIST overhead is very low and test time is quite short. Six devices, with one of the test schemes, have been manufactured and are in the field.     

基于确定性测试图形的BIST构建方法

为降低内建自测试(Build-in Self Test,BIST)的测试功耗,提出了一种基于确定性测试图形的内建自测试构建方法:首先采用D算法生成测试所需的测试图形,然后使用粒子群算法对其进行优化,使内建自测试的功耗大幅度降低;文中最后以ISCAS'85Benchmark中的部分电路作为实验对象,并给出了测试图形优化前后的功耗数;实验结果证明该方法能够有效降低内建自测试的测试功耗,并且具有方法简单、无需额外硬件开销的特点.     

SoC可测性技术研究

超深亚微米工艺和基于可复用嵌入式IP模块的系统级芯片(SoC)设计方法使测试面临新的挑战,需要研究开发新的测试方法和策略.介绍了可测性设计技术常用的几种方法,从芯核级综述了数字逻辑模块、模拟电路、内存、处理器、第三方IP核等的测试问题,并对SoC可测性设计策略进行了探讨,最后展望了SoC测试未来的发展方向.     

Memory access schedule minimization for embedded systems

The growing gap between microprocessor speed and DRAM speed is a major problem that computer designers are facing. In order to narrow the gap, it is necessary to improve DRAM’s speed and throughput. To achieve this goal, this paper proposes techniques to take advantage of the characteristics of the 3-stage access of contemporary DRAM chips by grouping the accesses of the same row together and interleaving the execution of memory accesses from different banks. A family of Bubble Filling Scheduling (BFS) algorithms are proposed in this paper to minimize memory access schedule length and improve memory access time for embedded systems.When the memory access trace is known in some application-specific embedded systems, this information can be fully utilized to generate efficient memory access schedules. The offline BFS algorithm can generate schedules which are 47.49% shorter than in-order scheduling and 8.51% shorter than existing burst scheduling on average. When memory accesses are received by the single memory controller in real time, the memory accesses have to be scheduled as they come. The online BFS algorithm in this paper serves this purpose and generates schedules which are 58.47% shorter than in-order scheduling and 4.73% shorter than burst scheduling on average. To improve the memory throughput and further reduce the memory access schedule, an architecture with dual memory controllers is proposed. According to the experimental results, the dual controller algorithm can generate schedules which are 62.89% shorter than in-order scheduling, 14.23% shorter than burst scheduling, and 10.07% shorter than single controller BFS algorithms on average.     

用内建自测试(BIST)方法测试IP核

近几年基于预定制模块IP(Intellectua lProperty)核的SoC(片上系统)技术得到快速发展，各种功能的IP核可以集成在一块芯片上．从而使得SoC的测试、IP核的验证以及IP核相关性的测试变得非常困难，传统的测试和验证方法难以胜任。本文通过曼彻斯特编码译码器IP核的设计、测试，介绍了广泛应用于IP核测试的方法一内建自测试fBuilt—In SeIf Test)方法，强调了面向IP测试的IP核设计有关方法。     

Testing mixed-signal cores: a practical oscillation-based test in an analog macrocell

A formal set of design decisions can aid in using oscillation-based test (OBT) for analog subsystems in SoCs. The goal is to offer designers testing options that do not have significant area overhead, performance degradation, or test time. This work shows that OBT is a potential candidate for IP providers to use in combination with functional test techniques. We have shown how to modify the basic concept of OBT to come up with a practical method. Using our approach, designers can use OBT to pave the way for future developments in SoC testing, and it is simple to extend this idea to BIST.     

SoC设计中嵌入存储器对ATPG的影响

在ASIC设计中，越来越多地采用了So（systems-on0a-chip）方法，同时也因为采用各种IP核和嵌入存储器，给芯片的设计和测试带来了复杂性，特别是在ATPG中这些单元对故障覆盖率有较大的影响，现在已经有一些测试嵌入存储器本身的方法，但这些方法一般不考虑嵌入存储器对周围逻辑可测性的影响，在分析了嵌入存储器对ATPG的影响后，提出了消除这些影响的RTL级的DFT方法，这种方法得到了实验的检验。