YON界面钝化层改善HfO2/Ge界面特性的研究

本文采用YON界面钝化层来改善HfO₂栅介质Ge metal-oxide-semiconductor（MOS）器件的界面质量和电特性.比较研究了两种不同的YON制备方法：在Ar+N₂氛围中溅射Y₂O₃靶直接淀积获得以及先在Ar+N₂氛围中溅射Y靶淀积YN再于含氧氛围中退火形成YON.实验结果及XPS的分析表明,后者可以利用YN在退火过程中先于Ge表面吸收从界面扩散的O而氧化,从而阻挡了O扩散到达Ge表面,更有效抑制了界面处Ge氧化物的形成,获得了更优良的界面特性和电特性：较小的CET（1.66 nm）,较大的k值（18.8）,较低的界面态密度（7.79×10¹¹ eV^-1cm^-2）和等效氧化物电荷密度（-4.83×10¹² cm^-2）,低的栅极漏电流（3.40×10^-4 A/cm²@V_g=V_fb+1 V）以及好的高场应力可靠性.     

基于低温氧化的4H-SiC/SiO2界面态钝化方案

阐述4H-SiC晶圆的Si面上通过CVD淀积与低温热氧化生长的双层栅氧化物结构，在高温氮气环境下可降低4H-SiC/SiO₂界面的高密度界面缺陷。采用PECVD淀积一层均匀的SiO₂膜后，通过热氧化工艺在淀积膜与4H-SiC/SiO₂间生长一层很薄的氧化物过渡层。根据不同温区间热氧化温度形成的SiO₂膜晶型不同，改变界面中氮气退火过程中氮元素的引入，从而钝化4H-SiC/SiO₂的界面缺陷。     

偏压应力下SiC/SiO2界面间隙碳缺陷的结构和电学性质演变

SiC栅氧近界面碳缺陷是SiC MOSFET器件在偏压应力下可靠性劣化的主要根源。间隙碳缺陷Si2-C=O(Ci1)和O-C=C-O(Ci2)被认为是构成SiC/SiO₂界面缺陷能级的重要源头之一。基于第一性原理密度泛函理论,研究了不同外部电场对SiC/SiO₂界面处间隙碳缺陷的结构和电学性质的影响。结构键长键角计算结果表明,电场对缺陷Ci1和Ci2的结构影响较小,但施加电场后两种缺陷的形成能均减小,说明偏压应力更有助于这两种缺陷的形成。电荷态密度计算结果表明,不同大小和方向的偏压应力(电场)会改变Ci1和Ci2的缺陷能级位置。上述作用诠释了界面缺陷产生偏压应力不稳定问题的物理机制。     

界面陷阱分布对SiC MOSFET准静态C-V特性的影响

为了分析4H-SiC/SiO₂固定电荷和界面陷阱对MOSFET准静态电容-电压(C-V)特性曲线的影响机制，对不同栅氧氮退火条件下的n沟道4H-SiC双注入MOSFET(DIMOSFET)进行了氧化层中可动离子、界面陷阱分布和准静态C-V特性曲线的测试，并结合仿真探讨了测试频率、固定电荷、4H-SiC/SiO₂界面陷阱分布对准静态C-V特性曲线的影响。实验和仿真结果表明：电子和空穴界面陷阱分别影响准静态C-V曲线的右半部分和左半部分；界面陷阱的E₀、E_s、N₀(E₀为陷阱能级中心与导带底能级或价带顶能级之差，E_s为陷阱能级分布的宽度，N₀为陷阱能级分布的密度峰值)对准静态C-V曲线的影响是综合的；当E₀为0 eV,E_s为0.2 eV,电子和空穴捕获截面均为1×10^-18 cm²,电子和空穴界面陷阱的N₀分...     

He+2+O2电荷交换激光器的理论

本文介绍由He⁺₂与O₂间近共振电荷交换产生的O⁺₂第一负带激光器的动 力学。它可在高压Ηe、O2混合气体(Ηe>>O2)内放电余辉中被激励。针对属于高能质子束产生的放电所提出的增益计算，正推动其用于高压气体激光器。此外，评述了He⁺₂+N₂电荷交换激光器中3914埃激光谱线随Ν2密度的增加而消失。     

聚甲基丙烯酸对STI CMP中SiO2和Si3N4去除速率选择比的影响

在浅沟槽隔离(STI)化学机械抛光(CMP)中,需要保证极低的Si₃N₄去除速率,以及相对较高的SiO₂去除速率,并且要达到SiO₂与Si₃N₄的去除速率选择比大于30的要求。在CeO₂磨料质量分数为0.25%,抛光液pH=4的前提下,研究了聚甲基丙烯酸(PMAA)对SiO₂与Si₃N₄去除速率以及二者去除速率选择比的影响,分析了PMAA在影响SiO₂与Si₃N₄去除速率过程中的作用机理。结果表明,PMAA的加入可以降低SiO₂与Si₃N₄的去除速率,当PMAA的质量分数为120×10^-6时,SiO₂和Si₃N₄的去除速率分别为185.4 nm/min和...     

不同表面活性剂对浅沟槽隔离CMP中SiO2与Si3N4速率选择性的影响

针对浅沟槽隔离(STI)化学机械抛光(CMP)过程中SiO₂与Si₃N₄去除速率选择比难以实现的问题，研究了阳离子表面活性剂十六烷基三甲基溴化铵(CTAB)、阴离子表面活性剂直链烷基苯磺酸(LABSA)以及非离子表面活性剂脂肪醇聚氧乙烯醚(AEO7)对SiO₂与Si₃N₄去除速率以及速率选择比的影响。结果表明，CTAB对于SiO₂去除速率的抑制作用过强，导致速率选择比很低；与CTAB相比，LABSA对SiO₂去除速率的抑制作用减弱，但同时对Si₃N₄去除速率的抑制作用也变小，导致速率选择比无法满足工业生产的30∶1的要求；AEO7对SiO₂去除速率的影响较小，且对Si₃N₄去除速率的抑制作用强于LABSA。当引入质量分数为0.05%的AEO7时，SiO₂的去除速率由318.6 nm/...     

6H-SiC氧化层中Na离子的C-V测试研究

半导体热氧化过程中,不可避免会沾污Na离子,造成MOS电容的C-V曲线平带电压漂移.在1200℃下热氧化,生成SiC/SiO2界面,进而制作MOS电容.采用高电压偏置,在高温度条件下作用于MOS电容;利用Keithley590 C-V分析仪,测量其C-V曲线.计算出氧化层Na离子密度为2.26×1012/cm2,高温负高压偏置不能完全恢复MOS电容的C-V特性,且高压偏置处理后的MOS电容在积累区的电容值减小,与Si材料MOS的情况不同.主要原因是SiC氧化层和界面质量较差,在高温和高压下弱键断裂、固定电荷重新分布.     

Ta2O5高k介电薄膜的制备及其电学性质的研究

用射频磁控溅射法制备了Ta2O5高介电薄膜,并对其进行了退火处理。用C-V,(G/ω)-V和I-V方法研究了Al/Ta2O5/p-Si结构的电学特性,观测到了C-V和(G/ω)-V的频散效应。认为串联电阻、Si/Ta2O5界面的界面态密度、边缘俘获是频散效应的主要原因,提取了界面态密度和边缘俘获电荷的大小。同时也研究了不同的退火温度对这些参数以及漏电流的影响,经600℃退火后,样品的电容最大,俘获电荷密度和漏电流最小,器件的电学性能最佳。     

TCE浓度对热氧化制备6H-SiC MOS特性的影响

研究了新型SiCMOS电容的制备工艺。采用干O2+CHCCl3(TCE)热氧化方法生长6H-SiCMOS氧化层。研究了TCE浓度与SiC/SiO2界面态电荷密度和氧化层电荷密度和应力下平带电压漂移的关系,随着TCE浓度的增加,SiC/SiO2界面态电荷密度和氧化层电荷密度先减小后增大,应力下平带电压漂移减小,得出了最佳TCE:O2浓度比。     

Low temperature identification of interfacial and bulk defects inAl/SiO2/Si capacitor structures by electron beam inducedcurrent

A low temperature electron beam induced current (EBIC) study using Al/SiO₂/Si capacitors as probes of defects affecting the electrical properties of the bulk Si, SiO₂ interface and the SiO₂ layer is presented. The technique's relevance to current research on thin oxides and EBIC image enhancements obtained at reduced temperature are explained. The characteristic EBIC contrast representative of three capacitor bias conditions are reviewed as follows: 1) localized temperature dependent recombination at extended bulk defects for inversion bias, 2) spatial variation of the flat-band voltage due to nonuniform interfacial or oxide charge distributions for weak depletion bias, and 3) electron beam enhancement of SiO₂ leakage currents at defect sites for accumulation bias. Illustrations of these contrast modes are presented for samples containing buried epitaxial misfit dislocations and oxide interface defects     

Suppression of the boron penetration induced dielectric degradationby using a stacked-amorphous-silicon film as the gate structure forpMOSFET

This work proposes a stacked-amorphous-silicon (SAS) film as the gate structure of the p⁺ poly-Si gate pMOSFET to suppress boron penetration into the thin gate oxide. Due to the stacked structure, a large amount of boron and fluorine piled up at the stacked-Si layer boundaries and at the poly-Si/SiO₂ interface during the annealing process, thus the penetration of boron and fluorine into the thin gate oxide is greatly reduced. Although the grain size of the SAS film is smaller than that of the as deposited polysilicon (ADP) film, the boron penetration can be suppressed even when the annealing temperature is higher than 950°C. In addition, the mobile ion contamination can be significantly reduced by using this SAS gate structure. This results in the SAS gate capacitor having a smaller flat-band voltage shift, a less charge trapping and interface state generation rate, and a larger charge-to-breakdown than the ADP gate capacitor. Also the Si/SiO₂ interface of the p⁺ SAS gate capacitor is much smoother than that of the p⁺ SAS gate capacitor     

Metal–Oxide–High-$kappa$ Dielectric–Oxide–Semiconductor (MOHOS) Capacitors and Field-Effect Transistors for Memory Applications

Metal-oxide-high-kappa dielectric-oxide-silicon capacitors and transistors are fabricated using HfO₂ and Dy₂O₃ high-kappa dielectrics as the charge storage layer. The programming speed of Al/SiO₂/Dy₂O₃/ SiO₂/Si transistor is characterized by a DeltaV _th shift of 1.0 V with a programming voltage of 12 V applied for 10 ms. As for retention properties, the Al/SiO₂/Dy₂O₃/ SiO₂/Si transistors can keep a DeltaV _th window of 0.5 V for 2 times10⁸ s. The corresponding numbers for Al/ SiO₂/HfO₂/SiO₂/Si transistors are 100 ms and 2 times10⁴ s, respectively. The better performance of the Al/SiO₂/Dy₂O₃/ SiO₂/Si transistors is attributed to the larger conduction band offset at the Dy₂O₃/SiO₂ interface.     

Low-Frequency Noise Assessment of Silicon Passivated Ge pMOSFETs With TiN/TaN/ HfO2 Gate Stack

The low-frequency noise of pMOSFETs fabricated in epitaxial germanium-on-silicon substrates is studied. The gate stack consists of a TiN/TaN metal gate on top of a 1.3-nm equivalent oxide thickness HfO₂/SiO₂ gate dielectric bilayer. The latter is grown by chemical oxidation of a thin epitaxial silicon film deposited to passivate the germanium surface. It is shown that the spectrum is of the 1/f^gamma type, which obeys number fluctuations for intermediate gate voltage overdrives. A correlation between the low-field mobility and the oxide trap density derived from the 1/f noise magnitude and the interface trap density obtained from charge pumping is reported and explained by considering remote Coulomb scattering     

Spatial Distributions of Trapping Centers in HfO2/SiO2 Gate Stack

An analysis methodology for charge pumping (CP) measurements was developed and applied to extract spatial distributions of traps in SiO ₂/HfO₂ gate stacks. This analysis indicates that the traps accessible by CP measurements in the frequency range down to a few kilohertz are located primarily within the SiO₂ layer and HfO₂/SiO₂ interface region. The trap density in the SiO₂ layer increases closer to the high-kappa dielectric, while the trap spatial profile as a function of the distance from the high-kappa film was found to be dependent on high-kappa film characteristics. These results point to interactions with the high-kappa dielectric as a cause of trap generation in the interfacial SiO₂ layer     

The Effect of Nanoscale Nonuniformity of Oxygen Vacancy on Electrical and Reliability Characteristics of HfO2 MOSFET Devices

To understand the influence of oxygen vacancies in on the electrical and reliability characteristics, we have investigated area-dependent leakage-current characteristics of HfO₂ with large-area device and conducting atomic force microscopy (C-AFM). Unlike with the large-area analysis with typical capacitor and transistor, a clear evidence of oxygen vacancy was observed in nanoscale-area measurement using the C-AFM. Similar observations were made in various postdeposition annealing ambients to investigate the generation and reduction of oxygen vacancy in HfO₂ . With optimized postdeposition annealing for oxygen vacancy, significantly reduced charge trapping was observed in HfO₂ nMOSFET.     

Suppression of the boron penetration induced Si/SiO2interface degradation by using a stacked-amorphous-silicon film as thegate structure for pMOSFET

The authors report that the boron penetration through the thin gate oxide into the Si substrate does not only cause a large threshold voltage shift but also induces a large degradation in the Si/SiO₂ interface. An atomically flat Si/SiO₂ interface can be easily obtained by using a stacked-amorphous-silicon (SAS) film as the gate structure for p⁺ poly-Si gate MOS devices even with the annealing temperature as high as 1000°C     

Transient Charging and Discharging Behaviors of Border Traps in the Dual-Layer HfO2/SiO2 High- κ Gate Stack Observed by Using Low-Frequency Charge Pumping Method

Transient charging and discharging of border traps in the dual-layer HfO₂/SiO₂ high-kappa gate stack have been extensively studied by the low-frequency charge pumping method with various input pulse waveforms. It has been demonstrated that the exchange of charge carriers mainly occurs through the direct tunneling between the Si conduction band states and border traps in the HfO₂ high-kappa dielectric within the transient charging and discharging stages in one pulse cycle. Moreover, the transient charging and discharging behaviors could be observed in the time scale of 10^-8- 10^-4 s and well described by the charge trapping/detrapping model with dispersive capture/emission time constants used in static positive bias stress. Finally, the frequency and voltage dependencies of the border trap area density could also be transformed into the spatial and energetic distribution of border traps as a smoothed 3-D mesh profiling     

Effective Work-Function Modulation by Aluminum-Ion Implantation for Metal-Gate Technology (Poly-Si/TiN/SiO2)

The impact of aluminum (Al) implantation into TiN/SiO₂ on the effective work function (EWF) of poly-Si/ TiN/SiO₂ is investigated. Al implanted at 5 keV with a dose of 5 times 10¹⁵ cm^-2 reduces the flatband voltage (V_FB) and the EWF of poly-Si/TiN/SiO₂ stack by ~150 mV compared with the unimplanted poly-Si/TiN/SiO₂ stack. This reduction of V_FB is found to be dose-dependent, which is correlated to the Al concentration at the TiN-SiO₂ interface as evidenced by secondary-ion-mass-spectrometry profiles. The interface dipole created due to the Al presence at the metal-dielectric interface is believed to contribute to the observed V_FB (or EWF) reduction (or increase). This technique for EWF modulation is promising for further threshold-voltage (V_t) tuning without any process complexities and is quite significant for planar and multiple gate field-effect transistors on fully depleted silicon on insulator.     

In Situ Comparison of Si/High- $kappa$ and $hbox{Si}/ hbox{SiO}_{2}$ Channel Properties in SOI MOSFETs

Detailed measurements of front- and back-channel characteristics in advanced SOI MOSFETs (ultrathin Si film, high-kappa, metal gate, and selective epitaxy of source/drain) are used to reveal and compare the transport properties at the corresponding Si/high- kappa (HfO₂ or HfSiON) and Si/SiO₂ interfaces. Low-temperature operation magnifies the difference between these two interfaces in terms of carrier mobility, threshold voltage, and subthreshold swing. As compared with Si/SiO₂, the low-field mobility is lower at the Si/high-kappa interface and increases less rapidly at low temperature, reflecting additional scattering mechanisms governed by high-kappa and neutral defects.