毫米波三维异质异构集成技术的进展与应用

三维异质异构集成技术是实现电子信息系统向着微型化、高效能、高整合、低功耗及低成本方向发展的最重要方法,也是决定信息化平台中微电子和微纳系统领域未来发展的一项核心高技术。文章详细介绍了毫米波频段三维异质异构集成技术的优势、近年来的发展趋势以及面临的挑战。利用硅基MEMS 光敏复合薄膜多层布线工艺可实现异质芯片的低损耗互连,同时三维集成高性能封装滤波器、高辐射效率封装天线等无源元件,还能很好地处理布线间的电磁兼容和芯片间的屏蔽问题。最后介绍了一款新型毫米波三维异质异构集成雷达及其在远距离生命体征探测方面的应用。     

微流体光纤芯片的研究进展

微流体光纤芯片是一种把光纤植入到芯片中以方便检测的新型生物芯片,它具有体积小、试剂消耗少、处理速度快、灵敏度高、可实现高度集成等优点,成为微全分析系统(μ—TAS)研究的热点．结合目前光纤芯片的发展状况,综述了两种类型光纤芯片的制作方法,介绍了每种芯片的检测原理,结构及其分类,分析了每种芯片优点与不足,并探讨了其发展趋势．     

聚合物二极管结构激光器

本文对最近几年国内外光学微腔结构发光二极管、稀土金属配合物发光二极管及聚全哦二极管结构激光器的研究进展状况做了简要介绍。     

集成微光机械振动传感器芯片制作工艺研究

介绍了一种新型集成微光机械振动传感器的工作原理和芯片制作工艺。以聚甲基丙烯酸甲酯为结构材料，采用旋涂和干法刻蚀技术，实现了光波导集成光路和悬臂梁-质量块微机械结构在硅基底上的集成。详细讨论了高分子聚合物微器件制作工艺中的关键技术、工艺难点以及解决措施。     

IGCT

IGCT集成门极换流晶闸管（Intergrsted Gate Commutated Thyriscors）是一种用于巨型电力电子成套装置中的新型电力半导体器件。IGCT使变流装置在功率、可靠性、开关速度、效率、成本、重量和体积等方面都取得了巨大进展,给电力电子成套装置带来了新的飞跃。IGCT是将GTO芯片与反并联二极管和门极驱动电路集成在一起,再与其门极驱动器在外围以低电感方式连接,结合了晶体管的稳定关断能力和晶闸管低通态损耗的优点,在导通阶段发挥晶闸管的性能,关断阶段呈现晶体管的特性。     

IGCT

IGCT集成门极换流晶闸管（Intergrsted Gate Commutated Thyriscors）是一种用于巨型电力电子成套装置中的新型电力半导体器件。IGCT使变流装置在功率、可靠性、开关速度、效率、成本、重量和体积等方面都取得了巨大进展,给电力电子成套装置带来了新的飞跃。IGCT是将GTO芯片与反并联二极管和门极驱动电路集成在一起,再与其门极驱动器在外围以低电感方式连接,结合了晶体管的稳定关断能力和晶闸管低通态损耗的优点,在导通阶段发挥晶闸管的性能,关断阶段呈现晶体管的特性。     

W波段64通道相控阵微系统设计与实现

相控阵微系统的主要特征是电路与天线的高度融合集成,将三维微纳集成技术和微电子技术紧密地结合在一起,切合相控阵高频化、小型化和低成本的发展需求。本文设计了一款W波段的封装天线相控阵微系统,该相控阵采用硅基三维集成的方式将T/R多功能芯片、天线阵列集成在一个微系统模块中,并详细介绍了基于硅工艺的多功能收发芯片设计和相控阵封装天线设计。给出了相控阵微系统的测试结果。该微系统具有高集成度、高性能、低成本的特点,可以为高速无线通信、高精度探测和成像等应用提供一个较优的技术路径。     

PDMS微流控芯片中的微通道加工技术

传统加工方法制作PDMS微流控芯片中的微通道存在诸多限制,特别是难以实现复杂三维微通道的加工。首先介绍了微通道的传统加工方法,接着简要介绍了不同3D打印技术的基本原理,最后重点阐述了3D打印技术在PDMS微流控芯片微通道加工中的应用。未来,微流控芯片中微通道的加工将会向着高通量、低成本、高精度、三维化、集成化、微型化的方向发展。3D打印、以纳米压印为主要代表的微纳制造技术与传统微通道成型技术的不断融合,为研究人员提供了更多的思路,必将成为微通道加工中的重要技术手段,推动微流控芯片在生物医学、检验检疫、分析化学等领域更广泛的应用。     

蓝光波段顶发射有机发光二极管

针对顶发射有机发光二极管(TEOLEDs)中的微腔效应会增加蓝光波段TEOLEDs的制作难度这一问题,提出利用高透明金属阴极并结合在阴极表面生长增透膜的方法来减小二极管阴极的反光性,从而抑制二极管中的微腔效应(这里主要是指多光束干涉);同时利用宽角干涉对器件结构进行设计来改善二极管的蓝光强度,制备了基于有机蓝光材料4,4'-bis(2,2'-diphenylvinyl)-1,1'-biphenyl的顶发射有机发光二极管;优化了增透膜的厚度,研究了增透膜对于二极管电光性能的影响;得到了性能(亮度、效率、色纯度等)可以与底发射有机发光二极管相比的蓝光波段TEOLEDs.     

一种非对称结构微流体混合器的设计与分析

微流体混合器可以用于不同流体之间的混合与反应,其与化学传感器结合构成的化学分析测试系统,具有灵敏度高、响应时间短和稳定性好的特点。在微电子机械加工技术的基础上,设计了一种新型的、具有非对称分离重组结构的微流体混合器,并应用有限元方法建立了仿真模型,讨论了在不同雷诺数(Re=10~80)下,通道几何结构参数对微混合器内的流体流动特性和混合效率的影响。研究结果表明,微流体在该混合器内形成了扩展涡、分离涡和迪恩(Dean)涡,实现了涡系的叠加和强化,加大了流体间的扰动,增加了流体的接触面积,从而大大增强了混合效率。     

BiCMOS edge detector with correlated-double-sampling readout circuit for pattern recognition neural network

A new image sensor is presented that comprises a chopper-stabilised edge detector and a correlated-double-sampling readout circuit, based on 2 mu m BiCMOS technology for pattern recognition neural network VLSI applications operating at 77 K. With the chopper-stabilised edge detector and the correlated-double-sampling readout technique, the two-dimensional photodiode array, which can be efficiently built with only one readout circuit, provides a bidirectional edge detection capability for high resolution image sensing applications operating at 77 K.<>     

Operating principles and performance of a novel a-Si:H p-i-n-based X-ray detector for medical image applications

This work develops a novel hydrogenated amorphous silicon (a-Si:H) p-i-n photodiode-based X-ray detector aimed at medical image applications. The new detector consists of an a-Si:H p-i-n photodiode and a stacked dielectric layer, deposited on the p-layer (n-i-p-SiN/sub x/) or the n-layer (p-i-n-SiN/sub x/) of the p-i-n photodiode, as the main charge storage element. This detector operates as a capacitor and is connected in parallel to a reverse-biased p-i-n photodiode during the detection cycle to accumulate photon-converted charges. The junction capacitance (C/sub j/) of the p-i-n diode was enhanced by this stacked dielectric layer without reducing the active area of the detector. The design of the charge storage capacity and the photon-charge transfer efficiency can be optimized separately for various applications. Moreover, the linearity, dynamic range of operation, and data retention capacity of the detector were found to be markedly improved by the enlarged capacitance in the detector. The operating principles and performance of this novel device are discussed, and the corresponding control sequence of the switch of the device array is also addressed. The experimental results proved that this novel structure is valid and can be applied to construct effectively a two-dimensional detection array, offering considerable advantages of the novel device in X-ray medical image applications.     

Detection system based on a novel large area hybrid detector

A system level implementation of a large area hybrid detector is presented. The detector used in this system consists of an array of hydrogenated amorphous silicon photodiodes directly connected to a CMOS readout chip, which is vertically integrated over the sensor array using flip-chip bonding. In particular, the proposed solution relies on a stack of interconnection layers, deposited on top of the photodiode array, to route each individual pixel output to a separate pre-amplifier channel. This avoids the need for a geometrical matching between the sensor array and the chip contact pads. As a consequence, conventional non-pixelated readout chip can be used and easy-scalable large area detectors can be produced. The CMOS chip is connected to an electronic board, providing the interfaces needed to read the signals as well as providing voltage references and power to the chip. The signals are collected and pre-processed by an FPGA chip, providing a very compact and flexible setup.     

Antifuse field programmable gate arrays

An antifuse is an electrically programmable two-terminal device with small area and low parasitic resistance and capacitance. Field-programmable gate arrays (FPGAs) using antifuses in a segmented channel routing architecture now offer the digital logic capabilities of an 8000-gate conventional gate array and system speeds of 40-60 MHz. A brief survey of antifuse technologies is provided. the antifuse technology, routing architecture, logic module, design automation, programming, testing and use of ACT antifuse FPGAs are described. Some inherent tradeoffs involving the antifuse characteristics, routing architecture and logic module are illustrated     

Asynchronous 250-Mb/s optical receivers with integrated detector instandard CMOS technology for optocoupler applications

A high-speed ten-channel optical receiver, integrated in a standard 0.6-μm CMOS technology, is presented. Each data channel consists of a spatially modulated light detector (SML-detector) and a low-offset receiver. The SML detector has a much higher intrinsic bandwidth than a conventional photodiode junction implemented in standard CMOS. One channel of the ten is sacrificed and used as a reference to define the threshold level for the other channels. The optical receiver can handle up to 250 Mb/s of noncoded data (including dc) per channel at 20 μW average light input power (λ=860 nm). Power dissipation per channel is only 4 mW. When combined with appropriate light emitters, a compact and low-cost optocoupler can be obtained with improved speed performance compared to existing optocouplers     

A single-chip 9-32 mb/s read/write channel for disk-driveapplications

This paper reports on a single-chip read/write channel for disk drive. The integrated circuit implements a peak detector architecture fully compatible with zoned-bit recording applications. The chip contains all the functions needed to implement a high performance read channel, i.e., pulse detector, programmable active filter, servo demodulator, frequency synthesizer, data separator and RLL(1,7) ENDEC. The design has been done in a way that takes full advantage of the features available in a BiCMOS technology to achieve power saving, high speed and immunity to cross-talk from digital to analog. The IC is fabricated in a 1.2 μ BiCMOS technology and has an active area of approximately 28 mm². While operating from a single 5 V supply the power consumption is only 450 mW at 32 Mb/s     

用于高速量子密码系统的1.25 GHz InGaAs/InP单光子探测器的研制

随着量子密码领域的快速发展,近红外单光子探测器的研究已经成为该领域的研究重点和技术制高点。报道了一种基于正弦门控与滤波技术的InGaAs/InP雪崩光电二极管(APD)高速单光子探测器,门控频率达到1.25GHz。在探测效率为10.3%时,暗计数概率为1.3×10-6/gate,后脉冲概率为5.6×10-5/ns。这种高速单光子探测器将大幅度提升量子密码系统的两个关键指标——密钥率和传输距离,为下一代高速量子密码系统的实用化应用奠定了基础。     

光收发器中光电集成接收芯片的实现

针对应用于850nm光通信中的10/100Mbit/s收发器,提出采用0.5μm标准CMOS工艺对其光接收芯片实现Si基单片集成。整体芯片面积为0.6mm2,共集成了一个双光电二极管的(DPD)光电探测器和一个跨阻前置放大电路,功耗为100mW,并给出了具体的测试性能结果。结果表明,在850nm光照下,光接收芯片带宽达到53MHz,工作速率为72Mbit/s。重点介绍了DPD光电探测器的原理和结构,并给出了相应的制造过程和电路等效模型,对整个光接收芯片进行了多种实用性测试,可以满足系统的性能要求。     

高速双通道光电耦合器OC—5631的研制

本文叙述了一种全密封式高速双通道光电耦合器OC－5631的研制。此种光电耦合器采用高速GaAsPLED为发光部，采用带Si光敏二极管的放大电路为光敏部，采用开集电极肖特基晶体管输出，其数据速率可达5～6Mb/s。本文还就提高光电耦合器性能的一些理论和实践问题进行了探讨。     

单光子探测器研究现状与发展

单光子探测器的研制是量子光学和量子信息领域的一个重要研究课题。单光子探测器突破了传统探测器只针对振幅进行采样的局限,同时对光波或者光子的偏振、波矢、位相等特性进行探测,具有可保持测量信号完整性、理论量子效率高、工作电压低、探测灵敏度高等优点,同时具有室温单光子探测的潜力。为了深入了解单光子探测器的研究现状和发展前景,本文介绍了单光子探测器的工作机理,总结对比了光电倍增管、雪崩光电二极管等传统单光子探测器以及基于新型二维材料的雪崩光电二极管、超导纳米线单光子探测器等新型单光子光电探测器的优势与不足,并对其发展前景进行了展望。此外还介绍了单光子探测器在量子通信、激光测距和成像等领域的应用。