CMOS工艺多功能数字芯片的输出缓冲电路设计

为了提高数字集成电路芯片的驱动能力,采用优化比例因子的等比缓冲器链方法,通过Hspice软件仿真和版图设计测试．提出了一种基于CSMC2P2M0．6μmCMOS工艺的输出缓冲电路设计方案。本文完成了系统的电原理图设计和版图设计,整体电路采用Hspice和CSMC2P2M的0．6μmCMOS工艺的工艺库（06mixddct02v24）仿真,基于CSMC2P2M0．6μmCMOS工艺完成版图设计,并在一款多功能数字芯片上使用,版图面积为1mm×1mm,并参与MPW（多项目晶圆）计划流片。流片测试结果表明,在输出负载很大时,本设计能提供足够的驱动电流,同时延迟时间短、并占用版图面积小。     

0．18μm直接式数字频率合成器全定制版图设计

文章采用0．18μm混合信号1P6M1．8W3．3VCMOS工艺,介绍了一种高速直接式数字频率合成器的全定制版图设计。该芯片为数模混合信号IC,电路内部时钟频率达到1GHz。版图设计过程中采用了集成无源金属-绝缘体-金属（MIM）结构电容及深N阱技术,使用了合适的版图布局和电源、地线、时钟网络拓扑结构,最后还对芯片各模块作了版图优化设计。芯片测试结果表明芯片功能全部实现、性能良好,版图设计较好地实现了电路功能。     

功率集成电路TID加固环栅器件研究现状综述

总结了标准工艺下功率集成电路中总剂量辐射(TID)加固环栅MOS器件与环栅功率器件的研究现状,归纳了不同结构形态的环栅器件的性能优劣,推荐8字形环栅MOS器件、华夫饼功率器件及回字形LDMOS器件结构用于功率集成电路的TID加固设计。同时,阐述了现有环栅MOS器件等效W/L的建模情况,提出保角变换是环栅MOS器件等效W/L精确建模的重要方法,最后还给出了环栅器件建库的基本流程。     

Algorithm for VLSI chip floor plan

An algorithm for a VLSI chip floor plan is presented. It uses initial block placement obtained by the AR (attractive and repulsive force) method, and performs iterative block packing by gradually moving and reshaping blocks with chip boundary shrinking. By the use of several types of experimental data, it is shown that the method is very effective for handling various types of blocks and is well suited to interactive chip layout design.     

一种基于CMOS工艺的电平转换芯片

基于CSMC 2P2M 0.6 μm CMOS工艺设计了一种电平转换芯片.整体电路采用Hspice和CSMC 2P2M的0.6 μm CMOS工艺的工艺库(06mixddct02v24)仿真,基于CSMC 2P2M 0.6 μm CMOS 工艺完成版图设计,并在一款多功能数字芯片上使用,版图面积为1mm×1mm,并参与...     

Self-consistent modeling of heating and MOSFET performance in 3-D integrated circuits

We present a new method for finding the temperature profile of vertically stacked three-dimensional (3-D) digital integrated circuits (ICs). Using our model, we achieve spatial thermal resolution at the desired circuit level, which can be as small as a single MOSFET. To resolve heating of 3-D ICs, we solve nonisothermal device equations self-consistently with lumped heat flow equations for the entire 3-D IC. Our methodology accounts for operational variations due to technology nodes (hardware: device), chip floor plans (hardware: layout), operating speed (hardware: clock frequency), and running applications (software). To model hardware, we first decide on an appropriate device configuration. We then calculate elements of the lumped thermal network using the 3-D IC layout. To include software, chip floor plan, and duty cycle-related performance variations, we employ a statistical Monte Carlo type algorithm. In this paper, we investigate performance of vertically stacked 3-D ICs, with each layer modeled after a Pentium III. Our calculated results show that layers within the stacked 3-D ICs, especially the ones in the middle, may greatly suffer from thermal heating.     

用MSM64164实现的微型测速测温装置

日本OKI公司的MSM64164四位单片微机具有体积小、指令丰富、I／0接口功能强的特点。本文介绍利用这种微处理器芯片组成一种带时钟的数字式测速测温装置；介绍了这种芯片的基本特点和装置的硬件结构，以及RC振荡器式的A／D转换功能的实现和软件设计的基本思想。该装置可以广泛地应用于健身器材和自行车等行业。     

一种新的基于SRAM的快速综合技术

对静态随机存储器(SRAM)全定制设计过程中的版图设计工作量大、重复性强的问题进行了分析,并在此基础上提出了一种新的应用于SRAM设计的快速综合技术。这种技术充分利用SRAM电路重复单元多的特点,在设计过程中尽可能把电路版图的硬件设计转换为使用软件来实现,节省了大量的版图设计和验证的时间,从而提高了工作效率。这种技术在龙芯Ⅱ号CPU的SRAM设计中得到了应用;芯片采用的是中芯国际0.18μm CM O S工艺。流片验证表明,该技术对于大容量的SRAM设计是较为准确而且有效的。     

Area efficient layout design of CMOS circuit for high-density ICs

Efficient layouts have been an active area of research to accommodate the greater number of devices fabricated on a given chip area. In this work a new layout of CMOS circuit is proposed, with an aim to improve its electrical performance and reduce the chip area consumed. The study shows that the design of CMOS circuit and SRAM cells comprising tapered body reduced source fully depleted silicon on insulator (TBRS FD-SOI)-based n- and p-type MOS devices. The proposed TBRS FD-SOI n- and p-MOSFET exhibits lower sub-threshold slope and higher I_on to I_off ratio when compared with FD-SOI MOSFET and FinFET technology. Other parameters like power dissipation, delay time and signal-to-noise margin of CMOS inverter circuits show improvement when compared with available inverter designs. The above device design is used in 6-T SRAM cell so as to see the effect of proposed layout on high density integrated circuits (ICs). The SNM obtained from the proposed SRAM cell is 565 mV which is much better than any other SRAM cell designed at 50 nm gate length MOS device. The Sentaurus TCAD device simulator is used to design the proposed MOS structure.     

基于CMOS多功能数字芯片的ESD保护电路设计

基于CSMC 2P2M 0.6 μm CMOS工艺设计了一种ESD保护电路。整体电路采用Hspice和CSMC 2P2M 的0.6 μm CMOS工艺的工艺库(06mixddct02v24)仿真,基于CSMC 2P2M 0.6 μm CMOS工艺完成版图设计,并在一款多功能数字芯片上使用,版图面积为1 mm×1 mm,参与MPW(多项目晶圆)计划流片,流片测试结果表明,芯片满足设计目标。     

SRAM版图布局方向对产品失效率的影响

静态随机存储器(SRAM)是集成电路中重要的存储结构单元。由于其制备工艺复杂、关键尺寸较小、对设计规则的要求最为严格,因此SRAM的质量是影响芯片良率的关键因素。针对一款微控制单元(MCU)芯片的SRAM失效问题,进行逻辑地址分析确认失效位点,通过离子聚焦束(FIB)切片及扫描电子显微镜(SEM)分析造成失效的异常物理结构,结合平台同类产品的设计布局对比及生产过程中光刻工艺制程的特点,确认失效的具体原因。对可能造成失效的工艺步骤或参数设计实验验证方案,根据验证结果制定相应的改善措施,通过良率测试及SEM照片确认改善结果,优化工艺窗口。当SRAM中多晶硅线布局方向与测试单元中一致时,工艺窗口最大,良率稳定;因此在芯片设计规则中明确SRAM结构布局方向,对于保证产品的良率具有重要意义。     

基于BC7281的功能键盘设计

键盘是最常见的计算机输入设备,广泛应用于微型计算机和各种终端设备上,计算机操作者通过键盘向计算机输入各种指令、数据,指挥计算机的工作。因此键盘设计的好坏,将会直接关系到系统的可靠性与稳定性。本文采用键盘控制芯片BC7281和单片机AT89S52的输入／输出接口设计一个具有功能键的键盘。     

百万门系统级芯片的后端设计

采用0.18μm及以下工艺设计高性能的VLSI芯片面临着诸多挑战,如特征尺寸缩小带来的互联线效应、信号完整性对芯片时序带来的影响、时序收敛因为多个设计变量的相互信赖而变得相当复杂,使百万门级芯片版图设计师需深入物理设计,选用有效EDA工具,结合电路特点开发有针对性的后端设计流程。文章介绍了采用Synopsys公司Astro后端工具对一款百万门级、基于0.18μm工艺SoC芯片后端设计的过程,分为后端设计前的数据准备、布局规划、电源设计、单元放置及优化、时钟树综合、布线等几个阶段进行了重点介绍。同时考虑到深亚微米工艺下的互联线效应,介绍了如何预防串扰问题以及在整个布局布线过程中如何保证芯片的时序能够满足设计要求。     

Design Considerations for Single-Chip Computers of the Future

In the mid 1980's it will be possible to put a million devices (transistors or active MOS gate electrodes) onto a single silicon chip. General trends in the evolution of silicon integrated circuits are reviewed and design constraints for emeging VLSI circuits are analyzed. Desirable architectural features in modem computers are then discussed and consequences for an implementation with large-scale integrated circuits are investigated. The resulting recommended processor design includes features such as an on-chip memory hierarchy, multiple homogeneous caches for enhanced execution parallelism, support for complex data structures and high-level languages, a flexible instruction set, and communication hardware. It is concluded that a viable modular building block for the next generation of computing systems will be a self-contained computer on a single chip. A tentative allocation of the one million transistors to the various functional blocks is given, and the result is a memory intensive design.     

An integrated speech synthesizer

A large scale integrated speech synthesizer is described. It is based on linear predictive coding which is a voice compression technique. The speech synthesizer is suitable for a wide range of applications, particularly in the telecommunications field. The circuit has been designed and fabricated in standard NMOS silicon-gate enhancement-depletion technology. The multidrain MOS (MDMOS) technique used permits a symbolic layout which makes the chip design remarkably simple.     

ASIC物理设计中金属层数对芯片的影响

ASIC芯片物理版图设计的一个重要问题是选用几层金属层。以一款SMIC0.18μmDVBC芯片(BTV2040S03)为例,选用三种不同金属层工艺进行对比。首先设计出三种不同金属层的版图,分析电源电势分布判断其合理性;之后进行布线拥塞率的对比,以分析不同金属层工艺对布线的影响;最后通过最终布线的时序验证和最终流片结果来证实选用金属层设计的可行性。通过上述方法研究集成电路物理设计中,如何选择所使用工艺的金属层数,以达到最大限度节约芯片成本、减小芯片面积和满足布线及时序的目的。     

Chip area estimation method for VLSI chip floor plan

A chip area estimation method is presented, which consists of intrablock area calculation based on empirically obtained block data and interblock channel area calculation. The method is used in a chip floor program for hierarchical standard-cell VLSI layout design. By applying to several practical circuits, it is shown that the estimation error is within ±10%.     

一种中频接收电路的版图设计

利用Cadence版图设计工具采用B300工艺对一种中频接收电路芯片的版图设计实例,阐述了模拟集成电路版图的设计过程,论述了包括单元库建立、布局、布线、设计规则检查（DRC）和版图对照原理图检查（LVS）等在内的设计步骤以及进行每一步骤的具体方法,尤其对布局和布线这样的关键步骤进行了重点讨论。最后给出了完整的芯片版图。     

Computer-aided design of an eight bit binary counter N-MOS chip for large scale integration (LSI)

An integrated eight bit synchronous binary counter along with input/output circuits: gate protection, two phase clock, pad-out has been designed for MOS LSI. The counter has a master-slave flip-flop and a combinational logic to generate the next state, and outgoing carry outputs from this stage. The combination logic has been implemented using pass transistors and thus acts as a steering type logic. This type of logic is very fast, consumes lesser power and needs significantly less area for its implementation.Latest CAD techniques: interactive Graphics system of Applicon AGS/860 LSI Design Station, MOS circuit simulation program MSINC and Design Rule Check (DRC) program have been used for design and chip layout. The entire chip has been laid out in the area of 3 × 3 mm² including test devices and structures for testability analysis. The design is based on LOCOS N-MOS (E-D) technology and 8 micron design rules. The Electromask pattern generation (PG) tape has been prepared from Applicon for making chrome masks.A set of six masks have been used for the fabrication of device and die encapsulated in dual-in line package and tested for its performance. Counter works up to 5 MHz clock frequency as expected from design calculations. From 25 stage ring oscillator frequency measurement the gate delay comes out to be 6 nS.The counter design could easily be substituted as a sub-system/building block or cell in any MOS LSI system design where it makes a part of it.     

Computer-aided design of an n-MOS custom IC-“Subscriber Chip” of the 32-lines microprocessor based PAX (private automatic exchange) system

A 40-pin custom IC-“Subscriber Chip” of the subscriber module of the Intel 8085A microprocessor based PAX system (32P₄-32 lines and four parallel conversations) has been designed using CAD techniques. The chip design is based on the LOCOS n-MOS(E-D) process, 8 micron minimum feature size geometries, λ-based design rules and the cell based design approach.DIF-POL contact for the gate-source interconnection of the depletion load transistors has been made with the buried contacts. System routing has been done on two layers: metal and polysilicon/diffusion. Single metal layer has been used for power and ground routing having interdigitated structure.Chip has also been designed for its testability analysis based on the chip partioning approach. Two phases of the testing have been evolved and the test pattern generation sequences got fully integrated with the chip layout.Latest CAD techniques: Applicon AGS/860 VLSI Interactive Graphics Design System, MOS circuit simulation program MSINC and Design Rule Check program (DRC) have been used for the design and chip layout. The entire chip has been laid-out in the area of 3.35 × 3.35 mm² integrating around 500 components including test devices and structures for the evaluation of devices and process parameters. The Electromask pattern generation (PG) tape has been prepared for making chrome masks.A set of eight masks are to be used in the fabrication of the chip and encapsulated in 40 pin LSI package. The subscriber chip makes the PAX system design simple and reliable.