基于SPARC V8的事务级SoC验证平台设计

针对片上系统SoC架构设计和嵌入式软件开发的需求,采用事务级建模方法使用SystemC完成了基于SPARC V8的事务级SoC验证平台的设计.为降低设计复杂度和提高仿真速度,基于解释-执行技术完成SPARC V8处理器指令精确事务级模型建模,并利用SystemC中的分层通道机制完成AMAB总线、中断控制器、UART、定时器等设备的事务级建模.完成事务级SoC验证平台的构建后,使用测试基准程序组Mibench对该验证平台的功能和仿真速度进行了验证.仿真结果证明了其功能正确,并且仿真速度相对于RTL SoC验证平台有大幅度的提高.     

通信系统中SystemC可重用验证平台的设计

文章以SystemC为验证语言的通信系统的可重用验证平台的设计思路,通过层次化设计,将验证平台划分为4个层次:用户层、配置管理层、总线功能模型层和待测设计层.介绍了各层接口的通信方式,着重介绍了用户层模块、算法模块、端口模块、激励产生模块、总线功能模块以及结果比较模块重用设计方法,依照此方法能快速高效地搭建可重用的验证平台.     

一种基于SystemC的D触发器验证平台研究

当今复杂电子系统更倾向于在更高抽象级进行建模一种基于C/C＋＋的硬件描述语言,SystemC语言变得非常重要,在此介绍了SystemC语言的验证库,以及验证库的顶层设计,接口设计。文章在最后的阶段对D触发器进行了基于SystemC的验证平台搭建,进而展现了SystemC在验证上的优势。     

片上网络的SystemC建模研究

为了实现软硬件协同设计和提高仿真速度的需求,采用SystemC语言的建模方法,通过对片上网络体系结构的研究,提出了一种片上网络的建模方案,并对一个mesh结构完成了SystemC的建模设计。该模型可在系统级和寄存器传输级上使用同一个测试平台,且具有仿真速度快的特点,达到了设计要求。     

片上网络性能及功耗仿真实验研究

片上网络成为解决片上系统互联问题的研究热点。分析了基于SystemC的片上网络软件仿真平台。以NIRGAM模拟器为例,实现了JPEG编码器和XYYX路由算法,并对三种路由算法进行了功耗与时延的对比实验,体现了其方便的扩展能力及性能评估能力。实例表明软件模拟提供了灵活的实验方式,缩短了设计和验证的周期,利于培养创新能力。     

基于SystemC的系统级芯片设计方法研究

在分析当前系统级芯片设计方法的基础上，提出了目前新型系统级IC设计语言SystemC及其平台的设计思想及设计流程，并以具体项目RS编码器来实现和验证。实验结果表明，SystemC是一种很好的软硬件联合设计语言，它不仅可以帮助设计人员完成一个复杂的系统设计，还可以避免传统设计中的各种弊端，并提高设计效率。当然，如何更好地利用SystemC设计也将是EDA领域当前探索的一个重要方向。     

可重构专用处理器周期精确建模

介绍了一种基于SystemC的可重构专用处理器核周期精确建模.该模型采用模块化设计,基于SystemC事务级建模,将运算功能和通信功能分开,模块之间的通信通过函数调用来实现.通过该模型,为可重构专用处理器核提供一种仿真验证平台,与传统RTL验证方法相比,大大提高了可重构专用处理器核的仿真验证效率.     

基于SystemC的片上系统设计

文章提出了基于SystemC的片上系统设计方法.本设计方法引入SystemC,消除了一直存在于系统级设计和硬件设计之间的语言隔阂,基于SystemC进行的系统功能定义能够方便有效地映射为硬件实现部分和软件实现部分,大大地提高了SOC时代集成电路设计效率.     

基于SystemC和Cocentric System Studio设计平台的SoC设计

SystemC是一种基于C 的新型的描述语言.基于SystemC的软硬件协同设计比传统设计方法更加灵活.Cocentric System Studio(CCSS)是Synopsys公司推出的基于SystemC的系统开发和模拟工具.本文讨论了利用CCSS平台和SystemC语言进行设计、仿真和调试的方法.     

基于SystemC的片上网络仿真实验研究

本文分析了基于SystemC的片上网络软件仿真平台。我们以NIRGAM模拟器为例,实现并评估了JPEG编码器和XYYX路由算法,体现了NIRGAM软件模拟器方便的扩展能力及性能评估能力。实例表明,片上网络采用软件模拟提供了更灵活的实验方式,缩短了设计和验证的周期,有利于培养创新能力。     

Platform designer: An approach for modeling multiprocessor platforms based on SystemC

This paper[3.5pc] presents the Platform Designer (PD) framework, a set of SystemC based tools that provide support for modeling, simulation and analysis of multiprocessor SoC platforms (MPSoC), at different abstraction levels. PD provides mechanisms for interconnection specification, process synchronization and communication, thus allowing the modeling of a complete platform, in a unified environment. To do that it uses an extension of the ArchC ADL and acsys, a tool that enables the automatic generation of a SystemC simulator of the platform. The main advantages of this approach are twofold. First, designers have more flexibility since they can integrate and configure different processors to the platform, using a single environment. Second, it enables a faster design space exploration, given that it automatically generates SystemC simulators of whole platforms at distinct abstraction levels. A number of platform variations can be tried out with minor design changes, thus reducing design time. Experimental results show the suitability of the platform simulator for design space exploration. Real applications (with medium complexity) run in the platform in few minutes. Combined with the facility to generate platforms with minor changes, this feature allows an improvement of the design space exploration.     

TAPES—Trace-based architecture performance evaluation with SystemC

The design of today’s System-on-Chip (SoC) architectures faces many challenges in respect to the involved complexity and heterogeneity. An early and systematic exploration of alternatives is mandatory to find a solution that meets all design requirements. Therefore, the experience of system architects has to be supplemented with efficient performance evaluation methods and tools that help in the broad exploration of the solution space. This article describes TAPES (Trace-based Architecture Performance Evaluation with SystemC), an approach that supports system designers in the performance evaluation of SoC architectures. The concept captures the functionality of the architecture in the form of traces for each resource. The trace primitives making up a trace are translated at simulation run-time into transactions and superposed on the system architecture. The method uses SystemC as modeling language, requires low modeling effort and yet provides accurate results within reasonable turnaround times. A concluding application example for the exploration of a network processor architecture demonstrates the effectiveness of the TAPES approach.     

Exploiting UML based validation for compliance checking of TLM 2 based models

SoC system designers commonly employ SystemC based Transaction level modeling (TLM) for its early software development usage and its analysis capabilities. TLM helps in realizing a SoC using virtual prototyping by integration of SoC components at different abstraction levels. The TLM 2 standard introduces interoperability rules for the models that may have been developed independently. However, neither SystemC compiler nor TLM library supports checking of such rules and manually debugging interoperability errors in such models could be a major problem. This provides motivation for developing automatic compliance checking techniques which can detect and report such errors. As the models are refined to incorporate detailed intercommunication protocols among the system components, the need for compliance checking extends to these protocols as well. In this paper, we present an efficient UML based compliance checking technique for TLM 2 models which supports static, dynamic and protocol-specific rule checking.     

Target software generation: an approach for automatic mapping of SystemC specifications onto real-time operating systems

In this paper we present a new approach for automated target code generation for given real-time operating systems out of SystemC to support platform independent software development. Since SystemC becomes the most important language in electronic system level design, the support of a seamless design flow becomes an important task. During the system design process, SystemC is used to develop a “Golden Reference Model” that provides a well-suited platform for specification, simulation, and verification of embedded systems. Based on the “Golden Reference Model,” an important task of the design process is to map applications, that have been described either in C++ or directly in SystemC, to the specific real-time operating system which is running at the target processor. Since a manual mapping approach is time-consuming and error-prone, the mapping process should be performed automatically. This paper presents a new method for automated generation of code for a specified operating system just by using an abstract XML representation of the RTOS API.     

A Semantics-based Translation Method for Automated Verification of SystemC TLM Designs

SystemC has become a de-facto standard language for SoC and ASIP designs. The verification of implementation with SystemC is the key to guarantee the correctness of designs and prevent the errors from propagating to the lower levels. In this project, we attempt translate SystemC programs to formal models and use existing model checkers to implement the verification. The method we proposed is based on a semantic translation method which translates sequential execution statements described as software character to parallel execution ones which are more closely with the implementation of hardware. This kind of conversion is inevitable to verify hardware designs but is overlooked in related works. The main contribution of this work is a translation method which can preserve the semantic consistency while building SMV model for SystemC design. We present the translation rules and implement a prototype tool which supports a subset of SystemC to demonstrate the effectiveness of our method.     

Mining metadata for composability of IPs from SystemC IP library

Exploring the design space when constructing a system is vital to realize a well performing design. Design complexity has made building high-level system models to explore the design space an essential but time-consuming and tedious part of the system design. Reduction in design time and acceleration of design exploration can be provided through reusing IP-cores to construct system models. As a result, it is common to have high-level SoC design flow based on IP libraries promoting reuse. However, the success of these would be dependent on how introspection and reflection capabilities are provided as well as what are the interoperability standard defined. This leads to the important question of what kind of IP metadata must be available to allow CAD tools to effectively manipulate these designs as well as allow for a seamless integration and exchange design information between tools and design flows. In this article, we describe our tools and methodology, which allow introspection of SystemC designs, such that the extracted metadata enables IP composition. We discuss the issues related to extraction of metadata from IPs specified in SystemC and show how our methodology combines C++ and XML parsers and data structures to achieve the above.     

Design and verification of SystemC transaction-level models

Transaction-level modeling allows exploring several SoC design architectures, leading to better performance and easier verification of the final product. In this paper, we present an approach to design and verify SystemC models at the transaction level. We integrate the verification as part of the design flow where we first model both the design and the properties (written in Property Specification language) in Unifed Modeling Language (UML); then, we translate them into an intermediate format modeled with AsmL [language based on Abstract State Machines (ASM)]. The AsmL model is used to generate a finite state machine of the design, including the properties. Checking the correctness of the properties is performed on the fly while generating the state machine. Finally, we translate the verified design to SystemC and map the properties to a set of assertions (as monitors in C#) that can be reused to validate the design at lower levels by simulation. For existing SystemC designs, we propose to translate the code back to AsmL in order to apply the same verification approach. At the SystemC level, we also present a genetic algorithm to enhance the assertions coverage. We will ensure the soundness of our approach by proving the correctness of the SystemC-to-AsmL and AsmL-to-SystemC transformations. We illustrate our approach on two case studies including the PCI bus standard and a master/slave generic architecture from the SystemC library.