针对嵌入式系统的存储器管理单元设计

针对Linux操作系统,实现了面向32位RSIC嵌入式处理器的存储器管理单元。通过在指令快表中增加预比较电路,提高了处理器连续访问同一虚拟页面时的地址转换效率。快表失效时,设计了专门的硬件来实现页表查询及快表填充,处理速度明显优于软件。论文设计的MMU能够很好地和Linux配合,完成地址映射及存储权限管理。     

针对Linux操作系统的MMU设计

本文针对Linux操作系统的内存管理机制设计了一款在TLB不命中时自动查询页表,填充TLB的MMU,并为它设计了一条专门的验证、调试平台.经仿真验证后,本文所设计的MMU能很好的和Linux配合,高效的完成虚拟地址和物理地址的转换.     

重叠地址空间的二次重定向研究

为了提高操作系统内核在地址空间切换时候的效率,利用ARM处理器上的快速上下文切换扩展(fast context switching extension,FCSE),实现任务地址空间的二次重定向.该方法首先将任务地址空间重定向到一个大的单地址空间,内存管理单元再进行从虚拟地址空间到物理地址空间的重定向.单地址空间到物理地址空间的地址转换信息始终保持有效.因而,内存管理单元(memory management unit,MMU)在任务切换的时候不必清空转换查询表(translation look-aside buffer,TLB),可提高处理器在任务切换时候的效率.通过在ARM920RT处理器上的实验发现,按该方法设计实现的内核可以稳定地运行在虚拟机上.     

MIPS内存管理单元的设计与实现

设计MIPS32 4kc处理器内存管理单元(MMU),该模块对处理器地址进行合法性检查,并按照不同的地址空间对虚拟地址进行静态或动态映射。在硬件上采用三级流水线方式实现JTLB,并为处理器指令端口和数据端口设计相应的快表以提高TLB的查询速度。MMU与总线接口模块的时序采用简化的AMBA协议,与处理器进行联合调试并运行Linux操作系统,同时在功能上通过FPGA验证。该模块经过DC综合后,面积约为32K等效逻辑门。     

基于精化的可信执行环境内存隔离机制验证

可信执行环境(trusted execution environment, TEE)基于硬件隔离机制,为安全敏感应用提供隔离的执行环境,保护敏感数据的安全性.内存隔离机制是TEE的关键机制之一,用于对安全内存和非安全内存进行隔离,并对安全内存实施访问控制,如果其安全性不能保证,可能造成存储在安全内存中的敏感数据泄露.为验证TEE内存隔离机制的安全性,针对基于ARM TrustZone技术构建的TEE,提出一种基于精化的可信执行环境内存隔离机制安全性验证方法.建立抽象模型和具体模型,并定义两种模型之间的精化关系,在证明精化关系成立和抽象模型满足信息流安全性的前提下,验证具体模型的信息流安全性.具体模型建模了TEE内存隔离机制的关键硬件和软件,包括TrustZone地址空间控制器、MMU和TrustZone monitor等,在定理证明器Isabelle/HOL中,验证了该模型满足无干扰、无泄露、无影响等信息流安全属性.     

中低端微处理器平台软件仿真MMU的设计与实现

嵌入式软件目前已广泛应用于生活和工业中,由于其硬件开发的局限性,在微控制器(单片机)利用软件的方式来仿真嵌入式硬件平台的物理结构和硬件功能目前在工业和软件开发过程中的应用越来越普遍,以软件方式模拟MMU对内存的操作,实现低端微处理器管理大量内存,来代替高端的ARM内核的微处理器能以比较快的速度进行访问的功能,实现应用上层接口比较方便的系统。本文先重点介绍了ARM系列微处理器中MMU的硬件结构、MMU相关的缓存结构以及MMU的事务处理过程。在此基础上对MMU访问的缓存硬件TLB、Cache、WriteBuffer等结构组成和属性进行描述,并进行软件仿真实现。最后针对s3c2440微处理器与MMU所相关的行为给予软件实现,并进行平台测试。     

MMU协处理器的一种软件模拟模型

根据ARM926EJ-S处理器中MMU协处理器的硬件结构和工作原理,利用CCD建模方法来描述MMU的体系结构,并用FSM建模方法来描述MMU的取指过程和数据读写过程,建立MMU的软件模拟模型。利用建立的模拟模型,给出了模型在实际工程中的应用并进行了测试实验。实验结果表明,建立的MMU模拟模型能够正确模拟MMU的功能,在工程实践中具有较好的应用价值。     

uCLinux与标准Linux在内存管理中的分析与比较

标准Linux系统在内存管理中使用了虚拟内存技术,使得Linux系统的内存管理功能相当强大和安全,而在嵌入式Linux系统中,uCLinux的内存没有相应的MMU处理器,也无法实现虚拟内存管理,针对这种情况,uCLinux采用了针对没有MMU的特殊处理,以实现在嵌入式设备中的需求。     

EEPROM数据指针的断电保护方法

在存储式数据采集系统中,数据指针的断电保护和延长EEPROM的寿命是两个重要的工作.本文采用了校验加冗余的方法对数据指针进行存储,达到了可靠存储的目的.分配了若干个内存块循环存储数据指针,避免了对同一内存块重复擦写的情况,然后使用地址指针记录数据指针的地址.应用证明,该算法满足了工业的需要.     

BASICA调用汇编子程序的简便方法

1.基本思路 1)把汇编子程序安排在内存当前用户空间的低端并驻留。 2)借用为用户保留的中断向量区中的两个存储单元暂存汇编子程序所在代码段的段地址,而这个地址由汇编子程序的引导程序根据操作系统的当前内存分配现行提供。 3)BASIC源程序的一开始从上述内存单元取出段地址,然后用该值重新设置DEFSEG语句,使当前存储段指向汇编子程序所在的代码段。     

CC-NUMA系统中面向页迁移的反向页表技术

页迁移技术是实现CC-NUMA访存局部性优化的一种重要策略,其实现涉及到虚存系统中物理地址到虚拟地址的转换,传统做法需要遍历所有进程的虚拟地址空间,效率低、开销大.针对此问题,介绍了一种在操作系统内核中高效实现物理地址到虚拟地址转换的技术-一反向页表技术,并着重阐述了反向页表在页迁移策略中的应用.     

基于IA64架构的虚拟哈希页表的研究与实现

虚拟哈希页表（VHPT）是高性能微处理器系统实现虚拟地址到物理地址的转换映像，是存储管理的关键技术之一。本文在讨论IA64微处理器地址空间的基础上分析了单地址空间（SAS）和多地址空间（脑）模型的应用需求，研究了长格式、短格式两种页表映射机制，实现了基于这两种格式的64位虚地址空间的哈希地址算法，增强了虚地址转换的
性能。模拟结果表明，该设计与IA64架构兼容。     

A unified framework for designing high performance in-memory and hybrid memory file systems

The emerging non-volatile memory technologies provide a new choice for storing persistent data in memory. Therefore, file system structure needs re-studying and re-designing. Our goal is to design a framework that gives high-performance in-memory file accesses and allows a file whose data can be stored across memory and block device. This paper presents a novel unified framework for in-memory and hybrid memory file systems based on the concept that each file has a contiguous “File Virtual Address Space”. Within this framework, the file access for in-memory data can be efficiently handled by address translation hardware and the virtual address space of file. The file accesses for data in block devices are handled by a dedicated page fault handler for file system. A file system called Hybrid Memory File System (HMFS) is implemented based on this framework. Experimental results show that the throughput of HMFS approaches the memory bus bandwidth in best cases. Compared with in-memory file systems, HMFS reaches 5 times, 2.1 times, and 1.6 times faster than EXT4 on Ramdisk, RAMFS, and PMFS, respectively. Compared with EXT4 on SSD and EXT4 using page cache, HMFS also achieves 100 times and tens of times performance improvement, respectively.     

Forensic Investigation Through Data Remnants on Hadoop Big Data Storage System

Forensic examiners are in an uninterrupted battle with criminals in the use of Big Data technology. The underlying storage system is the main scene to trace the criminal activities. Big Data Storage System is identified as an emerging challenge to digital forensics. Thus, it requires the development of a sound methodology to investigate Big Data Storage System. Since the use of Hadoop as Big Data Storage System continues to grow rapidly, investigation process model for forensic analysis on Hadoop Storage and attached client devices is compulsory. Moreover, forensic analysis on Hadoop Big Data Storage System may take additional time without knowing where the data remnants can reside. In this paper, a new forensic investigation process model for Hadoop Big Data Storage System is proposed and discovered data remnants are presented. By conducting forensic research on Hadoop Big Data Storage System, the resulting data remnants assist the forensics examiners and practitioners for generating the evidences.     

Suggest a format for intelligence control and structure of holographic data storage system

Data storage related with writing and retrieving requires high storage capacity, fast transfer rate and less access time. Today any data storage system cannot satisfy all of these conditions, however holographic data storage system (HDSS) can perform faster data transfer rate because it is a page oriented memory system using volume hologram in writing and retrieving data. System can be constructed without mechanically actuating part therefore fast data transfer rate and high storage capacity about 1Tb/cm3 can be realized. In this research, to reduce errors of binary data stored in HDSS, a new method for bit error reduction is suggested. Firstly, find fuzzy rule using test bed system for Element of Holographic Digital Data System and make fuzzy rule table using subtractive clustering algorithm and genetic algorithm and Reduce prior error element and recording digital data. Secondly, Reduce prior error element and recording digital data using the particle filter method. Finally, Recording ratio and reconstruction ratio show good performance and we suggest intelligence control method and filter method. Our format table include intelligence control algorithm and filter method.     

一种TLB结构优化方法

针对国产处理器地址代换旁路缓冲(TLB)性能不足的问题,通过对现有的虚实地址代换流程进行分析,提出设置独立第三级页表基址虚实映射缓存,对数据TLB结构进行优化的方法,减少低级页表虚实映射关系对高级页表虚实映射关系的挤占淘汰。SPEC CPU2000测试结果表明,近一半的课题能减少60％以上数据TLB的DM次数,少数课题甚至能减少90％以上,有效减少数据TLB缺失率。     

嵌入式WinCE平台下的频谱数据传输控制

针对频谱仪中频谱数据的有序传输控制问题,设计并实现了一种基于ARM＋FPGA的运行于WinCE环境下的频谱数据实时采集系统。设计中主要完成了ARM＋WinCE通过虚拟地址映射机制与外设缓存FIFO进行数据通信;同时,运行在WinCE系统环境下的人机监控软件,采取了合理高效的算法,实时有序地采集FIFO中缓存的大量频谱数...     

Compressed page walk cache

GPUs are widely used in modern high-performance computing systems. To reduce the burden of GPU programmers, operating system and GPU hardware provide great supports for shared virtual memory, which enables GPU and CPU to share the same virtual address space. Unfortunately, the current SIMT execution model of GPU brings great challenges for the virtual-physical address translation on the GPU side, mainly due to the huge number of virtual addresses which are generated simultaneously and the bad locality of these virtual addresses. Thus, the excessive TLB accesses increase the miss ratio of TLB. As an attractive solution, Page Walk Cache (PWC) has received wide attention for its capability of reducing the memory accesses caused by TLB misses. However, the current PWC mechanism suffers from heavy redundancies, which significantly limits its efficiency. In this paper, we first investigate the facts leading to this issue by evaluating the performance of PWC with typical GPU benchmarks. We find that the repeated L4 and L3 indices of virtual addresses increase the redundancies in PWC, and the low locality of L2 indices causes the low hit ratio in PWC. Based on these observations, we propose a new PWC structure, namely Compressed Page Walk Cache (CPWC), to resolve the redundancy burden in current PWC. Our CPWC can be organized in either direct-mapped mode or set-associated mode. Experimental results show that CPWC increases by 3 times over TPC in the number of page table entries, increases by 38.3% over PWC in L2 index hit ratio and reduces by 26.9% in the memory accesses of page tables. The average memory accesses caused by each TLB miss is reduced to 1.13. Overall, the average IPC can improve by 25.3%.     

一个基于IA-64体系的内存管理大页面的实现模型

本文提出了一种基于IA-64体系结构的内存页面大页面化的模型，可执行文件ELF的Data Segment使用大页面。由于转换解析缓冲区（TLB）能映射更大的虚拟内存范围，从而可减小未命中率，因此可以提高使用大页面的高性能计算（HPC）应用程序或使用大量虚拟内存的任何内存访问密集型应用程序系统性能。     

基于虚拟机技术的进程分析方法

针对现有进程分析方法存在的缺陷,提出了一种在Windows平台虚拟环境下分析进程的方法。该方法首先在宿主机下分析虚拟机的内存,捕捉当前线程,并通过内核数据结构得到当前线程所在进程, 然后通过页目录表物理地址计算进程页面,对内存进行清零来结束进程。实例分析表明本方法在保护宿主机安全的同时,能快速监测到程序,并且可以有效地结束进程。