一种电路板网络化诊断测试的可测性设计方法

提出并实现了一种电路板网络化诊断测试的可测性设计方法.按照此方法设计的电路板,除了能够实现上电自检,还可以借助无线或有线网络由异地PC(个人电脑)机等远地终端来启动电路板测试、控制测试过程、查看测试流程、获得测试结果以及更新/升级测试程序,对电路板进行全面的诊断测试.为电路板的高质量测试提供了一条实用、有效的技术途径.     

程控交换机交换网络电路板的测试与故障诊断

本文从PS-NA程控交换网络测试台的工程实际出发,提出了一套对交换网络存储电路板的诊断测试方法。它将时分交换网络中的信号部分和控制部分各电路板共同模型化为若干个功能模块,分别讨论了它们的故障模型和测试方法。本算法充分利用了系统的可测性资源,测试复杂性较低,执行时间短。     

一种基于网络编码的NC-BT文件共享系统设计与实现

为了克服目前流行BitTorrent系统工作中存在的文件分块调度算法复杂、文件下载稳定性等问题,提出在BitTorrent系统中采用网络编码技术解决这些问题的思路,设计并实现了基于网络编码的NC-BT系统.在实际网络环境中对该系统进行测试和分析,实验结果证明使用网络编码技术方案能够有效解决现有BitTorrent中存在的问题,从而增强系统的鲁棒性,降低系统调度算法复杂性等优点.     

通信设备可测试性设计技术分析

随着通信技术的高速发展、芯片集成度的不断提高以及电路板复杂性的不断增加,传统的测试模型和测试方法已经不能满足当前的测试要求,测试费用急剧增加。通信设备可测性设计对于提高通信设备的测试水平、缩短故障检测和隔离时间,进而降低生产测试成本及生命周期费用具有重要的意义。本文综述了通信设备可测性技术的基本原理和设计思路,并对其关键技术进行了具体分析。     

应用边界扫描技术提高电路板可测试性的两种优化问题

边界扫描测试技术很好地解决了VLSI电路诊断、测试的困难问题，得到了广泛的应用。作者在查阅大量文献资料的基础上．总结出了边界扫描技术在提高电路板可测试性上的两种优化问题：即设计过程中设计复杂性和测试性改善的优化，以及在测试生成算法中紧凑性与完备性优化的问题，论文详细分析了这两种问题，分析比较了相关的优化算法，并对这两种优化问题未来的发展方向进行了预测。     

谈谈电路板的可测性设计

在当今的电子产品生产企业中,为了使电路板质量得到有效监控,都采用了电路板在线测试的方法,但希望被测试的电路板是否能够进行在线测试呢?这就需要进行电路板的可测性设计。     

基于FPGA的PCB测试机测试算法及其实现

印刷电路板(简称PCB)测试机的测试算法是PCB测试机的核心,它直接决定测试机的测试功能和测试速度.在现场可编程门阵列(Field programmable gate array,FPGA)上实现此算法,不仅简化了电路板设计,而且提高了系统的测试速度及系统的可重构性.论文研究了PCB测试中的主要测试算法(导通测试和绝缘测试)的FPGA实现,给出了测试算法的状态图,以及应用Altera公司的EDA设计的仿真图.实验结果表明此方法是一种可行和有效的方法.     

集成电路可测性设计中网表的解析与实现

本文介绍了集成电路可测性设计项目中针对Cadence网表文件进行解析,提取待测元件之间管脚连线的方法和过程。首先分析网表文件结构,接着详细说明如何过滤网表文件中的无用信息,析取出与待测元件相关的网络节点定义,最后再从析取出的网络节点定义中提取待测元件的引脚连线信息并按照指定的文件格式输出。     

微电子学、集成电路

TN4 2005020497 运动视觉处理5 OC可测性设计与实现/张弘,杨莉,李玉山(西安电 子科技大学)11电子测量与仪器学报一2 004,18(2)一20一24 在设计运动视觉处理5 OC时,文中采用了基于IP的结构,虽然有设计 方法先进、可复用等优点,但也使得SOC复杂性增加,也加大了系统芯 片内部的数据通路完整性、IP和处理器等的测试难度.文中采用了基于 IEEE P1500的测试框架结构以及BIST方法对此SOC以及其中的 IP进行可测性设计的方法,有效地改善了整个SOC测试性能提高了 5 OC的可靠性.仿真试验的结果说明了其测试的有效性.图4参6(刚) 动态范围(S…     

一种基于总线复用的SoC功能测试结构设计

由于SoC结构的复杂性,必须考虑采用多种可测性设计策略.从功能测试的角度出发,提出了一种基于复用片内系统总线的可测性设计策略,使得片内的各块电路都可被并行测试.阐述了其硬件实现及应用测试函数编写功能测试矢量的具体流程.该结构硬件开销小,测试控制过程简单,可减小测试矢量规模,已应用到一种基于X8051核的智能测控SoC,该SoC采用0.35μm工艺进行了实现,面积为4.1 mm×4.1 mm,测试电路的面积仅占总面积的2%.     

基于人工免疫的PCB电路信息融合故障诊断

印制电路板(PCB)非介入式故障诊断方法,因获取信息有限,存在故障覆盖率低、定位不准等问题。多源信息融合能综合各类信息以提高电路诊断效果。文章提出采用人工免疫网络(AIS)作为信息融合技术的融合算法,实现PCB电路非介入式故障诊断。该方法以电路支路电流信息和节点电压信息为信息源,运用人工免疫系统实现基于特征层信息融合的印制电路板非介入式故障诊断。某实装电流转电压电路故障诊断仿真实验表明:基于多源信息融合的非介入式故障诊断可提高电路故障的覆盖率和定位的准确性。     

基于 DFT 的 MIMO 雷达发射方向图设计

针对多输入多输出(MIMO)雷达的发射方向图设计问题,为了在保证方向图匹配性能以及空域弱互相关性的前提下,有效降低计算复杂度,提出一种基于离散傅里叶变换(DFT)的方向图设计算法。该算法先依据方向图的匹配性能及空域互相关性构建代价函数,再利用DFT 构造发射信号协方差矩阵,从而避免了采用传统凸优化方法引入的极高复杂度。理论分析表明,该算法设计的信号协方差矩阵能够满足方向图设计模型中的基本约束条件,同时使得代价函数最小,具备一定的合理性。仿真及性能分析结果表明,该算法计算复杂度低,且设计出的方向图匹配性能良好、空域互相关性小。     

Efficient VLSI architectures for fast computation of the discreteFourier transform and its inverse

In this paper, we propose two new VLSI architectures for computing the N-point discrete Fourier transform (DFT) and its inverse (IDFT) based on a radix-2 fast algorithm, where N is a power of two. The first part of this work presents a linear systolic array that requires log₂ N complex multipliers and is able to provide a throughput of one transform sample per clock cycle. Compared with other related systolic designs based on direct computation or a radix-2 fast algorithm, the proposed one has the same throughput performance but involves less hardware complexity. This design is suitable for high-speed real-time applications, but it would not be easily realized in a single chip when N gets large. To balance the chip area and the processing speed, we further present a new reduced-complexity design for the DFT/IDFT computation. The alternative design is a memory-based architecture that consists of one complex multiplier, two complex adders, and some special memory units. The new design has the capability of computing one transform sample every log₂ N+1 clock cycles on average. In comparison with the first design, the second design reaches a lower throughput with less hardware complexity. As N=512, the chip area required for the memory-based design is about 5742×5222 μm², and the corresponding throughput can attain a rate as high as 4M transform samples per second under 0.6 μm CMOS technology. Such area-time performance makes this design very competitive for use in long-length DFT applications, such as asymmetric digital subscriber lines (ADSL) and orthogonal frequency-division multiplexing (OFDM) systems     

Low-Cost Fast VLSI Algorithm for Discrete Fourier Transform

A primeN-length discrete Fourier transform (DFT) can be reformulated into a (N-1)-length complex cyclic convolution and then implemented by systolic array or distributed arithmetic. In this paper, a recently proposed hardware efficient fast cyclic convolution algorithm is combined with the symmetry properties of DFT to get a new hardware efficient fast algorithm for small-length DFT, and then WFTA is used to control the increase of the hardware cost when the transform length Nis large. Compared with previously proposed low-cost DFT and FFT algorithms with computation complexity of O(logN), the new algorithm can save 30% to 50% multipliers on average and improve the average processing speed by a factor of 2, when DFT length Nvaries from 20 to 2040. Compared with previous prime-length DFT design, the proposed design can save large amount of hardware cost with the same processing speed when the transform length is long. Furthermore, the proposed design has much more choices for different applicable DFT transform lengths and the processing speed can be flexible and balanced with the hardware cost     

Design of M‐Channel IIR Uniform DFT Filter Banks Using Recursive Digital Filters

In this paper, we propose a method for designing a class of M‐channel, causal, stable, perfect reconstruction, infinite impulse response (IIR), and parallel uniform discrete Fourier transform (DFT) filter banks. It is based on a previously proposed structure by Martinez et al. [1] for IIR digital filter design for sampling rate reduction. The proposed filter bank has a modular structure and is therefore very well suited for VLSI implementation. Moreover, the current structure is more efficient in terms of computational complexity than the most general IIR DFT filter bank, and this results in a reduced computational complexity by more than 50% in both the critically sampled and oversampled cases. In the polyphase oversampled DFT filter bank case, we get flexible stop‐band attenuation, which is also taken care of in the proposed algorithm.     

A novel VLSI design of radix-4 DFT in current mode

Discrete-time Fourier transform (DFT) is viewed as an important tool in discrete time signal processing. Applications in wireless communication such as OFDM uses DFT/IDFT in its receiver and transmitter. For small battery powered wireless devices, discrete time analogue DFT can be very useful as a low-energy front-end. The quest for a reduction in the effect due to the mismatch of transistors lead to higher radix structure. It becomes very challenging for the designer to build an analogue circuit for implementation of DFT with radix sizes 4, 8, and so on. This is mainly because of hand calculation of circuit-level equations from butterfly algorithm becomes a long process. Thus, a design methodology becomes a necessary option in this regard. Here an algorithm is proposed for the generation of circuit-level equations leading to signal routing table for the circuit of basic radix-4 FFT. Following that algorithm, a current mode all analogue circuit with cascode current mirror is proposed. Simulations are carried out in SPICE using BSIM4 65 nm CMOS process. A mismatch noise model is also made to show the reduction in error with higher radix structure. The non-ideal effects due to mismatch in V_th are analysed through Monte-Carlo simulation.     

Nested planar array: configuration design,optimal array and DOA estimation

Nested array enables to enhance localisation resolution and achieve under-determined direction of arrival (DOA) estimation. In this paper, we improve the traditional nested planar array to achieve more degrees of freedom (DOFs) and better angle estimation performance. The closed-form expressions for sensor positions of the improved array are given and the optimal array configuration for largest available DOFs is derived. Meanwhile, a computationally efficient DOA estimation algorithm is proposed. Specifically, we utilise two dimensional Discrete Fourier Transform (2D DFT) method to obtain the coarse DOA estimates; Subsequently, we achieve the fine DOA estimates by 2D spatial smoothing multiple signals classification (SS-MUSIC) algorithm. The proposed algorithm enjoys the same estimation accuracy as SS-MUSIC algorithm but with lower complexity because the coarse DOA estimates enable to shrink the range of spectral search. In addition, estimation of the number of signals is not required by 2D DFT method. Extensive simulation results testify the effectiveness of the proposed algorithm.     

无线局域网通信芯片可测性设计及实现

可测性设计已应用在大规模集成电路设计中。本文介绍了可测性设计原理和实现技术。同时介绍了一款无线局域网(WLAN)芯片,根据该芯片的结构特点,介绍了本款芯片应用的可测性技术以及实现过程,对使用的EDA工具及设计方法进行了深入描述。最后对可测性设计实现的效果进行了说明,并给出部分测试结果。     

一种基于DFT的低复杂度虚子载波OFDM信道估计算法

该文针对采用虚子载波的OFDM通信系统,提出了一种基于DFT的低复杂度信道估计算法,并与最小二乘(Least Square,LS)估计算法和线性最小均方误差(Linear Minimum Mean Square Error,LMMSE)算法进行了详细的性能和复杂度比较。所提DFT算法较好地降低了高斯白噪声的影响,相对于LS算法获得了较大的性能增益。该算法在复杂度与性能之间取得了较好的折衷,具有很好的实用价值。