Statistical analysis of subthreshold leakage current for VLSI circuits

We develop a method to estimate the variation of leakage current due to both intra-die and inter-die gate length process variability. We derive an analytical expression to estimate the probability density function (PDF) of the leakage current for stacked devices found in CMOS gates. These distributions of individual gate leakage currents are then combined to obtain the mean and variance of the leakage current for an entire circuit. We also present an approach to account for both the inter- and intra-die gate length variations to ensure that the circuit leakage PDF correctly models both types of variation. The proposed methods were implemented and tested on a number of benchmark circuits. Comparison to Monte Carlo simulation validates the accuracy of the proposed method and demonstrates the efficiency of the proposed analysis method. Comparison with traditional deterministic leakage current analysis demonstrates the need for statistical methods for leakage current analysis.     

CMOS logic gate performance variability related to transistor network arrangements

The rapid scaling of CMOS technology has resulted in drastic variations of process parameters. Since different transistor arrangements present different electrical characteristics, this work analyzes the impact of process variability in performance of logic gates, according to their topology and the relative position of the switching device in the network. Results have been obtained through Monte-Carlo simulations and design guidelines for parametric yield improvement have been derived.     

Differential current switch logic: a low power DCVS logic family

Differential current switch logic (DCSL), a new logic family for implementing clocked CMOS circuits, has been developed. DCSL is in principle a clocked differential cascode voltage switch logic circuit (DCVS). The circuit topology outlines a generic method for reducing internal node swings in clocked DCVS logic circuits. In comparison to other forms of clocked DCVS, DCSL achieves better performance both in terms of power and speed by restricting internal voltage swings in the NMOS tree. DCSL circuits are capable of implementing high complexity high fan-in gates without compromising gate delay. Automatic lock-out of inputs on completion of evaluation is a novel feature of the circuit. Three forms of DCSL circuits have been developed with varying benefits in speed and power. SPICE simulations of circuits designed using the 1.2 μm MOSIS SCMOS process indicate a factor of two improvement in speed and power over comparable DCVS gates for moderate tree heights     

A new approach to power estimation and reduction in CMOS digital circuits

Modelling and optimization of dynamic capacitive power consumption in digital static CMOS circuits, taking into consideration a reason of a gate switching—gate control mode, is discussed in the present paper. The term ‘gate control mode’ means that a number and type of signals applied to input terminals of the gate have an influence on total amount of energy dissipated during a single switching cycle. Moreover, changes of input signals, which keep the gate output in a steady state, can also cause power consumption. Based on this observation, complex reasons of power losses have been considered. In consequence, the authors propose a new model of dynamic power consumption in static CMOS gates. Appropriate parameters’ calculation method for the new model was developed. The gate power model has been extended to logic networks, and consequently a new measure of the circuit activity was proposed. Switching activity, which is commonly used as a traditional measure, characterizes only the number of signal changes at the circuit node, and it is not sufficient for the proposed model. As the power consumption parameters of CMOS are dependent on their control mode, the authors used probability of the node control mode as a new measure of the circuit activity. Based on the proposed model, a procedure of combinational circuit optimization for power dissipation reduction has been developed. The procedure can be included in a design flow, after technology mapping. Results of the power estimation received for some benchmark circuits are much closer to SPICE simulations than values obtained for other methods. So the model proposed in this study improves the estimation accuracy. Additionally, we can save several percent of the consumed energy.     

三种低压高速低耗BiCMOS三态逻辑门

采用0.35μm B iCM O S工艺技术,设计了三种高性能的B iCM O S三态逻辑门电路,并提出了改进三态门电路结构和优化器件参数的方法和措施。仿真和实验结果表明,所优化设计的B iCM O S三态门的电源电压均小于3.3 V,工作速度比常用的CM O S三态门快约5倍,功耗在60 MH z下仅高出约2.2~3.7 mW,而延迟-功耗积却比该常用的CM O S三态门平均降低了38.1%,因此它们特别适用于低压、高速、低功耗的数字系统。     

A comprehensive delay macro modeling for submicrometer CMOS logics

The increasing need for high-performance, cost-effective, application-specific integrated circuits, associated to the reduction of design cycle time, compels designers to manage and optimize the circuit speed performance at each step of the design flow. Circuits are usually designed at gate level; the gate selection or sizing and their placement are driven by estimated delay, hence the need for accurate estimations at the logical level. In the submicrometer range, the gap between gate-level logical estimations and transistor-level electrical simulations dramatically increases. We propose here a comprehensive analytical modeling of the speed performance of CMOS gates with an accuracy comparable to electrical simulators. A design-oriented expression of delay is first developed for CMOS inverters, considering input slope, input-to-output capacitance coupling, and short-circuit current effects. The extension to more complex gates is proposed using a serial array reduction technique taking account of the gate input dependency and the input-slope-induced nonlinearity. Validations are obtained over a large range of design, load, and input slope conditions by comparison with SPICE simulations (level 6 with 0.65-μm foundry specified card model) used as a reference     

Subthreshold Performance of Dual-Material Gate CMOS Devices and Circuits for Ultralow Power Analog/Mixed-Signal Applications

Analog circuits based on the subthreshold operation of CMOS devices are very attractive for ultralow power, high gain, and moderate frequency applications. In this paper, the analog performance of 100 nm dual-material gate (DMG) CMOS devices in the subthreshold regime of operation is reported for the first time. The analog performance parameters, namely drain-current (I_d), transconductance (g_m), transconductance generation factor (g_m/I_d), early voltage (V_A), output resistance (R_o) and intrinsic gain for the DMG n-MOS devices, and and for the DMG p-MOS devices are systematically investigated with the help of extensive device simulations. The effects of different capacitances on the unity-gain frequency are also studied. The DMG CMOS devices are found to have significantly better performance as compared to their single-material gate (SMG) counterpart. More than 70% improvement in the voltage gain is observed for the CMOS amplifiers when dual-material gates, instead of single-material gates, are used in both the n- and p-channel devices.     

A bootstrapped bipolar CMOS (B2CMOS) Gate forlow-voltage applications

This paper reports on a BiCMOS logic gate which combines bootstrapping and transient saturation techniques to achieve full swing operation down to 1.1 V supply voltage. The proposed B²CMOS uses a conventional (noncomplementary) BiCMOS process. HSPICE simulations have been used to compare the B²CMOS to CMOS, BiNMOS, and BS-BiCMOS for sub-0.5 μm BiCiMOS technologies. Simulation results have shown that the B²CMOS gate outperforms CMOS, BiNMOS, and BS-BiCMOS gates at 3 V and below. The crossover capacitance/fanout of the B²CMOS gate is 100 fF (i.e., fanout of 4) at 1.5 V. The delay-to-load sensitivity of the B²CMOS is 220 ps/pF (8 ps/fanout) which is one order of magnitude smaller than that of CMOS at 1.5 V     

Sub-1/4-μm dual-gate CMOS technology using in-situ dopedpolysilicon for nMOS and pMOS gates

A new dual poly-Si gate CMOS fabrication process is proposed. The incorporated technology features a boron-penetration-resistant MBN gate structure for pMOSFET's, and a dual poly-Si gate CMOS process involving separate depositions of in-situ doped n⁺ and p⁺ poly-Si for the nMOS and pMOS gates, 0.2-μm CMOS devices with 3.5-nm gate oxide have been successfully fabricated. The advantages of the new process are demonstrated on these test devices. A CMOS 1/16 dynamic frequency divider fabricated by the new process functions properly up to 5.78 GHz at a 2-V supply voltage     

电路抗老化设计中基于门优先的关键门定位方法

随着CMOS工艺尺寸不断缩小,尤其在65 nm及以下的CMOS工艺中,负偏置温度不稳定性(NBTI)已经成为影响CMOS器件可靠性的关键因素。提出了一种基于门优先的关键门定位方法,它基于NBTI的静态时序分析框架,以电路中老化严重的路径集合内的逻辑门为优先,同时考虑了门与路径间的相关性,以共同定位关键门。在45 nm CMOS工艺下对ISCAS基准电路进行实验,结果表明:与同类方法比较,在相同实验环境的条件下,该方法不仅定位关键门的数量更少,而且对关键路径的时延改善率更高,有效地减少了设计开销。     

A flexible gate array architecture for high-speed and high-densityapplications

A scaleable gate array has been designed in half-micron CMOS for a wide range of high-speed and high-density applications. Transistor size and position within the basecell provide an efficient implementation of flip-flops, combinational gates, and memory. Design benchmarks have demonstrated 2700 gates/mm² routed density in a 0.5 μm TLM CMOS gate array. Compared to previous 5 V 0.7 μm gate arrays, the new basecell provides improvements of 2.5x in density and 30% in speed, at 70% lower power, NAND-2 delays are 170 ps (FO=2, 3.3 V). Metal-programmable two-port SRAM's feature 3.9 ns typical access times. The new architecture has been implemented in a CMOS gate array family which offers up to 1.15 million available gates and 700 I/O positions     

Variable Input Delay CMOS Logic for Low Power Design

We propose a new complementary metal-oxide semiconductor (CMOS) gate design that has different delays along various input to output paths within the gate. The delays are accomplished by inserting selectively sized ldquopermanently onrdquo series transistors at the inputs of a logic gate. We demonstrate the use of the variable input delay CMOS gates for a totally glitch-free minimum dynamic power implementations of digital circuits. Applying a linear programming method to the c7552 benchmark circuit and using the gates described in this paper, we obtained a power saving of 58% over an unoptimized design. This power consumption was 18% lower than that for an alternative low power design using conventional CMOS gates. The optimized circuits had the same critical path delays as their original unoptimized versions. Since the overall delay was not allowed to increase, the glitch elimination with conventional gates required insertion of delay buffers on noncritical paths. The use of the variable input delay gates drastically reduced the required number of delay buffers.     

Dynamic performance of graded channel DG FD SOI n-MOSFETs for minimizing the gate misalignment effect

Double gate MOSFET has been regarded as the most promising candidate for future CMOS devices, for excellent short channel effects (SCEs) immunity and high current drivability due to double gate coupling. The alignment between the top and bottom gates should be concern to fully realize the benefits of the double-gate configuration, as gate misalignment causes degradation in the device performance. Use of graded channel architectures somehow reduces the effect of gate misalignment. We scrutinize that how the misalignment affects the small signal behavior and device characteristics like conductances, capacitances and cut-off frequency, for uniformly doped and graded channel double gate architectures. Considering the fact that gate misalignment can occur on any side of the gate, extensive simulations have been carried out using high-low (H-L), low-high (L-H) and low-high-low (L-H-L) doping profiles for both source (DGS) and drain side (DGD) gate misalignment.     

Robustness aware high performance high fan-in domino OR logic design

A novel technique using a keeper with a simultaneous low supply voltage and low body voltage is proposed to improve the overall performance of high fan-in OR gates without modifying the physical dimensions of the keeper. Simulation results of a 16-input domino OR gate using 45 nm CMOS technology show that the proposed technique could trade off between a high power/speed efficient operation and the robustness to noise effectively.Also, a Monte Carlo analysis indicates that the proposed domino OR gate is more robust to parameter variation compared to a conventional domino OR gate.     

A subnanosecond 8K-gate CMOS/SOS gate array

An 8370-gate CMOS/SOS gate array has been developed using a Si-gate CMOS/SOS process with two-level metallization. The gate lengths of the transistors are 1.8 and 1.9 /spl mu/m for the n-channel and p-channel, respectively. Subnanosecond typical gate delay times have been obtained. Typical delay times of inverter, two-input NAND, and two-input NOR gates are 0.67, 0.87, and 0.99 ns, respectively, under a typical loading condition (three fan outs and 2 mm first metal). It is shown that ECL speed with CMOS power can be achieved in a system by using the CMOS/SOS gate array. Advantages of the SOS device on speed performance are also discussed.     

Standby power consumption estimation by interacting leakage current mechanisms in nanoscaled CMOS digital circuits

Leakage currents are gaining importance as design parameters in nanometer CMOS technologies. A novel leakage current estimation method, which takes into account the dependency of leakage mechanisms, is proposed for general CMOS complex gates, including non-series-parallel transistor arrangements, not covered by existing approaches. The main contribution of this work is a fast, accurate, and systematic procedure to determine the potentials at transistor network nodes for calculating standby static currents. The proposed method has been validated through electrical simulations, showing an error smaller than 7% and an 80× speed-up when comparing to electrical simulation.     

抗噪声和工艺参数浮动的高性能多输入多米诺或门设计

A novel technique using a keeper with a simultaneous low supply voltage and low body voltage is proposed to improve the overall performance of high fan-in OR gates without modifying the physical dimensions of the keeper.Simulation results of a 16-input domino OR gate using 45 nm CMOS technology show that the proposed technique could trade off between a high power/speed efficient operation and the robustness to noise effectively.Also,a Monte Carlo analysis indicates that the proposed domino OR gate is more robust to parameter variation compared to a conventional domino OR gate.     

A 540 K-transistor CMOS variable-track masterslice

A basic cell structure of p-n-n (a set of one p-channel and two n-channel resistors) is proposed for the cell of a variable-track masterslice (VTM) in order to increase the utilization of logic gates. The masterslice has 180 K p-channel and 360 K n-channel transistors for logic circuitry; it uses 1-3 /spl mu/m double-metal CMOS technology, and has 60 K equivalent (two-input NAND) gates without channel. A small track increment of six or nine allows fine adjustment of the track count in each routing channel. The gate density in p-n-n VTM has been increased by 10 to 30% over a conventional p-n VTM, where p-n represents CMOS pair transistors.     

Estimation of delay variations due to random-dopant fluctuations in nanoscale CMOS circuits

In nanoscale CMOS circuits the random dopant fluctuations (RDF) cause significant threshold voltage (Vt) variations in transistors. In this paper, we propose a semi-analytical estimation methodology to predict the delay distribution [Mean and Standard Deviation (STD)] of logic circuits considering Vt variation in transistors. The proposed method is fast and can be used to predict delay distribution in nanoscale CMOS technologies both at the circuit and the device design phase. The method is applied to predict the delay distributions in different logic gates and flip-flops and is verified with detail Monte Carlo simulations. It is observed that a 30% spread (STD/Mean) in Vt variation results in 5% spread in the delay of logic gates (inverter, NAND, etc.). The effect of Vt variation due to RDF is more significant in the setup time (STD/Mean = 11%) and clock-to-output delay (STD/Mean = 5% to 25%) of flip-flops.     

Input mapping algorithm for modelling of CMOS circuits

An algorithm for mapping every possible input pattern of a complementary metal oxide semiconductor (CMOS) gate to an equivalent set of normalised inputs (inputs which have the same starting point and transition time) is presented. Such an algorithm is required in order to perform analytical modelling of CMOS gates, and the results obtained are very accurate compared to SPICE simulations