SRAM型FPGA单粒子翻转模拟系统研究

SRAM型FPGA在空间辐照环境下,容易受到单粒子效应的影响,导致FPGA存储单元发生位翻转,翻转达到一定程度会导致功能错误。为了评估FPGA对单粒子效应的敏感程度和提高FPGA抗单粒子的可靠性,对实现故障注入的关键技术进行了研究,对现有技术进行分析,设计了单粒子翻转效应敏感位测试系统,利用SRAM型FPGA部分重配置特性,采用修改FPGA配置区数据位来模拟故障的方法,加速了系统的失效过程,实现对单粒子翻转敏感位的检测和统计,并通过实验进行验证,结果表明:设计合理可行,实现方式灵活,成本低,为SRAM型FPGA抗单粒子容错设计提供了有利支持。     

SRAM型FPGA单粒子翻转测试及加固技术研究

SRAM型FPGA空间应用日益增多,只有针对其特点设计相应的单粒子试验的测试程序才能系统、准确地获取该类芯片的单粒子翻转特性,为抗辐射加固设计提供依据.阐述了单粒子翻转的静态和动态的测试方法.静态测试包括硬件设计和配置位回读程序的设计;动态测试主要针对CLB(配置逻辑单元)和BRAM(块存储器)两部分进行了相应的软件测...     

基于定向故障注入的SRAM型FPGA单粒子翻转效应评估方法

介绍了一种基于定向故障注入的SRAM型FPGA单粒子翻转效应评估方法。借助XDL工具,该方法解析了Virtex-4 SX55型FPGA的帧地址与物理资源之间的对应关系;将电路网表中的资源按模块分组,利用部分重构技术分别对电路整体及各分组相关的配置帧进行随机故障注入,以评估电路整体及其子模块的抗单粒子翻转能力;按模块分组对电路分别进行部分三模冗余(TMR)加固和故障注入实验,以比较不同加固方案的效果。实验结果表明:电路的抗单粒子翻转能力与其功能和占用的资源有关;在FPGA资源不足以支持完全TMR的情况下,该方法可以帮助设计者找到关键模块并进行有效的电路加固。     

超大规模FPGA的单粒子效应脉冲激光测试方法

建立了一种28 nm HPL硅工艺超大规模SRAM型FPGA的单粒子效应测试方法。采用静态测试与动态测试相结合的方式,通过ps级脉冲激光模拟辐照实验,对超大规模FPGA进行单粒子效应测试。对实验所用FPGA的各敏感单元(包括块随机读取存储器、可配置逻辑单元、可配置存储器)的单粒子闩锁效应和单粒子翻转极性进行了研究。实验结果证明了测试方法的有效性,揭示了多种单粒子闩锁效应的电流变化模式,得出了各单元的单粒子效应敏感性区别。针对块随机读取存储器、可配置逻辑单元中单粒子效应翻转极性的差异问题,从电路结构方面进行了机理分析。     

Virtex FPGA抗单粒子翻转技术

SRAM型FPGA开发过程灵活,在航天领域有广泛的应用,但该系列FPGA易发生单粒子翻转事件,导致功能中断或信息丢失。配置刷新结合三模冗余能有效抑制单粒子翻转带来的影响。在详细讨论了配置刷新+三模冗余的基础上,提出了FPGA自主刷新+三模冗余的解决方案,保证FPGA抗单粒子性能的基础上提高了系统的资源利用率,经注错试验验证了方案可行性。     

基于FPGA定时刷新控制单元的应用技术研究

SRAM型FPGA在航天领域有着广泛的应用,为解决FPGA在宇宙环境中单粒子翻转的问题,适应空间应用需求,给出了一种低成本抗辐照解决方案,对耐辐射FPGA器件进行抗单粒子翻转加固设计。该方案兼容多种型号FPGA芯片,从3片SPI FLASH中读取配置数据,通过串行接口配置FPGA,并在配置完成后按照设定时间周期性刷新芯片,可以满足航天领域对抗辐照型FPGA的使用需求。     

一种SRAM型FPGA单粒子效应故障注入方法

随着FPGA在航天领域的广泛应用,SRAM型FPGA的单粒子故障也越来越引起人们的重视,用故障注入技术模拟单粒子效应是研究单粒子效应对SRAM器件影响的重要手段,该文主要研究SRAM型FPGA单粒子翻转、单粒子瞬态脉冲的故障注入技术,并在伴随特性的基础上,提出一种单粒子瞬态脉冲故障注入技术。该方法使注入故障脉冲宽度达到...     

SRAM型FPGA单粒子翻转故障定位注入研究

针对SRAM型FPGA用户设计电路可靠性评测问题,提出了一种基于FPGA配置资源位置的模拟FPGA单粒子翻转故障的定位注入方法。分别从SRAM型FPGA中的配置逻辑资源与用户逻辑资源两个方面对此方法进行了详细介绍,并且通过对LUT与BRAM两种资源的故障注入试验说明了此方法的有效性。对故障注入方法、故障注入系统、故障注入试验进行了介绍,说明了故障定位注入方法能够对用户设计电路中用到的关键资源进行测试,资源覆盖率高、耗时短,为针对大量配置逻辑资源进行故障定位注入,实施反复测试提供了时效前提,具有很强的实用性。     

一种静态随机存储器型现场可编程门阵列的单粒子软错误率的软件分析方法

静态随机存取存储器(SRAM)型现场可编程门阵列(FPGA)在当前空间电子设备中取得了广泛的应用,尽管它对空间辐射引起的单粒子翻转效应极其敏感。在FPGA的配置存储器中发生的单粒子翻转造成的失效机理不同于传统的存储器中的单粒子翻转。因此,如何评价这些单粒子翻转对系统造成的影响就成了一个值得研究的问题。传统的方法主要分为辐照实验和故障注入两种技术途径。本文中提出了一种新的方法,可以用来分析单粒子翻转对构建在FPGA上的系统造成的影响。这种方法基于对FPGA底层结构以及单粒子翻转带来的失效机理的深入理解,从布局布线之后的网表文件出发,寻找所有可能破坏电路结构的关键逻辑节点和路径。然后通过查询可配置资源与相应的配置数据之间关系来确定所有敏感的配置位。我们用加速器辐照实验和传统的故障注入方法验证了这种新方法的有效性。     

模拟低空环境下FPGA的SEU测试系统结果分析

为了探究在低空环境下SRAM型FPGA产生单粒子翻转事件与大气中高能粒子剂量的关系,设计了一种便携式测试系统。使用该系统在某地6个不同海拔的测试点对SRAM型FPGA进行单粒子翻转测试。某地平均海拔在3000～5000 m,可以很好地模拟低空飞行环境。通过测试试验,该系统获得了大量现场数据,使用Matlab对测试数据进行了分析。结合在某地的测试结果,从SRAM型FPGA的存储结构、单粒子翻转产生机理、测试系统的工作原理等方面入手,对该测试系统的科学性与实用性进行了验证分析。分析结果表明,该便携式测试系统科学有效,可为航空航天领域中SRAM型FPGA的选型与使用提供一种参考方式。     

基于码流的软件控制FPGA故障注入系统

基于静态随机存储器的现场可编程逻辑门阵列应用于航天电子系统时,易受到单粒子翻转效应的影响,存储数据会发生损坏。为评估器件和电路在单粒子翻转效应下的可靠性,提出一种基于TCL脚本控制的故障注入系统,可在配置码流层面模拟单粒子翻转效应。介绍了该故障注入系统的实现机制和控制算法,并将该软件控制方法与传统硬件控制方法进行对比分析。设计了一种关键位故障模型,从设计网表中提取关键位的位置信息,缩小了故障注入的码流范围。在Virtex-5开发板XUPV5-LX110T上的故障注入实验表明,该故障注入系统能有效模拟单粒子翻转效应,与传统随机位故障注入相比,关键位故障注入的故障率提高了近5倍。     

面向航空环境的多时钟单粒子翻转故障注入方法

随着新型电子器件越来越多地被机载航电设备所采用,单粒子翻转(Single Event Upset, SEU)故障已经成为影响航空飞行安全的重大隐患。首先,针对由于单粒子翻转故障的随机性,该文对不同时刻发生的单粒子翻转故障引入了多时钟控制,构建了SEU故障注入测试系统。然后模拟真实情况下单粒子效应引发的多时间点故障,研究了单粒子效应对基于FPGA构成的时序电路的影响,并在线统计了被测模块的失效数据和失效率。实验结果表明,对于基于FPGA构建容错电路,采用多时钟沿三模冗余(Triple Modular Redundancy, TMR) 加固技术可比传统TMR技术提高约1.86倍的抗SEU性能;该多时钟SEU故障注入测试系统可以快速、准确、低成本地实现单粒子翻转故障测试,从而验证了SEU加固技术的有效性。     

Hybrid time and hardware redundancy to mitigate SEU effects on SRAM-FPGAs: Case study over the MicroLAN protocol

SRAM-based field programmable gate arrays (FPGAs) are particularly sensitive to single event upsets caused by high-energy space radiation. Single Event Upset (In order to successfully deploy the SRAM-FPGA based designs in aerospace applications, designers need to adopt suitable hardening techniques. In this paper, we describe novel hybrid time and hardware redundancy (HT&HR) structures to mitigate SEU effects on FPGA, especially digital circuits that are designed with bidirectional ports. The proposed structures that combine time and hardware redundancy decrease the SEU propagation mechanisms among the redundant hard units. Analysis results and fault injection experiments on some standard ISCAS benchmarks and MicroLAN protocol, as a case study over the bidirectional ports, show that the capability of tolerating SEU effects in HT&HR technique increases up to 70 times with respect to solely hardware redundant versions. On average, the proposed method provides 39.2 times improvement against single upset faults and 14.9 times for double upset faults; however it imposes about 14.7% area overhead. Also, for the considered benchmarks, HT&HR circuits become 8.8% faster on the average than their TMR versions.     

Towards an efficient SEU effects emulation on SRAM-based FPGAs

A novel fault injection approach, reproducing results obtained from radiation ground testing while studying the Single Event Upset (SEU) effects on SRAM-based Field Programmable Gate Arrays (FPGAs), is presented. This approach can take into account the relative sensitivity difference between configuration bits set to ‘0’ and those set to ‘1’. According to irradiation experiments conducted under proton beam for a Xilinx Virtex-5 FPGA at the TRIUMF lab, configuration bits set to ‘1’ are approximately twice as sensitive as bits set to ‘0’. This fact was exploited in test sequence generation while performing fault injection experiments, in order to generate more realistic emulation results. The effectiveness of the approach is validated by comparing its results to those obtained with proton radiation tests, for two different ring-oscillator-based experimental setups. It shows that taking this sensitivity into account helps obtain more realistic results while dealing with delays induced by radiation, which justifies considering this relative sensitivity during fault emulation. In fact, comparing the results obtained from the proposed approach to those obtained at TRIUMF gives an absolute relative error of 3.1 and 14%, respectively, for the first and the second setups, while estimating the error between the latter and results from a conventional random fault injection provides error values of up to 75%. Finally, applying our fault injection approach on a more conventional circuit reveals that taking the relative sensitivity difference into account leads to 2.3 times as many errors detected as with random injection. This last result suggests that not taking the relative sensitivity difference into account during emulation can lead to an underestimation of a design sensitivity to radiation.     

真实FPGA器件下单粒子软错误评估工具设计

FPGA器件在航天领域应用广泛,然而在空间环境下,基于SRAM工艺的FPGA器件极易受到单粒子翻转(Single Event Upsets,SEU)影响而导致电路发生软错误。针对具有代表性的Xilinx Virtex系列器件进行了SEU评估方法的研究,设计并开发了一款面向Virtex器件的SEU效应评估工具,并与FPGA标准设计流程进行了有效融合。实验结果表明,提出的评估方法和工具对Virtex器件的SEU效应可以进行准确的评估,从而为FPGA结构设计和应用开发提供先于硬件实现的软件验证环境,对高可靠性FPGA芯片的研究、开发和设计都具有重要意义。     

NEW APPROACH TO EMULATE SEU FAULTS ON SRAM BASED FPGAS简

Field Programmable Gate Arrays （FPGAs） offer high capability in implementing of com- plex systems, and currently are an attractive solution for space system electronics. However, FPGAs are susceptible to radiation induced Single-Event Upsets （SEUs）. To insure reliable operation of FPGA based systems in a harsh radiation environment, various SEU mitigation techniques have been provided In this paper we propose a system based on dynamic partial reconfiguration capability of the modern devices to evaluate the SEU fault effect in FPGA. The proposed approach combines the fault injection controller with the host FPGA, and therefore the hardware complexity is minimized. All of the SEU injection and evaluation requirements are performed by a soft-core which realized inside the host FPGA Experimental results on some standard benchmark circuits reveal that the proposed system is able to speed up the fault injection campaign 50 times in compared to conventional method.     

A fast,flexible, and easy-to-develop FPGA-based fault injection technique

By technology down scaling in nowadays digital circuits, their sensitivity to radiation effects increases, making the occurrence of soft errors more probable. As a consequence, soft error rate estimation of complex circuits such as processors is becoming an important issue in safety- and mission-critical applications. Fault injection is a well-known and widely used approach for soft error rate estimation. Development of previous FPGA-based fault injection techniques is very time consuming mainly because they do not adequately exploit supplementary FPGA tools. This paper proposes an easy-to-develop and flexible FPGA-based fault injection technique. This technique utilizes debugging facilities of Altera FPGAs in order to inject single event upset (SEU) and multiple bit upset (MBU) fault models in both flip-flops and memory units. As this technique uses FPGA built-in facilities, it imposes negligible performance and area overheads on the system. The experimental results show that the proposed technique is on average four orders of magnitude faster than a pure simulation-based fault injection. These features make the proposed technique applicable to industrial-scale circuits.     

Estimating the SEU failure rate of designs implemented in FPGAs in presence of MCUs

Due to the continuous reduction of the transistor size in electronic devices, it is becoming more and more likely for an SEU (Single Event Upset) to provoke a flip on two or more memory cells in SRAM based FPGAs, which is called a MCU (Multiple Cell Upset). Fault injection in the configuration memory of these devices has been used for many years, in order to evaluate their reliability. Emulation of these injections using the bitstream file has always been a simple, fast and cheap solution. Most of the existent SEU emulation tools do not consider the injection of MCUs, and they do not discuss the implication MCUs have on the overall failure rate of the system.In this work, bitstream based SEU emulators are updated to consider MCUs. It is discussed the necessity of injecting faults on physically adjacent cells, in order to emulate appropriately the effect of MCUs. Adjacent MCU injection has been compared theoretically with an approach considering MCUs as bunches of independent SBUs, as it is done in other emulation platforms. A Zynq-based fault injection platform has been used, in order to apply this way of emulating MCUs and validate the proposal.     

Virtex-Ⅱ系列FPGA的回读与部分重配置

介绍了基于SRAM的Virtex-Ⅱ系列FPGA试验样板的系统功能,实现了对XQ2V3000FPGA的回读与部分重配置,并给出了JTAG接口下的时序,最后分析了试验的结果。结果表明,FPGA回读可以有效地检测FPGA是否发生了单粒子翻转,而部分重配置可以有效地降低FPGA发生翻转的累积效应,并修复系统功能。