中小型电站和变电所的集成电路逻辑控制

本文介绍一种适用于中小型电站和变电所的集成电路逻辑控制装置的主体部分。该控制装置采用弱电选线操作方式，逻辑电路部分主要由ＣＭＯＳ集成电路组成。电路的逻辑功能较强，操作方便可靠。对于使用集成电路保护的电站和变电所，再配套使用集成电路逻辑控制是非常合适的。     

用于三相桥式电路的600V驱动集成电路

介绍了一种６００Ｖ单片式智能驱动集成电路，它可连接ＴＴＬ，ＣＭＯＳ逻辑电路与三相桥式电路之间，用以驱动ＭＯＳ栅极器件。本文给出了该驱动电路在步进电机，高频镇流器中的应用电路。     

系统电压畸变时STATCOM的运动性能研究

基于ＳＴＡＴＣＯＭ的标幺值数学模型,研究了系统电压畸变条件下ＳＴＡＴＣＯＭ的电压电流运行特性,讨论了ＳＴＡＴＣＯＭ谐波电压电流与装置主电路参数的关系,给出了ＬＣ谐波条件,理论分析结果得到了ＰＳＣＡＤ／ＥＭＴＤＣ数字仿真以及１０ｋｖａｒ ＳＴＡＴＣＯＭ动模装置实验的双重验证。     

用CMOS集成电路给TD4652型示波器增加时标功能

本文结合ＴＤ４６５２型示波器，介绍了示波器的时标显示功能及基本控制方法。并给出了由ＣＭＯＳ集成电路构成的时标信号发生电路，说明了用该电路给无时标功能的示波器增加时标电路的实现方法。     

0.1C5A标准镉镍电池充电器

介绍一种由电容和ＣＭＯＳ集成电路组成的镉镍电池充电器，阐述恒流与定时充电电路的原理、制作以及注意事项。     

统一潮流控制器电磁暂态过程数字仿真的初步研究

首先对ＵＰＦＣ并联部分ＳＴＡＴＣＯＭ的电磁暂态特性进行了详细的仿真。采用ＧＴＯ结构的逆变器,构造了两种类型的ＳＴＡＴＣＯＭ产暂态模型。在ＳＴＡＴＣＯＭ仿真的基础上,进行了ＵＰＦＣ一些电磁暂态特性的仿真。仿真采用了常规的ＰＩＤ控制方法,适当选取了ＰＩＤ参数,能够使设备表现出良好的性能。仿真结果表明,,ＰＵＦＣ能够对系统的潮流和电压进行有效的控制。仿真工作晃应用ＥＭＴＰ进行的。     

可变系数脉冲计数器

本文介绍一种可变系数脉冲计数器，将它与流量计、里程计等配用时，只要将系数设置好，所显示的数字就是实际的升、公斤或公里，极为方便。文中仪表采用中小规模ＣＭＯＳ集成电路，六位液晶显示屏，省电，静态电流为３～５ｍＡ。文中给出了电路的电原理图。     

一种新颖的电流模式高通滤波器

提出了一种利用电流传送器（ＣＣ）设计连续时间电流模式高通滤波器方法。在设计中,引入了多端输出电流传送器（ＭＯＣＣ）,并给出了ＭＯＣＣ简单的实现电路。基于典型ＦＬＦ结构的模拟,获得了一般高阶高通滤波器的电流模式ＭＯＣＣ结构。文中给出了系统的设计公式。做为例子,文中设计了一个四阶Ｂｕｔｔｅｒｗｏｒｔｈ高通滤波器,模拟仿真结果与理论分析吻合。     

采用EPLD构成的多路位置角检测电路

介绍了一种采用高密度Ｅ＾２ＣＭＯＳ可编程逻辑器件（ＥＰＬＤ）构成的多路位置检测电路。该电路具有结构简单,可靠性高,成本低廉等优点。     

静止同步补偿器的标幺化模型及开环响应时间常数分析

静止同步补偿器（ＳＴＡＴＣＯＭ）的标幺化建模是迄今为止国内外都没有得到解决的难题。作者在开发 同容量的ＳＴＡＴＣＯＭ装置所积累的理论和工程经验的基础上,提出了一个真正标幺化意义上的ＳＴＡＴＣＯＭ数学模型,并以此数学模型为基础,揭示了ＳＴＡＴＣＯＭ开环响应时间常数与装置主电路参数的相互关系。该模型为ＳＴＡＴＣＯＭ的各种稳态暂态性能分析及控制器参数设计提供了系统化方法。     

Analog CMOS integrated circuit design: research and undergraduateteaching

The authors describe the use of software that was developed as part of a research program in analog CMOS integrated circuit design for an undergraduate course on analog VLSI design. The software includes some unusual uses of readily available, inexpensive, and easy-to-use programs available for microcomputers such as Macintosh or IBM-PC clones. Although initially intended to help with the design of CMOS operational amplifiers, the IC design method used is very general; other possible applications are described. The flexibility of these programs also allows them to be used with other CAD (computer-aided design) software, including circuit simulators and programs for schematic entry and layout. The software tools allow undergraduate students to complete analog CMOS integrated circuit designs using advanced CAD techniques but without being overwhelmed or losing touch with the underlying circuit design principles. Details of the programs and their use are presented together with the resulting analog IC designs fabricated using MOSIS (MOS Implementation Service)     

Compressive image acquisition in modern CMOS IC design

Compressive sampling (CS) offers bandwidth, power, and memory size reduction compared to conventional (Nyquist) sampling. These are very attractive features for the design of modern complementary metal‐oxide semiconductor (CMOS) image sensors, cameras, and camera systems. However, very few integrated circuit (IC) designs based on CS exist because of the missing link between the well‐established CS theory on one side, and the practical aspects/effects related to physical IC design on the other side. This paper focuses on the application of compressed image acquisition in CMOS image sensor integrated circuit design. A new CS scheme is proposed, which is suited for hardware implementation in CMOS IC design. All the main physical non‐idealities are explained and carefully modeled. Their influences on the acquired image quality are analyzed in the general case and quantified for the case of the proposed CS scheme. The presented methodology can also be used for different CS schemes and as a general guideline in future CS based CMOS image sensor designs. Copyright © 2013 John Wiley & Sons, Ltd.     

MOS型集成电路在防爆应急灯具的应用

设计了一款采用MOS型集成电路驱动防爆应急灯。它内置有检测、控制、保护、驱动等多个功能模块,是一种高低压混合集成电路,完全可以满足防爆应急灯系统要求,并且该集成电路的逻辑控制部分和高压驱动部分都采用CMOS工艺,明显降低功耗、提高可靠性。     

A wide variable‐range CMOS–VCXO for IC

Recently, miniaturization, low power consumption, and high‐frequency stability have been required in crystal oscillators as a frequency source, because of the rapid development of mobile communications, typified by cellular phones. Usually, a VCXO (Voltage Controlled Crystal Oscillator) has been included in PLL. And it has been required that the VCXO should be implemented on a CMOS–IC chip. The oscillating frequency of a traditional VCXO has been controlled by capacitance variation of a varactor diode. But it is difficult to implement the varactor diode on an IC chip. In our previous study, we showed that a transistor VCXO utilizing the MOSFET's Miller capacitance of a variable capacitance circuit had a wide frequency variable range. On the other hand, in a CMOS–VCXO, the Miller capacitance has decreased. Therefore, a wide frequency variable range could not be obtained by utilizing the Miller capacitance in the CMOS–VCXO. In this paper, first, a variable capacitance circuit is realized in order to construct a wide‐variable‐range CMOS–VCXO for IC. The variable capacitance circuit is composed of a MOSFET as a voltage controlled resistance. Next, the CMOS–VCXO is constructed by the variable capacitance circuit and a CMOS crystal oscillator. As a result, we show that the CMOS–VCXO has a wide frequency variable range of about 400 ppm.© 1999 Scripta Technica, Electr Eng Jpn, 130(3): 49–56, 2000     

Overview of on-chip electrostatic discharge protection design with SCR-based devices in CMOS integrated circuits

An overview on the electrostatic discharge (ESD) protection circuits by using the silicon controlled rectifier (SCR)-based devices in CMOS ICs is presented. The history and evolution of SCR device used for on-chip ESD protection is introduced. Moreover, two practical problems (higher switching voltage and transient-induced latchup issue) limiting the use of SCR-based devices in on-chip ESD protection are reported. Some modified device structures and trigger-assist circuit techniques to reduce the switching voltage of SCR-based devices are discussed. The solutions to overcome latchup issue in the SCR-based devices are also discussed to safely apply the SCR-based devices for on-chip ESD protection in CMOS IC products.     

Advanced Plasma and Advanced Gate Dielectric—A Charging Damage Prospective

Current status of plasma charging damage is assessed. The impact of wide adaptation of high density plasma in IC processing to charging damage is examined for advanced CMOS technology where ultrathin gate oxide is used. The issue of measurement is high-lighted. The resulting misconception of plasma charging damage is no longer a problem when gate oxide is ultrathin is explained as a result of measurement difficulty as well as previously unexpected longer oxide lifetime.     

Engineering strained silicon-looking back and into the future

The purpose of this article is to explain the basics behind straining and report on the current process technologies available to strain CMOS devices. Strained Si enhances the performance of CMOS devices by increasing carrier mobility without having to make them smaller. As the benefits to be gained from scaling transistors continue to decrease, the commercial interest in using strained Si for CMOS devices has spiked. Additionally, strained Si still retains its integratability in CMOS manufacturing processes, unlike any other semiconductor material. Thus the real test for engineers lies in the ability to cost-effectively develop and apply strained Si technology into current CMOS process. Thus new methods for straining Si is integrated into IC manufacturing as industry interest in this technology continues to grow and also increases the speed, performance and functions of the circuits.     

A 5‐MHz AT‐cut quartz crystal oscillating circuit functioning in 350 nA

An oscillating circuit functioning at ultra low power (350 nA) for a 5‐MHz AT‐cut quartz crystal oscillator was investigated. This circuit has a resistance between the power terminal of the CMOS‐IC and the power supply, and another between the earth terminal of the CMOS‐IC and the ground (GND). These resistances discourage an inrush of current, and set a gain (g_m) necessary for oscillating the circuit at minimum. The developed circuit is quite simple, but enables driving at once‐unthinkable, low power (below 1 µA). © 2007 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.     

The boundary scan

Miniaturization trends in integrated circuit (IC) technology have caused many testing problems. As bigger packaged ICs with higher pin counts are more densely packed onto a printed circuit board (PCB), accessing an IC's pins is harder. No longer are the pins mechanically accessible to probes or a bed-of-nails fixture. Therefore, determining which IC or interconnect is faulty is difficult or impossible. Because each IC's input pins cannot be controlled, and each IC's output pins cannot be observed. The boundary scan method was developed with the goal of improving this controllability and observability problem. A shift-register is included next to each IC pin so that input and output values can be serially shifted in and out. This reduces the need to use probes to control and observe. Also, the output of each IC's scan register can be connected with the input of another IC's scan register. This effectively creates one big scan chain per PCB, further reducing points that must be mechanically probed. The inclusion of a scan-register on each IC allows: 1) the observation of each IC during normal operation; 2) the test of interconnects between ICs, and 3) the isolation of the IC from others so it can test itself. The IEEE Standard 1149.1 Test Access-Port and Boundary Scan defines the test logic for implementing a boundary scan test architecture. Example circuits were designed in CMOS. A boundary scan cell is described     

MSM6242集成电路在定时中的应用

本文对MSM6242集成电路进行简介,并且通过实例对该集成电路的长定时的使用方法和定时范围做了详细的介绍。从中可以看出它的定时范围要比一般定时器大很多。