Efficient Hardware/Software Implementation of an Adaptive Neuro-Fuzzy System

This paper describes the development of efficient hardware/software (HW/SW) neuro-fuzzy systems. The model used in this work consists of an adaptive neuro-fuzzy inference system modified for efficient HW/SW implementation. The design of two different on-chip approaches are presented: a high-performance parallel architecture for offline training and a pipelined architecture suitable for online parameter adaptation. Details of important aspects concerning the design of HW/SW solutions are given. The proposed architectures have been implemented using a system-on-a-programmable-chip. The device contains an embedded-processor core and a large field programmable gate array (FPGA). The processor provides flexibility and high precision to implement the learning algorithms, while the FPGA allows the development of high-speed inference architectures for real-time embedded applications.     

基于改进0-1动态规划的软硬件划分算法研究*

软硬件划分已被证明是NP完全问题,大多数研究主要集中在寻找各种快速的近似算法,常见的有爬山法、遗传算法、模拟退火、禁忌搜索等.这些算法大多只能处理小规模问题,而且是单纯从算法角度来研究软硬件划分问题,并没有考虑系统成本.以软硬件协同函数库为统一抽象模型,将系统执行时间、系统成本以及硬件面积等因素融入到0-1动态规划算法...     

Neuro-fuzzy control of antilock braking system using sliding mode incremental learning algorithm

A neuro-fuzzy adaptive control approach for nonlinear dynamical systems, coupled with unknown dynamics, modeling errors, and various sorts of disturbances, is proposed and used to design a wheel slip regulating controller. The implemented control structure consists of a conventional controller and a neuro-fuzzy network-based feedback controller. The former is provided both to guarantee global asymptotic stability in compact space and as an inverse reference model of the response of the controlled system. Its output is used as an error signal by an incremental learning algorithm to update the parameters of the neuro-fuzzy controller. In this way the latter is able to gradually replace the conventional controller from the control of the system. The proposed new learning algorithm makes direct use of the variable structure systems theory and establishes a sliding motion in terms of the neuro-fuzzy controller parameters, leading the learning error toward zero. In the simulations and in the experimental studies, it has been tested on the control of antilock breaking system model and the analytical claims have been justified under the existence of uncertainty and large nonzero initial errors.     

SoC设计中支持软硬件划分的虚拟微处理器

在SoC系统软硬件协同没计过程中，采用WISHBONE总线协议标准来构造虚部件级SoC系统，将经过软硬件划分后的软件和硬件在虚部件级进行协同仿真，再进行实部件级的综合。提出了一种基于ARMSim仿真内核的虚部件级微处理器(虚拟微处理器)的模型构造方法，可以简化SoC系统的设计。     

嵌入式系统芯片中SM2算法软硬件协同设计与实现

针对现有的椭圆曲线算法系统级设计中开发周期长,以及不同模块的性能开销指标不明确等问题,提出一种基于电子系统级(ESL)设计的软硬件(HW/SW)协同设计方法.该方法通过分析SM2(ShangMi2)算法原理与实现方式,研究了不同的软硬件划分方案,并采用统一建模语言SystemC对硬件模块进行周期精确级建模.通过模块级与系统级两层验证比较软硬件模块执行周期数,得出最佳性能划分方式.最后结合算法控制流程图(CFG)与数据流程图(DFG)将ESL模型转化为寄存器传输级(RTL)模型进行逻辑综合与比较,得出在180 nm CMOS工艺,50 MHz频率下,当算法性能最佳时,点乘模块执行时间为20 ms,门数83 000,功耗约2.23 mW.实验结果表明所提系统级架构分析对基于椭圆曲线类加密芯片在性能、面积与功耗的评估优势明显且适用性强,基于此算法的嵌入式系统芯片(SoC)可根据性能与资源限制选择合适的结构并加以应用.     

基于ESL的MEPG-4解码SoC软硬件协同设计

随着SoC(System on Chip)系统设计复杂度的不断提高,设计前期在系统级别进行软硬件规划对SoC 性能的影响日趋增加,在复杂视频解码SoC 设计中迫切需要高效的性能分析和验证平台从架构层次上优化性能.将基于电子系统级设计(Electronic System Level , ESL)仿真方法在MPEG-4 视频解码SoC 软硬件协同设计中的应用,利用ARM SoC-Designer ESL 平台分析软件算法的瓶颈,实现软硬划分.通过SystemC 对硬件单元周期精确建模,最终实现了MEPG-4 解码软硬件协同仿真验证.实践证明利用ESL 进行系统设计不仅可以有效提高仿真速度而且设计的视频解码硬件能有效改善系统的性能.     

面向SoC的软硬件协同验证平台设计

针对SoC设计验证的实际需求,介绍一种面向SoC设计的软硬件协同验证平台。平台中软硬件模型分别在不同环境下运行,通过网络实现信息交互。硬件用硬件描述语言实现对系统事务级、RTL级的建模,软件用高级编程语言来编写,使用指令集仿真器完成对硬件的仿真。仿真过程使用不同的进程并行进行,应用进程间通信方式实现仿真器之间的信息交互。     

SoC芯片验证技术的研究

近几年来,SoC技术已经得到了迅速的发展,随之而来的是SoC设计的验证也变得更加复杂,花费的时间和人力成倍增加。一个SoC芯片的验证可能会用到多种验证技术,常用的SoC的验证技术包括SoC的模拟仿真技术、静态时序分析技术、SoC的FPGA验证技术、SoC的形式验证技术以及SoC的软硬件协同验证技术等。本文讨论了这几种验证技术的特点以及在SoC设计中的作用。     

MODELING AND CONTROL OF INTERNAL COMBUSTION ENGINES USING INTELLIGENT TECHNIQUES

This article will compare two different fuzzy-derived techniques for controlling small internal combustion engine and modeling fuel spray penetration in the cylinder of a diesel internal combustion engine. The first case study is implemented using conventional fuzzy-based paradigm, where human expertise and operator knowledge were used to select the parameters for the system. The second case study used an adaptive neuro-fuzzy inference system (ANFIS), where automatic adjustment of the system parameters is affected by a neural networks based on prior knowledge. The ANFIS model was shown to achieve an improved accuracy compared to a pure fuzzy model, based on conveniently selected parameters. Future work is concentrating on the establishment of an improved neuro-fuzzy paradigm for adaptive, fast and accurate control of small internal combustion engines.     

多选择软硬件划分问题的计算模型与动态规划算法

软硬件划分是软硬件协同设计的关键环节,划分的结果直接影响目标系统的设计质量。因此,对于一个给定的应用程序,为了使得目标系统快速执行且成本低廉,合理的划分策略十分重要。由于单个任务具有多种不同的硬件实现方式,与传统的单一硬件实现方式的软硬件划分问题相比,多选择的软硬件划分更能客观地反映现实应用。这导致问题的求解更具挑战性,它们已被证明是NP完全问题。基于多核处理器片上系统并针对任务图为二叉树的应用,建立了多选择软硬件划分问题的计算模型,并提出了解决该问题的动态规划算法。实验结果表明,当问题规模适中时,所提动态规划算法能够有效地获得精确解,并展示了算法的计算能力与硬件面积限制之间的关系。     

Efficient heuristic and tabu search for hardware/software partitioning

Hardware/software (HW/SW) partitioning is a crucial step in HW/SW codesign that determines which components of the system are implemented on hardware and which ones on software. It has been proved that the HW/SW partitioning problem is NP-hard. In this paper, we present two approaches for HW/SW partitioning that aims to minimize the hardware cost while taking into account software and communication constraints. The first is a heuristic approach that treats the HW/SW partitioning problem as an extended 0–1 knapsack problem. In the second approach, tabu search is used to further improve the solution obtained from the proposed heuristic algorithm. Experimental results show that the proposed algorithms outperform a recently reported work by up to 28 %.     

采用动态译码缓存的高速指令集模拟器

指令集模拟器是计算机体系结构研究和SoC软硬件协同设计的重要工具，模拟器的性能和灵活性是影响设计和验证效率的重要因素。解释型指令集模拟器具有很好的灵活性，在操作系统等涉及到自修改代码的模拟中具有不可替代的作用。该文给出了一个高性能解释型指令集模拟器的设计，它具有很高的模拟精度和很好的灵活性；同时指令集模拟器采用了动态译码缓存等优化技术，使其具有很高的模拟性能。以ARM7指令集模拟器为实例，所提出的优化技术同样适用于其它现心RISC体系结构。     

过程级动态划分的RSoC软硬件双通信模式

软硬件通信模式的选择对软硬件通信效率产生很大影响.根据硬件函数的特点,提出一种根据软硬件通信量自适应地选择通信模式的软硬件双通信模式,并构建了一种通信模式自适应决策算法,软硬件通信模式的选择对用户透明.实验表明,根据运行时系统状态自适应地选择通信模式,软硬件通信效率得到优化,面积开销也适当减少.     

面向UMPC的北大众志-SK系统芯片设计

如何更好地满足3C融合的需求,是超便携个人计算机(UMPC)普及的关键.北大众志-SK系统芯片,将传统个人计算机中分布在主板上的中央处理器、北桥与南桥芯片组、显示控制器和其它输入输出控制设备等众多芯片的功能集成到单一芯片中.该系统芯片采用2D/3D扩展指令、软硬协同视频解码加速部件、硬件视频编解码等方式,在高效完成多媒体处理的前提下,有效降低了对中央处理器性能的需求.通过在单芯片内部实现多层次的存储架构,简化了数据的传输路径,提高了数据传输的效率,从而提高系统性能.此外,在该系统芯片中还实现了众多主流的输入输出接口控制部件,以满足个人计算机的日常应用需求.该设计达到了高集成度、高性能、低功耗的设计目标,提供了面向教育、电子政务和个人信息处理等领域的低成本、低功耗、易使用、便于维护的UMPC解决方案.     

基于DSP的转子磁场定向感应电机控制系统实现

本文介绍了一种采用磁链和开环速度估算器的转子磁场定向的控制系统,系统设计的的关键问题是磁链的观测和速度的准确估算。在系统动态过程中,电机的一些定、转子参数会随着电机温升和磁路饱和的影响而发生变化,是时变参数,本文按照模型参考自适应系统构造出参考模型和可调模型来实现了扩展卡尔曼滤波对磁链和电机转速的估算,并成功应用此算法设计了一套DSP实验控制系统,实现了速度自适应识别。同时本文介绍了DSP实验系统的硬件和软件实现方法并对实验结果进行了分析。模型试验应用于1.0kW的感应电机取得了较好的的控制效果。     

C高层建模设计MPEG-4解码SoC芯片

本文针对ARM946-S运用软硬件协同设计方法设计了一款低成本的MPEG-4解码系统芯片(SoC)。为了缩短验证时间和提高验证充分性,本文采用了基于C参考模型的验证方法。仿真结果表明芯片性能提升明显,针对MPEG-4 Simple Profile L3 Level最坏情况需130MHz就能实时解码。     

CONTREX: Design of embedded mixed-criticality CONTRol systems under consideration of EXtra-functional properties

The increasing processing power of today’s HW/SW platforms leads to the integration of more and more functions in a single device. Additional design challenges arise when these functions share computing resources and belong to different criticality levels. CONTREX complements current activities in the area of predictable computing platforms and segregation mechanisms with techniques to consider the extra-functional properties, i.e., timing constraints, power, and temperature. CONTREX enables energy efficient and cost aware design through analysis and optimization of these properties with regard to application demands at different criticality levels. This article presents an overview of the CONTREX European project, its main innovative technology (extension of a model based design approach, functional and extra-functional analysis with executable models and run-time management) and the final results of three industrial use-cases from different domain (avionics, automotive and telecommunication).     

一种基于SoC平台设计的AVS解码器软硬件分区结构

视频解码芯片的结构因硬件强大的处理能力和软件灵活的可编程功能从硬件转向软硬件分区结构。该文针对AVS标准的算法和解码实现复杂程度,根据软硬件协同设计思想提出了一种结构划分合理的AVS高清视频解码器软硬件分区结构。根据AVS算法的特点该结构将宏块层以上部分的元素解析划归到软件解码中,将宏块层解码划为硬件处理。经验证,该结构设计可实现AVS高清码流解码,并在C语言编写的硬件平台仿真程序中得以实现。