Scalable general high voltage MOSFET model including quasi-saturation and self-heating effects

In this work, we present for the first time, a highly scalable general high voltage MOSFET model, which can be used for any high voltage MOSFET with extended drift region. This model includes physical effects like the quasi-saturation, impact-ionization and self-heating, and a new general model for drift resistance. The model is validated on the measured characteristics of two widely used high voltage devices in the industry i.e. LDMOS and VDMOS devices, and implemented on commercial circuit simulators like SABER (Synopsys), ELDO (Mentor Graphics), Spectre (Cadence) and UltraSim (Cadence). The accuracy of the model is better than 10% for DC I–V and g–V characteristics and shows good behavior for all capacitances which are unique for these devices showing peaks and shift of peaks with bias variation. The model also exhibits excellent scalability with transistor width, drift length, number of fingers and temperature.     

On gate leakage current partition for MOSFET compact model

Aggressive scaling of the gate-oxide thickness has made gate-tunneling current an essential aspect of MOSFET modeling and this leakage current density continues to increase for every process generation. Accurate compact models for gate-tunneling current and its source/drain partition are extremely critical to valid circuit performance in the 90 nm technology or beyond. Gate current partition has been studied by several authors [Cao K, et al. “BSIM4 gate leakage model including source–drain partition,” in IEDM Tech. Dig., San Francisco, CA, Dec. 2000. p. 815–8; R. van Langevelde et al., Gate current: modeling, ΔL extraction and impact on RF performance, in IEDM Tech. Dig., Washington, DC, Dec. 2001. p. 289–92; Shih W-K, et al., “A general partition scheme for gate leakage current suitable for MOSFET compact models,” in IEDM Tech. Dig., Washington DC., Dec. 2001. p. 293–6]. In this paper, an insight on the common/difference of these different gate leakage current partition schemes into source/drain has been provided and the accuracy of BSIM4 [Cao K, et al. “BSIM4 gate leakage model including source–drain partition,” in IEDM Tech. Dig., San Francisco, CA, Dec. 2000. p. 815–8] partition scheme is confirmed with comparing to the new derived equation, which incorporates the gate current into the inhomogeneous term calculation.     

Thermal model for dc characteristics of algan/gan hemts including self-heating effect and non-linear polarization

A thermal model based on the polynomial relationship of n_s and E_F is presented. The effect of temperature rise due to self-heating is studied on various parameters viz. polarization, electron mobility, velocity saturation, low-field mobility and thermal conductivity of substrate. Parasitic resistances and channel length modulation were also taken into consideration. The relationship between self-heating effect and device parameters was studied. The model is based on closed-form expressions and does not require elaborate computation. After including self-heating effect in calculations of current–voltage characteristics, our results agreed well with published experimental data.     

An analytical effective channel-length modulation model for velocity overshoot in submicron MOSFETs based on energy-balance formulation

A compact analytical model for MOSFET channel-length modulation (CLM) based on momentum and energy-conservation of Boltzmann transport equation as well as quasi-2D formulation is presented. It is consistent with the generalized drift–diffusion formulation including the nonlocal electron temperature, which can be interpreted as being an effective CLM or effective velocity overshoot. The model has a simple familiar form of the “pinch-off” model, with one fitting parameter for the length- and bias-dependent effective saturation field and effective Early voltage. The model can be easily characterized with one measured I_ds–V_ds data and has been verified with submicron technology data for the full range of gate lengths and bias conditions.     

A novel trench gate floating islands power MOSFET (TG-FLIMOSFET): Two-dimensional simulation study

Novel trench gate floating islands MOSFET (TG-FLIMOSFET) designed using the concept of “Opposite Doped Buried Regions” (ODBR) and floating islands (FLI) along with trench gate technology is proposed and verified using two-dimensional simulations. The conventional FLIMOSFET experimentally demonstrated recently, although offers lowest on-resistance in the low voltage range, however, suffers from quasi-saturation effect like any other power MOSFETs. The proposed TG-FLIMOSFET demonstrated to obtain about 30% reduction in peak electric field in drift region of the proposed device. TG-FLIMOSFET also demonstrates quasi-saturation free forward and transconductance characteristics, improved synchronous rectifying characteristics, identical breakdown voltage, reduced on-resistance and increased transconductance ‘gm’ when compared with the conventional FLIMOSFET for various trench geometries. The proposed device breaks the limit set by the conventional FLIMOSFET approximately by a factor of 10. A possible process flow sequence to fabricate the proposed device commercially by integrating multi-epitaxial process with trench gate technology is also presented.     

PDP驱动芯片中高压LDMOS建模

建立了PDP驱动芯片用高压LDMOS的SPICE子电路模型,该模型集成了LDMOS固有特性：准饱和特性、电压控漂移区电阻、自热效应、密勒电容等. 与其他物理模型和子电路模型比较,该模型不但能提供准确的模拟结果,而且建模简单快捷,另外该模型可较容易地嵌入SPICE模拟软件中. 模型的实际应用结果显示：模拟与实测结果误差在5%以内.     

ESD robustness prediction and protection device design in partially depleted SOI technology

In this paper we investigate and develop models for partially-depleted silicon-on-insulator (SOI) (PD–SOI) device failure under EOS/ESD stress. The model and experimental data show that due to increased device self-heating, the second-breakdown current per micron width (I_t2) for salicided PD-SOI metal-oxide semiconductor field effect transistor (MOSFET)s with Si film thickness of 100 nm is about 50% of that in their bulk counterparts under human body model (HBM–ESD) stress pulses. Furthermore, I_t2 did not scale with device width. Therefore, ESD protection devices with non-silicided S/D diffusions and source-body tied MOSFETs are investigated for improved ESD protection levels. Compact ESD protection networks using the source-body tied device may have been shown to achieve HBM–ESD protection levels of ±3.75 kV (Smith JC, Lien M, Veeraghaven S. An ESD protection circuit for TFSOI technology. International SOI Conf. Proc. 1996. pp. 170–71).     

B-Spline Based, Large-Signal DC and Microwave-Model for SOI MOSFETs

We present a large/small-signal, non-quasi-static, charge conserving, SOI MOSFET modeling technique suitable for DC and high frequency circuit design. The device model is extracted from small signal microwave iso-thermal Y-parameter data and DC I–V characteristics. Low frequency dispersions associated with self-heating and floating body effects are verified to not limit the performance of this technique since it relies on both DC and transient I–V characteristics. The technique is applied to the modeling of a short-channel, partially depleted, SOI nMOSFET simulated on PISCES. The model generated is incorporated into a circuit simulator, which is used to perform large-signal transient and harmonic balance simulations. The transient I–V and gate charge extracted from the iso-thermal small-signal microwave Y-parameters, are in excellent agreement with the iso-thermal transient I–V and gate charge obtained from PISCES, respectively. The model topology is extended with a parasitic bipolar sub-circuit which automatically calculates the DC operating point for self-biasing circuits. Transient and non-linear power characterization results predicted with this model agree well with those obtained from PISCES for a wide range of input power drives. A complete electro-thermal model is proposed and verified to be able to predict temperature and transient I–V response.     

A physically based compact device model for fully depleted andnearly fully depleted SOI MOSFET

A compact submicrometer Fully Depleted Silicon-On-Insulator (FDSOI) and Nearly FDSOI MOSFET device model suitable for analog as well as digital application has been proposed. It is an all region model. In developing this model care has been taken in retaining the basic functional form of physical models while improving the model accuracy and computational efficiency. In addition to the commonly included effects in the FDSOI MOSFET model, we have given careful consideration to parasitic source/drain resistance, Drain Induced Conductivity Enhancement (DICE) effect, floating body effect, self-heating and model continuity. A single parameter set is used for a large set of device dimensions except threshold voltage and parasitic source/drain resistance due to silicon film thickness variations. The accuracy of the model is validated with experimental data using NMOS FDSOI devices and found to be in good agreement     

Linear dynamic self-heating in SOI MOSFETs

A model for small-signal dynamic self-heating is derived for the general case of a two-port device and then specialized to the case of an SOI MOSFET. The model is fitted to measured data for an SOI MOSFET and shown to accurately describe the frequency dependence of the self-heating. For this device, three time constants of 0.25 μs, 17 ns, and 90 ps adequately characterize the thermal response, showing that self-heating effects are active over a very wide frequency range     

An accurate and compact large signal model for III–V HBT devices

An accurate and compact large signal model is proposed for modeling heterojunction bipolar transistors (HBTs) based on III–V materials. In DC mode, the model includes self-heating, Kirk and Early effects, as well as the temperature dependence of the model parameters. In small signal mode, the model captures the variation of various AC parameters with bias. The procedure of extracting the model parameters uses DC and multiple bias S-parameter measurements. The model is compiled in the HP–ADS circuit simulator as user-compiled model and is verified by comparing its simulations to measurements in all modes of operation for an AlGaAs/GaAs transistor with an emitter area of 2 × 25 μm².     

A large-signal SOI MOSFET model including dynamic self-heatingbased on small-signal model parameters

A new technique for a large-signal SOI MOSFET model with self-heating is proposed, based on thermal and electrical parameters extracted by fitting a small-signal model to measured s-parameters. A thermal derivative approach is developed to calculate the thermal resistance when the isothermal dc drain conductance is extracted from small-signal fitting. The thermal resistance is used to convert the measured dc current-voltage (I-V) characteristics containing the self-heating effects to the isothermal I-V characteristics needed for the large-signal model. Large-signal pulse and sinusoidal input signals are used to verify the model by measurement, and shown to reproduce the observed large-signal behavior of the devices with great accuracy, especially when two or more thermal time constants are used     

Large-signal modeling and characterization of high-current effectsin InGaP/GaAs HBTs

High-current effects in InGaP/GaAs heterojunction bipolar transistors (HBTs) were modeled and characterized. In addition to the self-heating effect, high currents were found to degrade large-signal performance mainly through Kirk and quasi-saturation effects. New formalisms in terms of base transit time and base-collector diffusion capacitance were used to modify the conventional Gummel-Poon model. This new model was verified against large-signal characteristics measured at 2 GHz. The validity of the new model for HBTs of different emitter geometry was also explored     

Discrete random dopant distribution effects in nanometer-scale MOSFETs

In this paper, discrete random dopant distribution effects in nanometer-scale MOSFETs were studied using three-dimensional, drift-diffusion “atomistic” simulations. Effects due to the random fluctuation of the number of dopants in the MOSFET channel and the microscopic random distribution of dopant atoms in the MOSFET channel were investigated. Using a simplified model for the threshold voltage fluctuation due to dopant number fluctuation, we examine the standard deviations of the threshold voltage that can be expected for a highly integrated chip.     

LDMOS模型设计及参数提取

近年来,LDMOS由于其漏极、栅极和源极都在芯片表面,易于和低压器件集成,因而被广泛应用到功率集成电路和射频领域,一直以来,高压LDMOS的建模是一个十分复杂的问题。文章通过分析高压LDMOS的结构和物理特性,得到高压LDMOS的准饱和特性、自热效应和漂移区的压控电阻特性,这些特性类似JFET的特性,从而建立了高压LDMOS器件的MOS+JFET新的电路模型。通过设计一套1.0μm 40V LDMOS的模型版,在CMOS工艺线上流片提取参数,实验结果表明该模型的解析值和实测值符合良好,而且还体现了LDMOS器件的固有特性。因而该种新模型的建立可以很好地指导LDMOS器件的工程应用。     

An analytic I—V model for lightly doped drain (LDD) MOSFET devices

An analytic I-V model for lightly doped drain (LDD) MOSFET devices is presented. In this model, the n^-region is considered to be a modified buried-channel MOSFET device, and the channel region is considered to be an intrinsic enhancement-mode MOSFET device. Combining the models of these two regions, the drain current in the linear/saturation regions and the saturation voltage can be calculated directly from the terminal voltages. In addition, the parameters used in the channel region can be extracted by a series of least square fittings. According to comparisons between the experimental data measured from the test transistors and the theoretical calculations, the developed I-V model is shown to be valid for wide ranges of channel lengths.     

An extended Tanh law MOSFET model for high temperature circuitsimulation

The Tanh law MOSFET model proposed earlier by Shousha & Aboulwafa (see ibid., vol. 28, no. 2, p. 176-9, 1993) is extended to predict the temperature dependence of the drain current by including the temperature dependence of the threshold voltage and the mobility. The model requires fewer temperature dependent parameters compared to SPICE level2 model. The extended model shows good agreement between measurement and simulation of devices with different device geometries over wide temperature range (27-200°C)     

Compact distributed multi-finger MOSFET model for circuit-level ESD simulation

This work presents a model for multi-finger MOSFETs operating under ESD conditions. It is a distributed model that can reproduce the effect of layout geometry on trigger voltage, on-state resistance, and non-uniform turn-on of device fingers. A three-terminal transmission line pulsing technique enables model parameter extraction. Analysis of measurement data and TCAD simulation reveals that self-heating is not uniform across the device, and this affects the relation between on-state resistance and the number of fingers. With self-heating incorporated, the model correctly reproduces the device I–V curve up to high current levels.     

Reduction of self-heating effect using selective buried oxide (SELBOX) charge plasma based junctionless transistor

A junctionless transistor (JLT) having high doping concentration of the channel, suffers from the threshold voltage roll-off because of random dopant fluctuation (RDF) effect. RDF has been minimized by using charge plasma based JLT. Charge plasma is same as a workfunction engineering in which work function of the electrode is varied to create hole/electron plasma and induce doping in the intrinsic silicon. N-type doping is induced at the source and drain side due to difference of workfunction of silicon wafer. In this paper, charge plasma based junctionless MOSFET on selective buried oxide (SELBOX-CPJLT) is proposed. This approach is used to reduce the self-heating effect presented in SOI-based devices. The proposed device shows better thermal efficiency as compared to SELBOX-JLT. 2D-Atlas simulation revealed the electrostatics and analog performance of both the devices. The SELBOX-CPJLT exhibits better electrostatic performance as compared to SELBOX-JLT for the same channel length. The analog performance such as intrinsic gain, transconductance generation factor, output conductance and unity gain cut-off frequency are extracted from small signal ac analysis at 1 MHz and compared to SELBOX-JLT. The analysis of the thermal circuit model of SELBOX structure is also performed.     

A unified circuit model for bipolar transistors including quasi-saturation effects

This paper describes a compact model for bipolar transistors which includes quasi-saturation effects. The assumptions used in the formulation of this model are clearly stated and justified, and a step by step derivation of the model equations is presented. These equations model both de and charge storage effects. Parameter extraction techniques are qualitatively described and the compact model is evaluated using detailed physical simulations of a high voltage bipolar transistor. In addition, simulations employing this model are compared with measurements and are found to be in excellent agreement.