基于93000 ATE的高速高分辨率ADC动态参数测试

基于Verigy 93000 ATE,采用外挂高性能晶振和射频信号源的测试方案,实现了11位分辨率AD80141最高400 MHz输入信号的测试。结果表明,输入信号为140 MHz以下时,SNR测试值与目标值相差不到1 dB;输入信号为300 MHz、400 MHz时,SNR测试值分别达到59.46dB和57.03 dB。     

音频信号的数字处理及其应用设计

提出了2.4G无线影音传输系统中的数字音频传输方案,介绍了AES/EBU数字音频接口标准,并详细阐述了系统的关键技术,包括差错掩盖技术和天线切换技术。采用差错掩盖技术,可以消除“噼啪”声;而运用天线切换技术,提高了音频信号接收质量,有效地抑制干扰,提升了系统的性能。     

异地综合试验互联网络技术研究

文中以民用飞机电子系统的试验互联体系为例，介绍了一种试验互联网络设计技术。针对在大型复杂电子系统研发过程中，分布式试验设施之间测试信号传输需满足传输时延和品质保真的要求，采用基于光纤互联网络的多电信号适配技术，通过核心部件光纤交换机和信号中继转换装置构建了可级联扩展的试验互联网络体系。根据对原型系统的测试分析表明，在确保信号传输品质的情况下，在500 m传输范围内试验互联网络对典型信号的延时一般不超过60 μs     

OFDM技术在GSM语音信道中的应用

远距离数据传输以及数据传输的保密性向来是人们比较关注的问题,使用语音信道传输数据信息是一种可选的方案。利用GSM信道,结合OFDM技术,将电脑、手机、A/D、D/A组成一个系统,可以实现一种远距离数据传输平台。针对OFDM技术特点,实现了GSM语音信道OFDM调制解调系统,经过多次实验测试,平均误码率曲线表明设计达到了最初的设计要求,在话音保密数据通信及其他数据传输上有较好的应用前景。     

高速高精度流水线ADC的快速仿真方法研究

设计了一种可以与晶体管跨导运算放大器特性高度比拟的运放宏模型.用该宏模型替换采样/保持电路和MDAC模块中的晶体管级放大器电路,进行FFT分析;在仿真结果相差3.2%的情况下,仿真时间为原来的1.7%,大大缩短了流水线ADC的验证周期.在该方法的指导下,设计了一个10位20 MS/s 流水线A/D转换器.在2.3 MHz输入信号下测试,该A/D转换器的ENOB为8.7位,SFDR为73 dBc;当输入信号接近奈奎斯特频率时,ENOB为8.1位.     

基于ARM和FPGA的电力光纤信号分析仪的设计

为了能更好地实现变电站的自动化和数字化以及完成变电站系统的实时监控、测试,更快捷、直观地获得设备的运行状态。介绍了一台基于ARM＋FPGA的电力光纤信号分析仪的设计与研究,从硬件方面提出了新的设计方案。这种光纤信号分析仪主要实现对数字化变电站中通过100 M BaseFX传输的各种格式报文的抓取、信息提取、报文解码、实时存储及波形显示等功能。     

一种高精度多通道数据采集模块设计及实现

测试系统中的信号采集是系统的一个重要环节,在工业测控系统或实验室中,需要多通道的信号采集装置实现对模拟信号的采集。针对采集设备的通用性、小型化和高精度的要求,设计一种高精度多路数据采集模块,采用高精度A/D转换芯片,通过巡回采样的方法采集16路16位模拟量信号,实验表明,该方法特别适用于高精度工业现场数据采集。     

气象雷达综合数字终端技术

数字化综合传输终端是新型气象雷达系统中重要设备之一,它为气象雷达的测量和处理设备之间提供了一条高质量、高可靠的遥测、遥控、话音及图象数据的数字化综合传输通道,使气象雷连的整体性能获得了提高。通过测试和使用,证实数字化综合传输终端具有很多的优点,居国内领先水平。     

基于机顶盒语音信号分析的收视率调查仪设计

针对目前市场上机顶金调查仪设计复杂、成本高、价格昂贵,提出了基于DSP的收视率调查仪设计,通过将电视语音信号与多媒体高频头所得到的伴音信号进行A/D采样、FIR滤波、FFT运算和频谱比较,将最终运算结果发送到上一级的子处理系统进行数据统计,得出各栏目的收视率.该设计与传统机顶金调查仪相比,具有设备简单、成本低、实时性好和准确性高等特点.     

基于PLC的通信车配电机柜设计

本文根据通信车中各用电设备的用电特点,设计了以PLC为控制核心、以触摸屏为人机交互界面的配电机柜.通过传感器,实现电压、电流信号的采集.通过A/D转换模块,将传感器输出的模拟信号转换为PLC能识别的数字信号.通过触摸屏,实现各信号的实时显示及各用电设备的开关控制.     

Computer-aided design of analog and mixed-signal integratedcircuits

This survey presents an overview of recent advances in the state of the art for computer-aided design (CAD) tools for analog and mixed-signal integrated circuits (ICs). Analog blocks typically constitute only a small fraction of the components on mixed-signal ICs and emerging systems-on-a-chip (SoC) designs. But due to the increasing levels of integration available in silicon technology and the growing requirement for digital systems to communicate with the continuous-valued external world, there is a growing need for CAD tools that increase the design productivity and improve the quality of analog integrated circuits. This paper describes the motivation and evolution of these tools and outlines progress on the various design problems involved: simulation and modeling, symbolic analysis, synthesis and optimization, layout generation, yield analysis and design centering, and test. This paper summarizes the problems for which viable solutions are emerging and those which are still unsolved     

A novel simulation technique for testing analog ICs

The increasing demand for reliable and high quality mixed-signal integrated circuits necessitates a defect-oriented testing methodology. Thereby fault simulation (FS) is essential for test stimuli generation and test quality assessment. Due to the high computational effort needed, analog FS is becoming a critical factor in testing mixed-signal ICs. This paper provides a new accelerated FS approach. It is based on an improved application of the Newton–Raphson method in the analysis of similarly behaving circuits. Metrics for measuring circuits' behavior similarity are presented. The new techniques are implemented in an experimental FS tool. For sample circuits, experimental results are presented and discussed.     

BiCMOS emerges for gate-arrays and memories

The integration of CMOS and bipolar technologies for applications involving gate-arrays, memories, and mixed-signal tasks is described. The specific features of bipolar and CMOS devices are reviewed, and the ways in which the best of these characteristics can be combined in BiCMOS ICs are discussed. Future trends in the applications of BiCMOS technology are discussed     

Production Realization of MTPR Test on Low-Cost ATE for OFDM Based Communication Devices

Multi-tone power ratio (MTPR) test is fast replacing multiple single-carrier linearity and non-linearity tests for mixed-signal IC’s employed in broadband communication. Competitive cost models rule out the use of expensive automated test equipment that can perform MTPR test in a specification compliant manner. In this paper, deployment of a multi-tone dither based approach to perform MTPR tests on lower cost test platforms is presented. The proposed method uses existing resources of a low-cost ATE to improve the linearity performance of other resources required during the MTPR test. An ‘on-the-fly’ dither generation algorithm is developed to derive a robust dither signal accounting for variations typically encountered in production testing. Results obtained from multiple test benches including ADSL mixed-signal CODEC ICs on TI’s internal low-cost platform is presented to validate the proposed test method. Finally, statistical test data obtained from conducted experiments is presented to evaluate the repeatability of the proposed approach.     

一种混合信号边界扫描测试系统的设计

IEEE 1149.4的推出为混合信号测试提供了一个标准,推动了混合信号边界扫描测试技术的研究。简要介绍了IEEE 1149.4标准及混合信号测试方法,并根据标准定义的测试结构设计出一种混合信号边界扫描测试系统。经过测试验证,该系统能够对混合信号电路进行互连测试和参数测试,可实现准确的故障诊断,具有一定的实用价值。     

Transistor and circuit design for 100-200-GHz ICs

Compared to SiGe, InP HBTs offer superior electron transport properties but inferior scaling and parasitic reduction. Figures of merit for mixed-signal ICs are developed and HBT scaling laws introduced. Device and circuit results are summarized, including a simultaneous 450 GHz f/sub /spl tau// and 490 GHz f/sub max/ DHBT, 172-GHz amplifiers with 8.3-dBm output power and 4.5-dB associated power gain, and 150-GHz static frequency dividers (a digital circuit figure-of-merit for a device technology). To compete with advanced 100-nm SiGe processes, InP HBTs must be similarly scaled and high process yields are imperative. Described are several process modules in development: these include an emitter-base dielectric sidewall spacer for increased yield, a collector pedestal implant for reduced extrinsic C/sub cb/, and emitter junction regrowth for reduced base and emitter resistances.     

Analogue and mixed-signal IC design

Recent developments in fabrication technology have led to the advent of double-poly CMOS processes, which are attractive for analogue ICs. The process allows high-value capacitors to be made using the two polysilicon layers as the conducting plates, thus using a much smaller area than that required by earlier metal-poly capacitors. The BiCMOS process is particularly relevant to making mixed analogue/digital devices; it blends N- and P-channel complementary MOS devices with NPN bipolar devices in the same process, giving the ability to produce CMOS and bipolar transistors on a single chip. This means that high-performance analogue circuits can be mixed with high-density, low-power digital circuits, offering a single-package mixed-signal system. The authors highlight the rapid growth in the mixed-signal ASIC market. They examine the crucial developments taking place in analogue CAD environments, and in the device technologies on which the growth critically depends     

CMOS／SOSCC4066器件的可靠性研究

本文介绍了CMOS/SOS CC4066器件长期可靠性试验结果。对失效器件的分析表明,硅-蓝宝石技术没有新的失效机理。该器件的可靠性不低于国内体硅MOS IC能达到的水平,并接近“七专”器件的水平。     

基于高性能数字芯片的多协议可编程接口设计

设计并制作了一种基于SMIC18混合信号工艺,可用于高性能数字芯片中的多协议、可编程输入接口电路.Cadence SPECTRE仿真及测试结果表明,电路可以在多种不同的JEDEC标准协议下工作并自由切换,并加入可控延迟,根据不同协议,电路可以编程选择不同的输入缓冲路径,在同一模块上集成10种JEDEC协议标准.电路同时可以在高至200 MHz的HSTL协议下工作,也可以满足LVTTL等协议的5 V耐压需求.     

10GHz 2分频器芯片设计

目前,10 Gb/s以上的数字光纤通信技术正在逐步得到应用,研究和开发光纤通信用的高速集成电路具有重要的意义。文章介绍了使用0.2μm GaAs HEMT工艺设计的1个10 Gb/s以上的光纤传输用2分频器。该分频器采用双锁存器串联结构,仿真结果和流片测试结果均表明该电路在10Gb/s的速率上可以完成2分频功能。