嵌入式处理器的TLB电路设计

为了提高基于虚拟存储技术的嵌入式处理器的性能,本文提出了一种用于高效加速地址转换的TLB电路结构。该电路采用64-entries的全关联结构,硬件支持基于段及不同大小页的转换方式。通过VCS和Nanosim联合仿真对电路结构和性能进行了验证,仿真结果表明,系统中加入TLB电路以后性能有显著的提高。     

基于ARM7TDMI的TLB组织结构及存储保护设计

基于ARM7TMDI嵌入式处理器内核设计了一种兼容ARM720T存储管理机制的转换后备缓冲器(TLB)组织结构,建立了TLB的Verilog仿真模型,设计了相对应的存储保护模块.该TLB采用64页表项全关联结构,同时支持多种页转换方式和页表项命中控制,并且通过复用设计节省了硬件资源.通过整合TLB、存储保护模块和ARM7TMDI的仿真模型,采用VCS仿真软件进行仿真验证,结果证实了设计的有效性和正确性.     

一种并行指令Cache的设计与实现

为提高通用微处理器的执行效率,研究了高性能指令Cache的体系结构和设计方法。设计了高速并行指令Cache的系统架构,将Cache体访问与线形地址到物理地址的地址转换并行操作,成功实现一个时钟周期内完成地址转换和指令读出的设计目标。详细设计了Cache体和TLB的逻辑结构,并对相关设计参数进行了精心规划,并在设计中采用了奇偶校验逻辑增加了芯片的可靠性。此结构应用于JX微处理器流片成功,并工作可靠正确。     

数字CNN微处理器的指令集设计

指令集的设计直接影响到数字CNN微处理器的通用性、灵活性以及可编程性,因此是其设计中的关键内容之一.在充分研究数字CNN微处理器的实现方式及其实现原理的基础上,提出其指令集的设计方法,该方法具有一定的通用性,设计的指令简单实用.利用该方法设计的指令对图像进行处理具有良好的性能和效果.     

基于内存数据库的索引算法研究

随着内存价格的不断走低,数据库中的数据在内存中运行已经具有了一定的可行性。内存数据库有着比磁盘数据库无法比拟的优势,那就是在实时和高并发的应用上所展现的能力。因此基于磁盘的索引算法已经不能适应内存数据库的要求,有必要探索出一种新的索引算法。文中从当今研究比较热门的敏感索引树出发,分析了CSB+索引树的优缺点及适用情形,设计出了一种改进CSB+树的查询算法,得出改进后的CSB+树对TLB失配具有显著的改善效果,提高了内存数据库的性能。     

X微处理器FPGA仿真的研究与实现

X微处理器是一款具有完全自主知识产权的通用64位高性能微处理器,规模大、复杂度高.结合X微处理器的FPGA仿真,探讨了FPGA仿真验证的技术难点:FPGA的划分、FPGA芯片引脚复用、多片FPGA芯片互连信号传输的完整性问题.提出了基于系统功能和流水线结构的FPGA划分方法与虚拟I/O技术,设计了可重配置的通用FPGA仿真板,解决了用多片FPGA芯片实现X微处理器仿真的难题.     

高性能16位徽处理器IP软核设计

在对标准Intel 8086微处理器进行分析的基础上,本文介绍了一种与其指令集兼容、性能大幅提高的可重用16位微处理器IP软核的设计.从处理器体系结构的划分,到指令集的设计以及处理器内部各单元的设计,进行了比较详尽的阐述,并对该设计进行了软件仿真和硬件验证.该处理器采用缩短指令执行时钟周期、增加指令预取队列、改进总线接口时序和减少有效地址计算时间等系统架构的优化,使性能得到大幅度的提高;通过扩展指令集实现与标准8086、8088、80186和80188系列微处理器完全软件兼容.     

HPPA7100可伸缩性Cache组织及有关技术

本文介绍并分析了ＨＰＰＡ７１００微处理器的不在片的可伸缩性ｃａｃｈｅ组织结构的特点与用于改进ｃａｃｈｅ性能的有关设计技术。     

CMOS异或电路的设计与应用

设计了四种CMOS"异或"单元电路,通过模拟仿真分析了它们各自的性能特点,并讨论了它们在奇偶检测电路、微处理器系统加法器电路以及单片机全加电路等设计中的不同应用.     

一种适用于通用CPU的高命中率、低功耗TLB

为了提高 CPU的速度和更有效的管理物理内存 ,一般都采用转换查找缓冲器 (TLB)将虚拟地址转换为物理地址。文中介绍一种适用于 3 2位通用 CPU的 TLB结构。这种 TLB采用组相联映射、两种页粒度结构 ,采用静态存储结构作为其基本存储单元 ,同时应用了静态存储单元的低功耗设计来降低 TLB的功耗。     

Analog Circuit Design Methodology in a Low Power RISC Microprocessor

There are various kinds of analog CMOS circuits in microprocessors. IOs, clock distribution circuits including PLL, memories are the main analog circuits. The circuit techniques to achieve low power dissipation combined with high performance in newest prototype chip in the Super H RISC engines are described. A TLB delay can be decreased by using a CAM with a differential amplifier to generate the match signal. The accelerator circuit also helps to speed up the TLB circuit, enabling single-cycle operation. A fabricated 96-mm² test chip with the super H architecture using 0.35-m four metal CMOS technology is capable of 167-MHz operation at 300 Dhrystone MIPS with 2.0-W power dissipation.     

A Low-Power dTLB Design Based on Memory Region Encoding

Translation lookaside buffers （TLBs） consume significant power due to their highly associative structure. This is getting worse with the increasing width of Virtual page number （VPN） and TLB capacity in 64- bit computing. In this paper, we present a new data TLB （dTLB） design that reduces VPN width to a large extent, thereby saving considerable power during TLB lookups. This design is motivated by an observation： the VPN can represent a much larger set of memory regions than what can be cached by the TLB at any time. We exploit this redundancy by encoding some high-order VPN bits with a shorter memory region id before the VPN is sent to dTLB. The consistency of the encoding and the recycling of memory region ids are taken cared by a small amount of hard- ware with little timing/power overhead. Experimental results on SPEC CPU2000 show a 37% energy reduction of dTLB with negligible performance penalty.     

A 1.71-million transistor CMOS CPU chip with a testable cachearchitecture

A 1.71-million transistor CISC CPU chip for the business computer has been developed. The chip is implemented in a 0.8-μm CMOS double-polysilicon double-metal technology. The 16.3-mm×12.7-mm device contains a 16-kilobyte cache and 192 entries TLB and operates at 40 MHz. The sustained high performance in a complexed instruction set has been realized by a large horizontal microprogram that controls two 32-b ALU's. The cache and TLB employ a 77-μm² SRAM using load resistors formed by the second polysilicon; these are accessed in one-half clock cycle and are tested at an 8 bytes per clock rate utilizing a new test strategy     

Two New Techniques Integrated for Energy-Efficient TLB Design

The translation lookaside buffer (TLB) is an essential component used to speed up the virtual-to-physical address translation. Due to frequent lookup, however, the power consumption of the TLB is usually considerable. This paper presents an energy-efficient TLB design for the embedded processors. In our design, we first propose a real-time filter scheme to facilitate the block buffering to eliminate the redundant TLB accesses without comparator delay. By modifying the address registers to be sensitive to the contents variation, the proposed real-time filter can distinguish the redundant TLB access as soon as the virtual address is generated. The second technique is a banking-like design, which aims to reduce the energy consumption per TLB access in case of block buffer miss. To alleviate the performance penalty introduced by the conventional banking technique, we develop two adaptive variants of the banked TLB. Both variants can achieve the high energy efficiency as the banked TLB while maintaining the low miss ratio as the nonbanked TLB. The experimental results show that by filtering out all the redundant TLB accesses and then minimizing the energy consumption per access, without any performance penalty our design can effectively improve the Energy^* Delay product of the TLB, especially for the data TLB with poor locality     

Dual TLB structure for supporting two page sizes

A new translation lookaside buffer (TLB) structure is proposed which supports dual page sizes so as to obtain the effect of multiple page sizes with high performance and at low cost without operating system support. According to the results of a comparison and analysis, a similar performance can be achieved by using fewer TLB entries compared with conventional TLBs     

0.5-μm 3.3-V BiCMOS standard cells with 32-kilobyte cache andten-port register file

BiCMOS standard cell macros, including a 0.5-W 3-ns register file, a 0.6-W 5-ns 32-kbyte cache, a 0.2-W 3-ns table look-aside buffer (TLB), and a 0.1-W 3-ns adder, are designed with a 0.5-μm BiCMOS technology. A supply voltage of 3.3 V is used to achieve low power consumption. Several BiCMOS/CMOS circuits, such as a self-aligned threshold inverter (SATI) sense amplifier and an ECL HIT logic are used to realize high-speed operation at the low supply voltage. The performance of the BiCMOS macros is verified using a fabricated test chip