12GHz单片组合低噪声GaAs MESFET放大器

本文叙述了12GHz单片组合的低噪声GaAs MESFET放大器的设计和制造.每级单片放大器包含一个有源元件FET、一个隔直电容和两个射频旁路电容.在11.7～12.2GHz范围内,单级放大器增益6.0dB,噪声系数3～3.5dB,三级放大器增益16～18dB,噪声系数≤4.0dB.     

一种噪声系数为1.4 dB的S波段MMIC低噪声放大器

报道了一种可直接应用于无线接收系统前端的具有较低噪声系数和较高相关增益的MMIC低噪声放大器,该低噪声放大器采用0.50 μm GaAs PHEMT工艺技术制作.电路设计采用两级级联结构,为减小电路面积采用集总参数元件匹配电路,并用ADS软件仿真无源元件寄生效应.电路测试结果表明:在2.8～3.5 GHz 频段内噪声系数低于1.4 dB,同时相关增益大于25 dB,增益平坦度小于0.5 dB,输入输出反射损耗小于-10 dB.     

宽频带低噪声放大器设计

采用Lange耦合器的宽频带特性设计L／S波段平衡式低噪声放大器电路,并通过仿真设计软件对放大器的工作频带、噪声系数、增益及输入、输出驻波比等几个重要指标进行优化。最后设计的放大器在1．2～2．5GHz频率范围内增益为33～35dB,噪声系数不大于1dB,输入输出驻波比小于1．5,达到了预定的技术指标要求,性能良好。     

一种用于DVB-C射频调谐器宽带低噪声放大器的设计

设计了一种用于DVB-C射频调谐器的宽带低噪声放大器.低噪声放大器采用了负反馈拓扑结构,用于改善增益平坦度,使用Agilent公司的ADS软件对电路进行了优化设计,测试结果表明,在50～860 MHz有线数字电视全波段内获得了10.7 dB的增益,增益平坦度小于1.2 dB,噪声系数小于3.5 dB,输入电压驻波比小于2,输出电压驻波比小于2.5.     

S波段低噪声放大器设计

首先分析了低噪声放大电路的稳定性,功率增益及噪声系数的影响因素及改进方法;然后设计了一个中心频率为2.45 GHz,工作带宽为100MHz的S波段低噪声放大器.仿真结果表明,该放大器的噪声系数小于1 dB,功率增益大于28 dB,增益平坦度小于1 dB,输入/输出驻波比小于2:1.通过传统的电路板制作工艺实际制作了放大器电路,测试结果和仿真结果较一致.     

一种用于电视调谐器的宽带CMOS低噪声放大器设计

介绍了一种宽带CMOS低噪声放大器设计方法,采用噪声抵消技术消除输入MOS管的噪声贡献.芯片采用TSMC 0.25μm 1P5M RF CMOS工艺实现.测试结果表明:在50～860MHz工作频率内,电压增益约为13.4dB;噪声系数在2.4～3.5dB之间;增益1dB压缩点为-6.7dBm;输入参考三阶交调点为3.3dBm.在2.5V直流电压下测得的功耗约为30mW.     

一种用于电视调谐器的宽带CMOS低噪声放大器设计

介绍了一种宽带CMOS低噪声放大器设计方法,采用噪声抵消技术消除输入MOS管的噪声贡献.芯片采用TSMC 0.25μm 1P5M RF CMOS工艺实现.测试结果表明:在50～860MHz工作频率内,电压增益约为13.4dB;噪声系数在2.4～3.5dB之间;增益1dB压缩点为-6.7dBm;输入参考三阶交调点为3.3dBm.在2.5V直流电压下测得的功耗约为30mW.     

一种S波段平衡式限幅低噪声放大器的设计

介绍了一种小型化平衡式限幅低噪声放大器。该放大器采用Lange桥平衡结构,在实现低噪声的同时,保证了小电压驻波比;在3.0～3.5GHz频带内,噪声系数小于1.3dB,输入输出驻波系数小于1.3,增益大于27dB,平坦度±0.6dB以内,输出1dB压缩点大于12dBm。该放大器能够承受最大5W的连续波功率输入,且大功率输入时的驻波系数小于1.3。     

宽带CMOS低噪声放大器的设计

文章主要介绍应用于集群接收机系统的350MHz～470MHz低噪声放大器,采用0.6μm CMOS工艺。探讨了优化低噪声放大器的噪声系数、增益与线性度的设计方法,同时对宽带输入输出匹配进行了分析。这种宽带低噪声放大器的工作带宽350MHz～470MHz,噪声系数小于3dB,增益为24dB,增益平坦度为±1dB,输入1dB压缩点大于-15dBm。     

便携式UHF RFID阅读器中发射前端电路设计

采用0.18μm CMOS工艺设计并制作了一款应用于便携式UHFRFID阅读器的射频发射前端电路。所设计的有源I/Q上混频器通过开关控制Q支路的信号输入,实现了EPC Global Class-1Gen-2协议中所要求3种调制方式;驱动放大器通过实现增益7级数字可调有效地预放大混频器的输出信号。在1.8V的电源电压下,测得阅读器前端电路的主要性能参数如下:上混频器的输入端P1dB,达到-14.9dBVrms,转换增益和噪声系数分别为3.18dB和13.20dB;驱动放大器的输出端P1dB在50Ω阻抗上达到3.5dBm,转换增益可调范围和噪声系数变化范围,分别为7.90～16.30dB和3.10～5.00dB。     

用于IEEE802．11b／g WLAN直接下变频接收机的射频前端设计

介绍了一种应用于IEEE802．11b／g无线局域网接收机射频前端的设计。基于直接下变频的系统架构。接收机集成了低噪声放大器、I／Q下变频器、去直流偏移滤波器、基带放大器和信道选择滤波器。电路采用TSMC0．18μm CMOS工艺设计,工作在2．4GHz ISM（工业、科学和医疗）频段,实现的低噪声放大器噪声系数为0．84dB,增益为16dB,S11低于-15dB,功耗为13mW;I／Q下变频器电压增益为2dB,输入1dB压缩点为-1 dBm,噪声系数为13dB,功耗低于10mw。整个接收机射频前端仿真得到的噪声系数为3．5dB,IIP3为-8dBm,IP2大于30dBm,电压增益为31dB,功耗为32mW。     

Performance of GaAs MESFET's at Low Temperatures (Short Papers)

The noise- and s-parameters of a GaAs MESFET with 1-mu m gate Iength are characterized versus temperature. At room temperature, the noise figure measured at 12 GHz is 3.5 dB. At 90 K, the noise figure decreases to 0.8 dB (T/sub e/ = 60 K). The associated gain is 8 dB. The design of a cooled amplifier for the 11.7-12.2-GHz communication band is discussed. At 60 K, the three-stage amplifier exhibits 1.6-dB noise figure (T/sub e/ = 130 K) and 31-dB gain.     

S波段雷达接收机前端低噪声放大器

采用0.35μm SiGe BiCMOS工艺设计了用于S波段雷达接收机前端电路的低噪声放大器。对于现代无线接收机来说,其动态范围和灵敏度很大程度上都取决于低噪声放大器的噪声性能和线性度。相对于CMOS工艺来说,SiGe BiCMOS工艺具有更高的截止频率、更好的噪声性能和更高的电流增益,非常适合微波集成电路的设计。该低噪声放大器采用三级放大器级联的结构以满足高达30dB的增益要求。在5V的电源电压下,满足绝对稳定条件,在3GHz-3.5GHz频段内,功率增益为34.5dB,噪声系数为1.5dB,输出1dB功率压缩点为11dBm。     

A 2-18 GHz low-noise/high-gain amplifier module

The effectiveness of the two-tier matrix amplifier as a very-low-noise device with very high associated gains across multioctave frequency bands is theoretically and experimentally demonstrated. Experimental modules whose topology is based on a computer-optimized design exhibit an average noise figure of F=3.5 dB with an associated average gain of G=17.8 dB across the 2-18 GHz frequency band. These state-of-the-art results were achieved with GaAs MESFETs whose minimum noise figure is F=2.2 dB at 18 GHz and whose gate dimensions are 0.25×200 μm. The design considerations and the test results are discussed in detail     

All-optical gain-clamped erbium-doped fiber-ring lasing amplifierwith laser filtering technique

A unique laser filtering technique of a gain-clamped erbium-doped fiber amplifier based on ring-laser cavity is demonstrated. The filtering mechanism is achieved using a single fiber Bragg-grating, which also functions as a laser feedback reflector at the output end of the amplifier. This new design has low noise and most important, shows up to 98% reduction in output laser intensity as compared with a previous design studied earlier. An optimum result with gain and noise around 25 and 3.5 dB, respectively, obtained for a dynamic range of input signal power up to -8 dBm     

A 2.4/3.5/4.9/5.2/5.7-GHz concurrent multiband low noise amplifier using InGaP/GaAs HBT technology

A 2.4/3.5/4.9/5.2/5.7-GHz concurrent multiband low noise amplifier using InGaP/GaAs HBT technology is demonstrated for the first time. Multiband input matching is achieved by newly developed capacitive feedback instead of traditional inductive feedback technique. The experimental results showed that input return loss of -12, -16, -14, -13, and -12 dB, voltage gain of 29, 27, 24, 23.6, and 22.5 dB and noise figure of 2.89, 2.76, 2.95, 2.98, and 3.1 dB were obtained at 2.4/3.5/4.9/5.2/5.7 GHz, respectively.     

A W-band image-rejection downconverter

The design, fabrication, and evaluation of a W-band image-rejection downconverter based on pseudomorphic InGaAs-GaAs HEMT technology are presented. The image-rejection downconverter consists of a monolithic three-stage low-noise amplifier, a monolithic image-rejection mixer, and a hybrid IF 90° coupler with an IF amplifier. The three-stage amplifier has a measured noise figure of 3.5 dB, with an associated small signal gain of 21 dB at 94 GHz while the image-rejection mixer has a measured conversion loss of 11 dB with +10 dBm LO drive at 94.15 GHz. Measured results of the complete image-rejection downconverter including the hybrid IF 90° coupler and a 10 dB gain amplifier show a conversion gain of more than 18 dB and a noise figure of 4.6 dB at 94.45 GHz     

DVB-C系统中射频宽带低噪声放大器电路的设计研究

本文根据DVB系统对LNA的特殊要求,阐述了负反馈展宽放大器频带的原理,讨论了通过设计并联负反馈的手段来实现LNA宽频带稳定性,并在此基础上,设计出一种宽带LNA的拓补结构,并采用将负反馈解析计算与仿真优化相结合的LNA设计方法,给出了LNA最终设计的仿真及实测结果.实验结果和设计结果吻合较好.该LNA带宽为50 MHz～900 MHz,功率增益10.4 dB,带内增益波动0.6 dB,带内噪声系数2.7 dB～3.5 dB.     

应用于S波段AESA的射频收发前端设计

采用0．18μm Si RFCMOS工艺设计了应用于s波段AESA的高集成度射频收发前端芯片。系统由发射与接收前端组成,包括低噪声放大器、混频器、可变增益放大器、驱动放大器和带隙基准电路。后仿真结果表明,在3．3V电源电压下,发射前端工作电流为85mA,输出ldB压缩点为5．0dBm,射频输出在2～3．5GHz频带内电压增益为6．3～9．2dB,噪声系数小于14．5dB;接收前端工作电流为50mA,输入1dB压缩点为-5．6dBm,射频输入在2～3．5GHz频带内电压增益为12—14．5dB,噪声系数小于11dB;所有端口电压驻波比均小于1．8：芯片面积1．8×2．6mm0。