Logic circuit design using monostable-bistable transition logic element based on standard BiCMOS process

We present a monostable-bistable transition logic element (MOBILE) based on the negative-differential-resistance (NDR) circuit. In particular, this circuit can be completely implemented using the standard BiCMOS process. A traditional MOBILE using two resonant tunneling diodes (RTD) connected in series is a functional logic circuit. The fabrication of RTD is utilized in the complicated molecular-beam-epitaxy (MBE) system. However, we present a MOBILE circuit that is completely made of standard Si-based metal-oxide-semiconductor field effect transistors and SiGe-based heterojunction bipolar transistors. By suitably determining the control voltages and input conditions, we can obtain the operation of the inverter, AND and OR logic gates. We also demonstrate the latch characteristic of this MOBILE circuit. This logic circuit is fabricated using the standard 0.35 μm BiCMOS process without the need for the MBE system.     

Functions and applications of monostable-bistable transition logicelements (MOBILE's) having multiple-input terminals

The MOBILE is a logic gate exploiting the monostable-bistable transition of a circuit that consists of two resonant tunneling transistors connected in series. It has several advantages including multiple inputs and multiple functions. This paper describes the output characteristics of multiple-input MOBILE's and discusses their applications. For a two-input MOBILE, it is demonstrated that both NAND and NOR operations are possible with the appropriate control voltage. This implies the possibility of a variable function logic gate. Furthermore, the threshold logic operations for a weighted sum of input signals are demonstrated for a three-input MOBILE with a weight ratio of 4:2:1. The applications of MOBILE's in parallel processing architectures such as cellular automata and cellular neural networks are discussed based on the above results. Circuit simulations using a simple model of resonant tunneling transistors successfully reproduce the basic characteristics of MOBILE's, and demonstrate the usefulness of MOBILE's in such applications     

Compact parallel (m,n) counters based on self-timed threshold logic

A new, highly compact implementation of general parallel counters (i.e. population counters) with logic depth 2, based on self-timed threshold logic, is presented. The novel feature of the design is the sharing among all threshold gates of a single capacitive network for computing the weighted sum of all input bits. The significance of the result is the reduction by almost 50% in the required number of capacitors. Interconnect routing cost is also reduced, resulting in significantly decreased total area     

InP-based high-performance monostable-bistable transition logicelements (MOBILEs) using integrated multiple-input resonant-tunnelingdevices

MOBILEs (monostable-bistable transition logic elements), which have the advantages of multiple-input and multiple-function, are demonstrated in InP-based material system using monolithic integration of resonant-tunneling diodes and high electron mobility transistors. The high peak current density, high peak-to-valley ratio, and high transconductance, which are required for high-performance MOBILEs, are demonstrated in this InP-based material system. A fabricated MOBILE with three-input gates having 1:2:4 width ratio can perform weighted-sum threshold logic operation, and has a wide range of applications in new computing architectures, such as neural networks     

Single phase clock scheme for mobile logic gates

Many logic circuit applications of resonant tunnelling diodes are based on the MOnostable-BIstable Logic Element (MOBILE). Cascaded MOBILE gates are operated in a pipelined fashion using a four phase overlapping clocking scheme. To improve the robustness of MOBILE networks, a simpler clock scheme is desirable. It is demonstrated that a network of MOBILE gates can be operated with a single clocked bias signal. Both schemes are compared     

Threshold logic

A threshold gate has binary inputs and outputs just like any other logic gate. The difference, however, is that in the threshold gate the inputs may be weighted and, eventually, a binary decision made as to whether the total weight is more or less than some reference. This principle of weighting and summing the inputs rather than simply noting the presence of all inputs as high (as in an AND gate) or one input high (as in an OR gate) is the reason that a threshold gate can tell more about the state of the inputs, thus providing greater ``logic power.' This article gives some examples of the applicability of threshold logic, as well as an integrated-circuit approach for building arrays of versatile threshold gates. In addition, some logic designs are described and compared with conventional ECL implementations.     

Novel pipeline architectures based on Negative Differential Resistance devices

Devices exhibiting Negative Differential Resistance (NDR) in their I–V characteristic are attractive from the design point of view and circuits exploiting it have been reported showing advantages in terms of performance and/or cost. In particular, logic circuits based on the monostable to bistable operating principle can be built from the operation of two series connected NDR devices with a clocked bias. Monostable to Bistable Logic Element (MOBILE) gates allow compact implementation of complex logic function like threshold gates and are very suitable for the implementation of latch-free fine grained pipelines. This pipelining relies on the self-latching feature of MOBILE operation. Conventionally, MOBILE gates are operated in a gate level pipelined fashion using a four-phase overlapped clock scheme. However other simpler, and higher through-output interconnection schemes are possible. This paper describes latch-free MOBILE pipeline architectures with a single clock and with a two phase clock scheme which strongly rely on distinctive characteristics of the MOBILE operating principle. Both the proposed architectures are analyzed and experimentally validated. The fabricated circuits use a well-known transistor NDR circuit (MOS-NDR) and an efficient MOBILE gate topology built on its basis. Both solutions are compared and their distinctive characteristics with respect to domino based solutions are pointed out.     

Monolithic integration of resonant tunneling diodes and FET's formonostable-bistable transition logic elements (MOBILE's)

A MOBILE (monostable-bistable transition logic element), employing two n-type negative differential resistance devices connected in series, is a functional logic gate with the advantages of multiple inputs and multiple functions. In this paper, a novel approach to achieve MOBILE operation is demonstrated using monolithic integration of resonant tunneling diodes (RTD) and FETs. In our new integration structure, an RTD and FET are connected in parallel. This structure offers several advantages including separate optimization of RTD's and FET's, and flexible circuit design abilities. For a single-input MOBILE gate, inverter operation at room temperature is demonstrated as the evidence of monostable-to-bistable transition     

Threshold logic circuit design of parallel adders using resonanttunneling devices

Resonant tunneling devices and circuit architectures based on monostable-bistable transition logic elements (MOBILEs) are promising candidates for future nanoscale integration. In this paper, the design of clocked MOBILE-type threshold logic gates and their application to arithmetic circuit components is investigated. The gates are composed of monolithically integrated resonant tunneling diodes and heterostructure field-effect transistors. Experimental results are presented for a programmable NAND/NOR gate. Design related aspects such as the impact of lateral device scaling on the circuit performance and a bit-level pipelined operation using a four phase clocking scheme are discussed. The increased computational functionality of threshold logic gates is exploited in two full adder designs having a minimal logic depth of two circuit stages. Due to the self-latching behavior the adder designs are ideally suited for an application in a bit-level pipelined ripple carry adder. To improve the speed a novel pipelined carry lookahead addition scheme for this logic family is proposed     

Parallel Adder Design with Reduced Circuit Complexity Using Resonant Tunneling Transistors and Threshold Logic

Quantum-effect devices utilizing resonant tunneling are promising candidates for future nano-scale integration. Originating from the technological progress of semiconductor technology, circuit architectures with reduced complexity are investigated by exploiting the negative-differential resistance of resonant tunneling devices. In this paper a resonant tunneling device threshold logic family based on the Monostable-Bistable Transition Logic Element (MOBILE) is proposed and applied to different parallel adder designs, such as ripple carry and binary carry lookahead adders. The basic device is a resonant tunneling transistor (RTT) composed of a resonant tunneling diode monolithically integrated on the drain contact layer of a heterostructure field effect transistor. On the circuit level the key components are a programmable NAND/NOR logic gate, threshold logic gates, and parallel counters. The special properties of MOBILE logic gates are considered by a bit-level pipelined circuit style. Experimental results are presented for the NAND/NOR logic gate.     

Novel universal threshold logic gate based on RTD and its application

Resonant tunneling diodes (RTDs) are receiving much attention because of their high-speed switching capability and functional versatility. Due to the negative differential resistance exhibited by RTDs, great functionality with a single gate can be achieved. In this paper, novel universal threshold logic gates (UTLG) based on RTD with simple structure and fixed parameter are proposed. The three-variable UTLG implement all the threshold functions of three variables by reconfiguring the input bits. The proposed circuit can also be applied to the design of arbitrary logic function in a multilevel threshold network. Finally, the operation of UTLG is verified by HSPICE simulation using extensively validated models.     

A BiCMOS wired-OR logic

This paper proposes a BiCMOS wired-OR logic for high-speed multiple input logic gates. The logic utilizes the bipolar wired-OR to circumvent the use of a series connection of MOS transistors. The BiCMOS wired-OR logic was found to be the fastest compared with such conventional gates as CMOS NOR, BiCMOS multiemitter logic and CMOS wired-NOR logic, when the number of inputs was more than four and the supply voltage was 3.3 V. The BiCMOS wired-OR logic was also determined to be the fastest of the four when the fan-out number was below 20 and the number of inputs was eight. In addition, the speed was more than twice as faster when the fan-out number was less than 10. The BiCMOS wired-OR logic was applied to a 64-b 2-stage carry look-ahead adder, and was fabricated with a 0.5-μm BiCMOS process technology. A critical path delay time of 3.1 ns from an input to a sum output was obtained at the supply voltage of 3.3 V. This is 35% faster than that of conventional BiCMOS adders     

Compact logic NAND-gate based on a single in-plane quantum-wire transistor

We propose and demonstrate the operation of a monolithic logic NAND-gate based on a single in-plane quantum-wire transistor (QWT). The QWT is controlled by two lateral gates which serve as input terminals with a nonlinear transfer characteristic. Logic operation is demonstrated by exploiting a gate voltage-dependent efficiency of the lateral gates. The compact logic NAND-gate features high input impedance, shows voltage gain, and operates at room temperature.     

Margin analysis of quantum flux parametron logic gates

An analytical approach is used to estimate the (quasi-static) margins of quantum flux parametron (QFP) logic gates. The operation of a single QFP is analyzed in detail, and input biases or output variations caused by parameter fluctuations are obtained. The results are used to estimate the margins and yields of the QFP logic gates. The relations between the margin and the parameter fluctuations are obtained. The yields are estimated assuming normal distributions of the fluctuations. The calculations are consistent with experiments performed to date. The static margins of the QFP logic gates discussed here are sufficient, with presently available process technology, for medium size integrated circuits     

Static hazards in combinational threshold logic networks†

The possibility of transitory false outputs in conventional digital logic circuits is well known, such output ‘ spikes ’ being the result of different propagation times through the logic network from inputs to output. The usual solution to such ‘ Static hazards ’ is also well known, being the incorporation of additional gates in the system to cover such input transitions. This paper shows that the application of threshold logic gates to logic synthesis has attractions in very easily eliminating such hazards, in many cases without the need for any additional covering gates in the network.     

基于RTD的新型全加器设计

单双稳态转换逻辑单元(MOBILE)是基于共振隧穿二极管(RTD)电路的一个重要逻辑单元,非常适合阈值逻辑电路设计。由MOBILE可以构成阈值逻辑门(TG)和广义阈值逻辑门(GTG)等阈值逻辑电路。本文通过将三变量异或函数转化为较简单、理想的GTG输入输出函数形式,设计了由GTG构成的新型三变量异或门,并利用该三变量异或门设计了新型的全加器。通过HSPICE仿真和性能比较,该全加器不仅器件数量少,输出延时短,而且能达到较高的工作频率、更小的电路功耗与功耗-延迟积。     

Optical parallel logic gates using a shadow-casting system for optical digital computing

A new, simple method of optically implementing optical parallel logic gates has been described. Optical parallel logic gates can be implemented by using a lensless shadow-casting system with a light-emitting diode (LED) array as a light source. Pattern logic, i.e., parallel logic for two binary patterns (variables), is simply obtained with these gates; this logic describes a complete set of logical operations on a large array of binary variables in parallel. Coding methods for input images are considered. Applications of the method for a parallel shift operation and optical digital image processing, processing of gray-level images, and parallel operations of addition and subtraction for two binary variables are presented. Comparison of the operation of the proposed optical logic gate with that of array logic in digital electronics leads to a design concept for an optical parallel array logic system available for optical parallel digital computing.     

光电子混合模糊逻辑

本文提出了一种由光电子混合回路构成的简单光学模糊逻辑门设计。演示了补、最大、最小和限界差(相对补)四种最基本的逻辑操作。给出了一个多功能可编程的光电子混合模糊逻辑门,可实现模糊逻辑中七种基本逻辑运算。     

由RTD构成的MOBILE单元电路研究

对由共振隧穿二极管(RTD)构成的单双稳态转换逻辑单元(MOBILE)电路进行了详细地研究与分析,并结合实际RTD的特性用PSPICE进行了MOBILE单元电路模拟,总结和验证了MOBILE单元电路变化的三条规律,为进一步研究由RTD构成的多种复杂数字电路奠定了基础。     

High-speed and low-power operation of a resonant tunneling logicgate MOBILE

High-speed operations up to 35 Gb/s were demonstrated for a resonant tunneling (RT) logic gate monostable-bistable transition logic element (MOBILE). The test circuit consisted of a MOBILE and a DCFL-type output buffer, and it was fabricated using InP-based resonant tunneling diode/HEMT integration technology. This operation bit rate is close to the cutoff frequency of the 0.7-μm gate HEMTs used in the circuit, and was obtained after improvement of the output buffer design. This result indicates the high-speed potential of the MOBILE, though the speed is still limited by the buffer. The power dissipation of the MOBILE was also discussed based on a simple equivalent circuit model of RTDs. This revealed that the power dissipation is as small as 2 mW/gate over a wide range of operation bit rates