Factorial experimental design applied to DRIE for optimised process in power electronics applications requiring high-aspect ratio trenches

A reliable factorial experimental design was applied to DRIE for specifically producing high-aspect ratio trenches. These trenches are to be used in power electronics applications such as active devices: deep trench superjunction MOSFET (DT-SJMOSFET) and passive devices: 3D integrated capacitors. Analytical expressions of the silicon etch rate, the verticality of the profiles, the selectivity of the mask and the critical loss dimension were extracted versus the process parameters. The influence of oxygen in the passivation plasma step was observed and explained. Finally, the analytical expressions were applied to the devices objectives. A perfectly vertical trench 100-μm deep was obtained for DT-SJMOSFET. Optimum conditions for reaching high-aspect ratio structures were determined in the case of high-density 3D capacitors.     

Improvement of sidewall roughness in deep silicon etching

The recently developed High Aspect Ratio Si Etch (HARSE) process is widely used for applications requiring silicon structures with high aspect ratios. This process relies on the alternation of sidewall passivation and silicon etching phases and enables the obtainment of high silicon etch rates and highly anisotropic profiles. This paper reports an innovative approach to improve the sidewall roughness through a multiple-step HARSE process using an ICP system. Unlike the standard HARSE process, the etching conditions for this new process are gradually altered in order to reinforce the silicon etch efficiency as a function of the silicon depth previously etched. Trenches with aspect ratios as high as 40 can be achieved. The sidewall roughness along the entire etching depth is less than 8 nm rms. In comparison with the standard HARSE process in which ripples appear on the trenches sidewall, the sidewall roughness is improved by a factor of 4. Received: 15 July 1999/Accepted: 30 July 1999     

Fabrication of metallic microstructures by electroplating usingdeep-etched silicon molds

A new technology is presented here to fabricate three-dimensional micromachined metal structures. The microstructures are manufactured by electroplating in deep-etched silicon structures followed by a separation from their mold. Up to 140-μm-deep silicon structures with vertical sidewalls are realized by an anisotropic plasma etching process producing the mold for electroplating. An etching gas mixture of SF_6s and CBrF₃ is used to achieve both an anisotropic etching behavior by protective film formation of CF₂ -radicals and high etching rates. The anisotropy is due to photoresist masking, which enhances the polymer formation. The vertical trenches are electroplated from the trench base filling the structures uniformly to the substrate surface. By avoiding overplating across the whole substrate the resulting structures are suitable for micromechanical devices. If needed, released microstructures from the silicon mold can be obtained by direct lift-off     

A Gap Reduction and Manufacturing Technique for Thick Oxide Mask Layers With Multiple-Size Sub-$mu$m Openings

This paper introduces a technique for the fabrication of thick oxide hard masks on top of a substrate with adjustable opening sizes in the sub-$mu$m regime, while the only lithography step involved has$mu$m-scale resolution. This thick oxide mask layer with sub-$mu$m openings is suitable for etching deep narrow trenches in silicon using deep reactive ion etching (DRIE) tools. Openings of less than 100 nm are realized in a 1.5-$mu$m-thick oxide layer, while the original lithographically defined feature sizes are larger than 1$mu$m in width. This method, combined with modified high aspect ratio DRIE recipes, shows a great potential for single-mask batch-fabrication of high frequency low-impedance single crystalline resonators on silicon-on-insulator (SOI) substrates. Dry-etched trenches with aspect ratios as high as 60:1 are fabricated in silicon using the gap reduction technique to realize 200 nm opening sizes in an oxide mask layer. Various resonator structures with sub-$mu$m capacitive gaps are also fabricated on a SOI substrate using a single-mask process. Measurement results from high-frequency and high-quality factor (Q) all single crystal silicon resonators are presented.1684     

High aspect ratio silicon trench fabrication by inductively coupled plasma

Very high aspect ratio silicon trench with nearly vertical sidewall profile had been demonstrated by inductively coupled plasma (ICP) etching. This silicon trench with aspect ratio more than 30 and vertical sidewall were basically fabricated by STS ASE^TM technology and controlled at proper process parameters. We controlled the appropriate platen power and reaction gas to solve the problem of more positive profile at high aspect ratio trench and avoid the bowing formation on the sidewall simultaneously. Different feature sizes for silicon trench were designed to study the aspect ratio dependent etching properties. The 2.2 μm wide trench etched had aspect ratio of 33 and etching rate of 1.8 μm/min while the 5.0 μm wide trench had aspect ratio of 20 and etching rate of 2.5 μm/min. Received: 7 July 1990/Accepted: 25 August 1999     

Rapid soda-lime glass etching process for producing microfluidic channels with higher aspect ratio

This paper presents a simple method to produce microfluidic channels in soda-lime glasses with the aspect ratio >0.5 utilizing a modified wet etching protocol. A low-cost positive photoresist (PR) layer is used as the etching mask for the wet etching process. Prior to the PR and primer coating procedure, a UV activation process is adopted for enhancing the binding strength of the hexamethyldisilazane primer layer and the glass substrate, resulting in an better adhesion for the PR layer. A fast etching recipe is also developed by increasing the acidity and the temperature of the buffered oxide (BOE) etchant. Since the photoresist etching mask does not peel during the etching process shortly, the structure of the etching mask forms a barrier and results in a different diffusion rate for the etchant inside the etched trench structure. A slower etching rate for the glass is observed at the undercut region such that the proposed anisotropic etching pattern can be achieved. Results show that the etching rate of the modified glass etching process is as high as 7.7 μm/min which is much faster than that of pure BOE etchant (0.96 μm/min). Sealed microfluidic channel with the aspect ratio of around 0.62 is produced with the developed method. The method developed in the present study provides a rapid and efficient way to produce microfluidic channels with higher aspect ratio.     

Fabrication of Flexible Transducer Arrays With Through-Wafer Electrical Interconnects Based on Trench Refilling With PDMS

Flexible transducer arrays are desired to wrap around catheter tips for side-looking intravascular ultrasound imaging. We present a technique for constructing flexible capacitive micromachined ultrasonic transducer (CMUT) arrays by forming polymer-filled deep trenches in a silicon substrate. First, we etch deep trenches between the bottom electrodes of CMUT elements on a prime silicon wafer using deep reactive ion etching. Second, we fusion-bond a silicon-on-insulator (SOI) wafer to the prime silicon wafer. Once the silicon handle and buried oxide layers are removed from the back side of the SOI wafer, the remaining thin silicon device layer acts as a movable membrane and top electrode. Third, we fill the deep trenches with polydimethylsiloxane, and thin the wafer down from the back side. The 16 by 16 flexible 2-D arrays presented in this paper have a trench width that varies between 6 and 20 ; the trench depth is 150 ; the membrane thickness is 1.83 ; and the final substrate thickness is 150 . We demonstrate the flexibility of the substrate by wrapping it around a needle tip with a radius of 450 (less than catheter size of 3 French). Measurements in air validate the functionality of the arrays. The 250- by 250- transducer elements have a capacitance of 2.29 to 2.67 pF, and a resonant frequency of 5.0 to 4.3 MHz, for dc bias voltages ranging from 70 to 100 V.     

Electronically controlled etch-mask for silicon bulk micromachining

Wafers that are to be submitted to anisotropic etching in aqueous KOH are conventionally passivated with a silicon dioxide or nitride layer in which backside windows are etched to define the microstructures. A different method to mask the backside of a silicon wafer for this purpose is presented. The method makes use of the phenomenon that silicon is not etched in KOH when biased above the passivation potential. The mask is defined by applying a set of bias voltages to the front of the wafer instead of patterning a deposited passivation layer at the backside, for which an accurate double-sided alignment is required. The feasibility of the method was demonstrated with the fabrication of membranes and suspended masses of various sizes     

几种基于MEMS的纳米梁制作方法研究

特征尺度在纳米量级的梁结构是多种纳机电器件的基本结构.提出了几种基于MEMS技术的纳米梁制作方法,通过利用MEMS技术中材料与工艺的特性实现单晶硅纳米梁的制作.在普通(111)硅片上,利用各向异性湿法腐蚀对(111)面腐蚀速率极低的特性,通过干法与湿法腐蚀相结合制成厚度在100 nm以下的纳米梁.该方法不使用SOI硅片,有效控制了成本.在(100)SOI硅片上,通过氧化减薄的方法得到厚度在100 nm以下的多种纳米梁,由于热氧化的精度高,一致性好,该方法重复性与一致性均较好.在(110)SOI硅片上,利用硅的各向异性腐蚀特性以及(110)硅片的晶向特点,制作宽度在100 nm以下的纳米梁,梁的两个侧面是(111)面.     

Etching through silicon wafer in inductively coupled plasma

 Inductively coupled plasma reactor (ICP) has been used to etch holes, trenches and other shapes completely through 380 and 525 μm thick silicon wafers. Bosch/STS process of gas flow pulsing with SF₆ etch step and C₄F₈ sidewall passivation step was employed. Etch rate reduction due to aspect ratio dependence and pattern size and shape effects have been explored. Etch stop has been studied both on bulk and SOI wafers. Notching effect was observed for high aspect ratio features but it was absent in large, low aspect ratio features. Aluminum etch stop layer has been shown to eliminate notching. Received: 7 July 1999/Accepted: 22 October 1999     

Micromachining of buried micro channels in silicon

A new method for the fabrication of micro structures for fluidic applications, such as channels, cavities, and connector holes in the bulk of silicon wafers, called buried channel technology (BCT), is presented in this paper. The micro structures are constructed by trench etching, coating of the sidewalls of the trench, removal of the coating at the bottom of the trench, and etching into the bulk of the silicon substrate. The structures can be sealed by deposition of a suitable layer that closes the trench. BCT is a process that can be used to fabricate complete micro channels in a single wafer with only one lithographic mask and processing on one side of the wafer, without the need for assembly and bonding. The process leaves a substrate surface with little topography, which easily allows further processing, such as the integration of electronic circuits or solid-state sensors. The essential features of the technology, as well as design rules and feasible process schemes, will be demonstrated on examples from the field of μ-fluidics     

PECVD 工艺中氮化硅薄膜龟裂研究

PE 氮化硅薄膜优异的物理、化学性能使其在半导体分立器件、IC 电路中常被用作绝缘层、钝化层而使用。然而,氮化硅龟裂问题是影响其作为钝化层使用的阻碍因素,因此,科学的氮化硅工艺条件对其薄膜质量的影响非常关键。给出了等离子体化学气相淀积（PECVD）氮化硅薄膜技术的原理,通过实验验证,确定了诱发氮化硅龟裂现象的原因,优化工艺条件,确定了 PECVD氮化硅的最佳工艺条件,杜绝了龟裂现象对氮化硅作为钝化层使用的影响。     

基于金硅腐蚀自停止技术的亚微米梁制作研究

提出了利用无电极电化学腐蚀自停止技术制作亚微米梁结构的新工艺方法。根据金硅腐蚀自停止现象发生的条件,结合硅材料的各向异性腐蚀特性,设计器件结构,利用腐蚀暴露面积变化实现了硅的选择性自停止腐蚀。在(111)型硅片上利用原电池钝化效应一次性腐蚀出与衬底绝缘,由约4μm厚的金电极支撑,厚度约为235 nm的亚微米梁结构,具有制作简单、成品率高、成本低等特点,应用前景广阔。     

Fabrication of buried microfluidic channels with observation windows using femtosecond laser photoablation and parylene-C coating

We developed an advanced method for fabricating microfluidic structures comprising channels and inputs/outputs buried within a silicon wafer based on single level lithography. We etched trenches into a silicon substrate, covered these trenches with parylene-C, and selectively opened their bottoms using femtosecond laser photoablation, forming channels and inputs/outputs by isotropic etching of silicon by xenon difluoride vapors. We subsequently sealed the channels with a second parylene-C layer. Unlike in previously published works, this entire process is conducted at ambient temperature to allow for integration with complementary metal oxide semiconductor devices for smart readout electronics. We also demonstrated a method of chip cryo-cleaving with parylene presence that allows for monitoring of the process development. We also created an observation window for in situ visualization inside the opaque silicon substrate by forming a hole in the parylene layer at the silicon backside and with local silicon removal by xenon difluoride vapor etching. We verified the microfluidic chip performance by forming a segmented flow of a fluorescein solution in an oil stream. This proposed technique provides opportunities for forming simple microfluidic systems with buried channels at ambient temperature.     

Sub-Micro-Gravity In-Plane Accelerometers With Reduced Capacitive Gaps and Extra Seismic Mass

This paper presents a robust fabrication technique for manufacturing ultrasensitive micromechanical capacitive accelerometers in thick silicon-on-insulator substrates. The inertial mass of the sensor is significantly increased by keeping the full thickness of the handle layer attached to the top layer proof mass. High-aspect-ratio capacitive sense gaps are fabricated by depositing a layer of polysilicon on the sidewalls of low aspect- ratio trenches etched in silicon. Using this method, requirements on trench etching are relaxed, whereas the performance is preserved through the gap reduction technique. Therefore, this process flow can potentially enable accelerometers with capacitive gap aspect-ratio values of greater than 40:1, not easily realizable using conventional dry etching equipment. Also, no wet-etching step is involved in this process which in turn facilitates the fabrication of very sensitive motion sensors that utilize very compliant mechanical structures. Sub-micro-gravity in-plane accelerometers are fabricated and tested with measured sensitivity of 35 pF/g, bias instability of 8 mug, and footprint of <0.5 cm².     

Trench filling characteristics of low stress TEOS/ozone oxide deposited by PECVD and SACVD

In this paper low stress silicon oxide was deposited with tetraethylorthosilicate (TEOS, Si(OC₂H₅)₄)/ozone by plasma enhanced chemical vapor deposition (PECVD) and sub-atmospheric chemical vapor deposition (SACVD) for deep trench filling. Two kinds of PECVD oxide were fabricated: Coil antenna inductively coupled plasma (ICP) oxide and parallel plates capacitive coupled plasma (CCP) oxide. Adding ozone into the deposition process enhances the trench filling capability. Oxide filling in a deep trench (5 m wide, 52 m deep) was carried out using the SACVD process, which gave excellent conformal step coverage. However, the coil antenna ICP oxide was suitable as a sealing material. The effects of argon ion sputtering and magnetic field in the PECVD for the trench filling are discussed in this paper. Because the low temperature processes of PECVD and SACVD, the thermal residual stress was reduced and a low stress film of 85 MPa compression is available.This work is supported by a Grant-in-Aid (No. 13305010) from Japanese Ministry of Education, Culture, Sports, Science and Technology. A part of this work has been performed in Venture Business Laboratory, Tohoku University.     

扩散硅压力传感器性能优化研究

本文论述了实现扩散硅压力传感器性能优化的一些技术措施、设计原理和工艺技术.采用矩形双岛硅膜结构等新型微机械结构可提高灵敏度和精度并实现过压保护;通过改善工艺并进行表面钝化、改进封装工艺与结构等可改善稳定性;用恒压源及三极管补偿法和等效电阻最佳耦合法可对其灵敏度、零位温度系数进行补偿;采用各向异性腐蚀工艺技术可实现集成化生产.     

Alternative technology used to manufacture semitransparent monocrystalline silicon solar cells

This paper presents the manufacturing technology of a new semitransparent solar cell that can be used for building integrated applications. Diluted tetramethylammonium hydroxide and isopropyl alcohol mixture is used to create uniform and reproducible pyramidal textures on the silicon wafers, thus reducing surface reflectance. Arbitrary pattern of holes can be etched using 5 wt % tetramethylammonium hydroxide solution. Ammonium persulfate powder has to be dissolved in the bulk etchant in order to maintain a stable 1.34 μm/min etching rate over the 3.5 h etching process. The ARC layer is the 90 nm thick silicon dioxide remaining after the anisotropic etching. The efficiency of the semitransparent solar cell is 6.12 % including grid contact and silicon through-hole areas, the transparency reached is 6.7 %, weighted surface reflectance is 4.31 %.     

A combinative technique to fabricate hot embossing master for PMMA tunneling sensors

A combinative approach of anisotropic bulk etching and modified plasma etching has been successfully employed in a single wafer to fabricate silicon masters for the hot embossing process. The masters hold both pyramid pits and positive profile sidewalls with smooth surfaces and steep angles. The SiO₂ layer is utilized as a etching mask with the aid of photoresist in three steps of photolithography patterning. The first polymethyl-methacrylate (PMMA)-based tunneling transducer with polymer membrane structures is fabricated by hot embossing replication with the silicon master. Consequently, the exponential relations between tunneling currents and applied deflection voltages are also reported.This work is partially supported by grants NSF/LEQSF (2001–04)-RII-02, DARPA DAAD19–02–1-0338, and NASA (2002)-Stennis-22.     

Plasma planarization for sensor applications

Filling trenches in silicon using phosphosilicate glass (PSG) provides many possibilities for novel device structures for sensors and actuators. This paper describes a plasma planarization technique that provides fully planarized PSG filled silicon trenches for sensor applications. The technique consists of planarizing the substrate using two photoresist layers and plasma etching-back. The lower resist layer is the AZ5214 image reversal resist, which is patterned and then thermally cured. The upper resist layer is a global HPR204 coating. The plasma etching-back is carried out using CHF₃/C₂F ₆ gas mixture with an O₂ addition. It is shown that by using the image reversal photoresist approach, fully planarized surface coating can be obtained without resorting to an additional mask. By adding 25 sccm (14%) O₂ into the 137 sccm CHF₃+18 sccm C₂F₆ gas mixture, the etch rates for the photoresist and PSG can be matched. Process optimization for the two layer resist coating and plasma etching is discussed