10Gbit/s甚短距离并行光传输模块研究

本文讨论了符合OIF-VSR4-01.0规范的10Gbit/s 甚短距离(VSR)并行光传输模块实验系统、转换集成电路、12通道850nm垂直腔面发射激光器(VCSEL)并行光发射模块、12通道并行光接收模块中的12通道前端放大电路的实现,并给出了系统测试方案和测试结果。测试结果表明,转换集成电路数字逻辑部分的全部功能用FPGA实现,研制的12通道并行光发射模块传输带宽达12?.244Gbit/s。在点到点的传输测试中,采用12芯400MHz-km 62.5靘多模带状光纤时,传输距离达302米,系统误码率低于1?0-13,12通道前端放大电路单路工作速率达1.25Gbit/s。     

基于FPGA/CPLD的通用异步通信接口UART的设计

UART（通用异步接收发送设备）是一种短距离串行传输接口。在数字通信和控制系统中得到广泛应用。FPGA／CPLD是大规模集成电路技术发展的产物．是一种半定制的集成电路。结夸计算机软件技术（EDA技术）可以快速、方便地构建数字系统。本文介绍一种采用可编程逻辑器件FPGA／CPLD实现UART的方法，将UART的核心功能集成到FPGA／CPLD上，本设计包含UART的发送模块、接收模块和波特率发生器，所有功能的实现全部采用VHDL件描述语言来进行描述。设计、综合、仿真在QUARTUSII软件开发环境下实现。     

CMOS电路由设计到实现的经典指南美国电子与计算机工程领域获奖作品

内容简介：《CMOS集成电路设计手册》译自CMOS Circuit Design，Layout,and Simulatio，是CMOS集成电路设计的权威指南，包含CMOSfl,3基础知识以及模拟／数字电路各模块重要而实用的内容，例如锁相环、delta—sigma感测电路、参考电压／电流、运算放大器（op—amp）、数据转换器设计等。为方便读者更有条理性、选择性地学习，在策划该著作中文译本时，     

Δ-∑A／D转换器中数字下变频解调器的设计与实现

从集成电路设计技术的角度，介绍了Δ-∑A／D转换器中数字下变频解调器的原理和集成实现方法。釆用CSD码，用CIC滤波器、半带滤波器，实现了16位Δ-∑A／D转换器中的抽取器。对所设计的HDL代码进行了综合及仿真。结果表明，设计达到了精度要求，且具有速度快、面积小的特点。     

无线收发模块设计实现

研究并设计了一种低成本无线收发模块。采用F05P发送模块、J04V接收模块和PT2262,PT2272编解码集成电路,实现无线收发模块的数据收发。     

无线收发模块设计实现

本文研究并设计了一种低成本无线收发模块,采用F05P发送模块,J04V接收模块和PT3362/PT2272编解码集成电路,实现无线收发模块的数据收发。     

红外解码液晶显示设计的Proteus仿真

本论文主要介绍红外遥控解码显示设计,接收程序的通用性好,易于移植到其他红外遥控接收装置。其主要包含控制器模块、红外接收模块、12864液晶屏显示模块和EEPROM外部存储器模块。此设计以ATMEL公司AT89S52单片机为系统的控制核心,采用1838红外接收头及12864液晶屏显示等为硬件主体,实现红外遥控解码并显示。软件部分用KeilC进行模块化设计,基于Proteus强大的仿真功能和丰富的元件仿真模型,直观地观测出电路的仿真效果,成功完成红外解码液晶显示设计任务。     

TM—7模拟集成电路测试系统线接收器适配器设计

1 前言目前国内集成电路的常用测试设备为TM—6数字集成电路测试系统和TM—7模拟集成电路测试系统。主要解决了TTL数字集成电路、CMOS集成电路及一部分线性电路如集成运算放大器、集成稳压器、电压比较器、A/D转换器、D/A转换器的测试,但其余大部分线性电路的测试问题还未能得到解决。我们在用TM—6测试时基电路555的基础上得到启示,形成了在TM—7上设计测试线接收器所用适配器的设计思想,在此作一详细介绍。     

嵌入式多协议转换器的研究

设计给出了嵌入式多协议转换器软硬件实际解决方案。系统硬件部分主要包括RS-232接口模块、USB接口模块、以太网接口模块、存储器模块、电源模块、中央处理器模块等部分。中央处理器采用三星公司的ARM9 S3C2440A。软件部分基于嵌入式LINUX系统架构。实现了RS-232、USB与TCP/IP协议间的转换。经过测试,该转换器使原有低速率、短距离传输的串口设备能够可靠快速地接入以太网,实现系统的现代化远程管理。     

CMOS电路由设计到实现的经典指南 美国电子与计算机工程领域获奖作品

内容简介：《CMOS集成电路设计手册》译自CMOSCircuit Design,Layout,and Simulatio,是CMOS集成电路设计的权威指南,包含CMOS的基础知识以及模拟／数字电路各模块重要而实用的内容,例如锁相环、delta—sigma感测电路、参考电压／电流、运算放大器（op—amp）、数据转换器设计等。为方便读者更有条理性、选择性地学习,在策划该著作中文译本时,     

Compact 10-Gbit/s optical transmitter and receiver circuit packs

Compact wideband 10-Gbit/s optical transmitter and receiver circuit packs are realized using high speed analog and digital GaAs IC's as well as a highly thermally conductive board and appropriately designed small function block modules that employ multichip packaging and resonant cavity mode damping. To achieve a compact receiver, the receiver circuit employs a clamp and peak-detector IC in the high speed analog equalizer amplifier to obtain a constant output direct current level for any mark density imbalance in the number of ones and zeros in the signal and a variable phase-shifter IC in the timing circuit. Realized circuit pack size is 200×280×15.24 mm and the power consumption of each pack is about 25 W     

A 30 GHz MMIC receiver for satellite transponders

The development of 30-GHz-band monolithic microwave integrated circuits (MMICs) and multichip MMIC modules (low-noise amplifier and frequency converters) is reported. A 30-GHz-band full-MMIC receiver for satellite transponders was successfully constructed using the MMIC modules and the performance of the full-MMIC receiver is evaluated. Test results verify its successful performance as a satellite receiver system. The design and performance of the MMICs (a two-stage amplifier, an image rejection mixer, and a frequency multiplier), of multichip-type MMIC modules (a 30-GHz-band low-noise amplifier module with 30 dB gain and 8.2 dB noise figure, and an image rejection frequency converter with a 10 dB conversion loss and an 18 dB image rejection ratio) and of the full-MMIC receiver, which weighs 1/6 as much as a conventional hybrid integrated circuit are presented     

基于FPGA的RCN226绝对式编码器通信接口设计

实现了一种基于FPGA的绝对式码盘智能接口的设计,用以进行绝对式编码器和DSP之间的通信。此接口根据FPGA模块化设计的特点,把整个设计任务划分为若干功能模块,分别对这些模块进行设计,最后把各个功能模块进行综合,以完成整个设计。实验结果表明,该接口基本可以替代价格昂贵的专用接口芯片,降低产品成本。     

高性能PWM型DC-DC升压变换器研究

设计了一种单片集成PWM型电流模式升压变换器,芯片内部集成了耐压22V的DMOS功率开关管,开关频率为1.6MHz,采用1.5μmBCD工艺实现。芯片具有很宽的输入电压(2.7~14V)、高效率(85%)、低关断电流、快速暂态响应和低功耗等特性,适宜于用作便携式设备的电源管理,也可作为IP核,嵌入同种工艺下的其它芯片。文中除了对芯片设计方法、思路及主要电路模块结构的设计方案进行讨论外,还提出了减小单片集成开关电源噪声的措施。     

Reconfigurable radio receiver with fractional sample rate converter and multi-rate ADC based on LO-derived sampling clock

A composite radio receiver back-end and digital front-end, made up of a delta-sigma analogue-to-digital converter (ADC) with a high-speed low-noise sampling clock generator, and a fractional sample rate converter (FSRC), is proposed and designed for a multi-mode reconfigurable radio. The proposed radio receiver architecture contributes to saving the chip area and thus lowering the design cost. To enable inter-radio access technology handover and ultimately software-defined radio reception, a reconfigurable radio receiver consisting of a multi-rate ADC with its sampling clock derived from a local oscillator, followed by a rate-adjustable FSRC for decimation, is designed. Clock phase noise and timing jitter are examined to support the effectiveness of the proposed radio receiver. A FSRC is modelled and simulated with a cubic polynomial interpolator based on Lagrange method, and its spectral-domain view is examined in order to verify its effect on aliasing, nonlinearity and signal-to-noise ratio, giving insight into the design of the decimation chain. The sampling clock path and the radio receiver back-end data path are designed in a 90-nm CMOS process technology with 1.2V supply.     

一个高精度、低成本10位数字模拟转换器的设计与实现

随着集成技术的日益发展,高精度的数字模拟信号转换器模块（DAC）已经是许多芯片中不可或缺的模块。影响数模转换精度关键的因素之一是电阻的匹配程度。本文详细地描述和实现了一个采用UMC0.35μm工艺的高精度、低成本的10位DAC的设计电路,该电路对电阻匹配系数要求与7位DAC的要求相同,对工艺、版图精度的要求降低了8倍,在相同精度要求下有效减小了版图面积,降低了设计难度和生产成本。最后在版图上采用新颖的排列方式,进一步降低了温度等因素的影响。本文设计的DAC的精度为DNL范围在-0.2～＋0.2,INL范围在-0.6～＋0.6。该模块已经成功应用在某些驱动芯片中。     

A Gigabit Link CMOS Analog Interface for High Performance Signaling

In this brief, design of a gigabit link CMOS analog interface composed of a transmitter, a receiver, and clocking circuits is addressed with focus on high-performance signaling in terms of interference and jitter. The low-cost, low-power interface is targeted at parallel link applications. The transmitter adopts one-tap preemphasis to mitigate the intersymbol interference (ISI) problem. The receiver samples two adjacent bits and stores the difference of them to a capacitor, so it is more immune to timing uncertainties caused by nonideal sampling clocks and it is dependent only on the direction or difference of two consecutive bits, not on the absolute values of them. With these circuits, robust clocking circuits to multiplex and demultiplex the data on the transmit and receive side, respectively, are designed. Pseudo-differential-type delay elements are used in the oscillator and delay line to enable high power supply rejection ratio and low jitter. The delay locked loop (DLL) is designed to prevent harmonic locking. The transceiver performance is tested at 1 Gbps and 2 Gbps for double and quadruple interleaving, respectively. The maximum operating speed is about 1.7 Gbps for double interleaving and about 3 Gbps for the quadruple-interleaving receiver under a 3.3 V, 0.35 μm CMOS process. Sungkyung Park Large Scale SoC Research Department, Electronics and Telecommunications Research Institute(ETRI), 161 Gajeong-dong, Yuseong-gu, Daejeon 305–350, Korea (fitzgerald1971@yahoo.com) Sungkyung Park received B.S. (with highest honors) and M.S. degrees from Seoul National University, Korea, in 1995 and 1997, respectively. He received a Ph.D. degree in CMOS IC design from Seoul National University, Korea, in 2002. During the military service, from 2002 to Sep. 2004, he was with the Telecommunication Network, Samsung Electronics, Inc., Korea, as a Senior Engineer, where he was engaged in developing cdma 2000 system-level simulators. From Oct. 2004 until now, he has been with the Large Scale SoC Research Department, Electronics and Telecommunications Research Institute (ETRI), Korea, as a Senior Researcher. His research interests cover high-speed analog and mixed-mode CMOS IC design including RF CMOS IC design, data converter design, and issues in wireless/wireline communication SoC/NoC.     

10Gbit/s甚短距离并行光传输模块与实验系统

介绍符合OIF-VSR4-03.0规范的10Gbit/s甚短距离(VSR)实验系统研究.该系统由16×622Mbit/s到4×2.488Gbit/s转换集成电路、自制12通道850nm垂直腔面发射激光器(VCSEL)并行光发射模块和商用12通道并行接收光模块构成.用一片FPGA实现转换芯片的全部功能,采用基于二分查找法的SDH STM-64/OC192 并行帧对齐及同步算法,大大提高了转换芯片的工作速度和节省了逻辑资源,自制12通道VCSEL并行发射模块工作速率达到12×2.488Gbit/s的设计指标.在SDH STM-64/OC192 10Gbit/s测试仪点到点的传输系统测试中,采用5米的12芯400MHz·km 62.5μm多模带状光纤互联,系统误码率低于1×10^-14.     

Hermetic-equivalent packaging of GPS MCM-L modules for highreliability avionics applications

Results are presented of comparative reliability testing of multichip modules (MCM's) fabricated with laminate substrates, and protected with various bare-die coatings. The demonstration MCM's included two design versions (flip-chip and wire-bond) of the digital portion of global positioning system (GPS) receiver multichip modules. This paper summarizes the results for the wire-bonded constructions. Standard encapsulants and new inorganic coatings (Dow Coming's ChipSeal(R) hermetic coating materials') were evaluated in environmental stress exposures corresponding to high reliability avionics applications. Full wafer probe testing was performed both before and after the supplemental ChipSeal processing and dip-chip wafer bump processing steps. ChipSeal and flip-chip wafer processing steps were shown to cause no yield degradation on wafer lots of five different IC types used in the overall program. The environmental test results demonstrate that MCM-L units with bare die packaging can be designed for very robust reliability applications such as military and other high reliability avionics     

A reconfigurable low-pass/high-pass \varDelta \varSigma ADC suited for a zero-IF/low-IF receiver

This paper presents the design of a reconfigurable delta sigma analog to digital converter. Its main degree of freedom is the choice of the noise shaping between low-pass and high-pass. Thanks to this reconfiguration parameter, the converter takes full advantage of both noise shapings and employs the most suited architecture depending on the received standard. Moreover, the low-pass/high-pass reconfiguration makes the analog-to-digital converter compliant for both the low-IF and the zero-IF receiver architectures. The paper also presents a novel reconfigurable dynamic element matching technique which efficiently addresses the digital to analog converter mismatch for both the high-pass and the low-pass delta sigma modulators. The sampling frequency and the quantizer number of bits are likewise adjustable. A GSM/UMTS compliant delta sigma analog to digital converter including reconfigurable decimator has been designed in a 1.2 V 65 nm CMOS process. The high-pass modulator is employed in a low-IF receiver for the GSM mode to profit from its robustness against offset and 1/f noise. For the UMTS mode, the low-pass modulator is employed in a zero-IF receiver because of its lower sensitivity to clock jitter.