一种高精密的Gm-C 2阶带通滤波器的设计

针对红外接收芯片对带通滤波器参数可调的要求,提出了一种高精密的Gm-C 2阶带通滤波器。该滤波器的中心频率、带宽和通带增益均可调。电路采用0.35μm标准CMOS工艺进行流片。测试结果显示,电路中心频率调节精度为0.8 kHz。该电路结构简单、容易集成,可广泛应用于红外遥控接收系统。     

高竞争力的电能计量芯片相位偏差校正方法

传统电能计量芯片需要提供较大容量的采样数据缓存器，用于相位偏差校正，该缓存器占用较大的芯片面积，增加了芯片成本，提出了一种新的电能计量芯片相位偏差校正方法，它根据相位偏差值计算一阶全通滤波器系数，并采用选择开关将其置于需要进行相位校正的信号通道，利用其相移特性完成相位偏差校正。该方法不仅可以保证较高的校正精度，而且无需数据缓存，节省内存空间，简化了硬件电路实现，降低了芯片总成本，提高了产品竞争力。     

基于线性曲率校正技术的低电压带隙基准源设计

采用电流求和取代传统电压求和的方法设计了一款低基准电压输出的带隙基准电压源电路,同时提出一种线性化P-N结正向导通电压（VBE）的温度曲率校正技术,保证了基准电压的低温漂和高精度。整个电路采用TSMC0.6μmBCD工艺设计实现,芯片面积为0.2mm2。在Cadence环境下使用Spectre对电路进行了模拟仿真,仿真结果表明：该基准电路可在低至1.1V的电源电压下正常工作;在-20℃～120℃温度范围内,温度系数为9.1×10-6/℃,PSRR为-78dB。在典型的1.5V电源电压下,基准输出电压可调节范围为0.165～1.25V。     

一种有源滤波器的RC常数自动调节电路及其算法

有源RC滤波电路时间常数随集成电路制造工艺变化,为此我们设计了一种高精度RC常数调节电路。提出了一种RC常数自动调节的算法。在SMIC 0.18um工艺中实现了对中心频率为2.2MHz,信号带宽为100kHz的6阶带通滤波器的RC常数的自动调节。在全工艺角范围内,调节精度达0.5~1%。     

应用于直接变频架构直播卫星调谐器中的具有宽调谐范围的连续时间低通滤波器

本文用0.35微米锗硅BiCMOS工艺设计了七阶巴特沃兹跨导电容低通滤波器及其片上自动调谐电路,该低通滤波器适用于采用直接变频架构的直播卫星调谐器。该滤波器的-3dB带宽截止频率具有从4MHz到40MHz的宽调谐范围。成功实现了一种新颖的片上自动调谐方案,用来调谐和锁定滤波器的-3dB带宽截止频率。测试结果表明,该滤波器具有-0.5dB的通带电压增益,+/- 5%的带宽精度,30nV/Hz1/2的等效输入噪声,-3dBVrms 通带电压三阶交调点,27dBVrms 阻带电压三阶交调点。I/Q正交两路滤波器及其调谐电路采用5V电源,在滤波器的-3dB带宽截止频率为20MHz的情况下,消耗电流13毫安,占用芯片面积0.5mm2。     

低功耗可配置CIC滤波器设计

针对超大规模集成电路的发展以及无线射频芯片中带宽可变的需求,提出一种低功耗可配置级联积分梳状(Cascade Integral Comb, CIC)滤波器结构。该结构采用半字节串行算法优化ASIC电路内部位宽,借助多路复用技术减少运算逻辑和存储逻辑单元,并在增益校正部分采用正则有符号数(Canonic Signed Digit, CSD)编码乘法代替全位宽二进制补码乘法,从而实现低功耗目的。信道带宽配置模块选取CIC滤波器采样因子,实现带宽可变功能。通过MATLAB Simulink搭建抽取滤波器模型以验证算法可行性,并采用verilog HDL完成代码设计,仿真结果表明该滤波器可实现2～16倍下采样。基于65 nm COMS标准单元工艺库进行DC综合和ASIC版图设计,与传统CIC滤波器比较,数字电路在功耗方面具有显著优势。     

一种具有动态带宽校正功能的锁相环

提出了一种锁相环的动态带宽校正方法。通过监测压控振荡器的频率增益、反馈调节电荷泵电流,对锁相环的带宽进行补偿,保证锁相环的闭环带宽始终大于信号速率。采用该方法,能够在兼顾设计复杂度和低噪声的情况下,获得最小的锁相环闭环带宽裕度,降低功耗。基于SMIC 0.18 μm 1P4M CMOS工艺,实现了一个2.4 GHz的频率调制发射机芯片。发射机采用单点输入结构,可对锁相环进行直接调制,整个芯片面积仅为1.54 mm²。测试结果表明,该方法可以动态校正因VCO频率增益变化引起的锁相环带宽偏差,实现了数据的稳定传输。     

一种带宽可调的低通开关电容滤波器的设计

介绍了一种带宽可调的二阶低通开关电容滤波器，带宽调节范围为100～500Hz，调节精度约为100Hz。该滤波器用双层金属、双层多晶硅1．2μm的N阱MOS工艺实现，用于一个加速度传感器电路中。设计着重考虑了由时钟信号引起的、严重制约开关电路性能的各种因素，通过优化开关的时序，消除了电荷注入引起的非线性效应，并采用高电源电压抑制比的折叠结构运算放大器，以减轻电源噪声的影响，从而有效地改善了电路的精度。     

一种宽范围高精度滤波器设计

提出了一种同时实现宽的带宽调谐范围和高的带宽频率精度的滤波器设计方法,克服了采用传统带宽校准方法设计滤波器时带宽调谐范围和精度相矛盾的弊端。设计方法通过计算机模拟验证和0.13μmCMOS工艺流片测试,结果与理论预期一致。实验结果表明,在实现5～30MHz的宽范围连续调谐的滤波器中,在保证带宽频率误差低于6%的情况下,滤波器仅需占用0.2mm2的面积。     

电视显示系统中Gamma校正电路的改进

以彩电Gamma校正的最新进展为背景,介绍了3种电视显示模型,并针对现有Gamma校正电路的不足,提出了Gamma校正的改进方法,其在硬件开销和精度控制上达到了很好的折衷.实验结果证明该方法在基本保证图像质量的前提下,可大大减小芯片面积,节省功耗.     

基于DSP和PowerPC的开放式伺服控制系统设计

设计了一种基于DSP和PowerPC的开放式伺服控制系统,该系统主要采用TMS320C6713微控制器实现通信及控制算法的运算。硬件部分介绍了双端口RAM电路、电源电路及复位电路,并提出了PowerPC端和DSP端基于双端口RAM芯片进行通信的方法。软件部分每400 us进行一次伺服采样运算并通过PID调节进行误差补偿。通过实验对PID算法部分进行参数整定及误差分析,结果证明,该伺服运动控制系统可达到良好的控制精度。     

具有精确恒定跨导偏置电路的Gm-C滤波器

改进了一种精确恒定跨导偏置电路,通过对电流和晶体管尺寸的设计使主电路跨导恒等于外接高精度电阻跨导,与传统结构相比具有更高的精度.将该偏置电路应用于无线传感网芯片中9阶Gm-C椭圆低通滤波器的设计,使该滤波器省去了片上调谐电路的设计,在降低功耗的同时提高了精度,节省了面积.设计基于SMIC 0.18μm 1.8 V 1P6M CMOS工艺,芯片面积仅为0.9 mm×0.22 mm,测试结果表明,该滤波器的截止频率与设计值相差在1%以内,输入噪声电压小于25 nV/√Hz,消耗电流仅为0.9 mA,满足无线传感网节,点芯片的要求.     

基于红外热图序列的板级芯片故障诊断研究

提出一种基于红外热图序列的板级芯片开/短路缺陷检测方法。首先记录芯片关键区域在上电程序响应过程的温度均值序列,运用Savitzky Golay卷积平滑法对其平滑滤波后提取时域特征参量,利用主成分分析法优选关键特征;然后构建支持向量机分类模型,利用粒子群算法优化支持向量机模型参数,使其能有效区分不同的电路板故障类型。为验证提出的方法在芯片开/短路缺陷检测中的有效性,在开发板上的主控芯片上进行了多种焊球开/短路模拟实验。结果表明,优化后的分类模型在测试集的交叉验证分类准确率为96.90%,证明了该方法诊断芯片开/短路缺陷的有效性。     

High speed and silicon-saving adaptive tuning system for high frequency Gm-C filters

In this paper, a novel adaptive tuning system used in Gm-C continuous time (CT) filters has been presented. The novelty of this method is the generation of quasi-gradient functions for the adaptive algorithm. By this method we have implemented the fully adaptive tuning algorithm on chip, and received more than 95% precision for the all characteristics of Gm-C filter. All the circuit level simulations and prototype fabrication have been done using 0.6 μ CMOS technology of AMS.     

An RC time constant auto-tuning structure for high linearity continuous-time /spl Sigma//spl Delta/ modulators and active filters

An automatic RC time constant tuning scheme is proposed for high linearity continuous-time g/sub m/-C and active RC circuits in a low power consumption environment. Instead of changing the g/sub m/ (in g/sub m/-C filters), the RC time constant is tuned by discretely varying the integration capacitors to preserve a high linearity. The auto-tuning circuit, consisting of an analog integrator, a voltage comparator, and a digital tuning engine, generates a control word and sets on-chip capacitors to obtain an RC time-constant accuracy of /spl plusmn/2-10%. The proposed scheme is verified by the experimental results of a test chip in a 0.5 /spl mu/m CMOS technology. It achieves a peak S/(N+D) of 83 dB while a tuning range of over /spl plusmn/40% is accomplished.     

A circuit technique for broadbanding the electronic tuning range of Gunn oscillators

A circuit technique is described whereby the electronic tuning range obtained by varactor tuning solid-state oscillators, such as Gunn oscillators, can be improved. The principle of the technique has been demonstrated by doubling the tuning range obtained from a coaxial X-band Gunn oscillator using distributed circuit elements. An analytical expression for the improved tuning range is presented and predictions for the improvement in an existing microstrip X-band oscillator using chip devices given.     

Gyrator video filter IC with automatic tuning

A single-chip gyrator filter for separating the components of the video signal in a TV receiver is described which is suitable for mass production in a standard bipolar process (f/SUB T//spl ap/400 MHz). The 11 mm/SUP 2/ filter chip operates at frequencies up to 10 MHz, requires no tuning or alignment and has Q-factors which are stable with temperature. The IC contains an automatic tuning system which tunes the five resonators of the filter by aligning an auxiliary gyrator resonator with the crystal oscillator present in the color decoder of a TV receiver. Problems of matching the frequencies of the individual gyrator resonators are discussed, showing how alignment accuracy of 0.5 percent can be obtained when resistivities and specific capacitances have production spreads of at least 10 percent. Various gyrator circuit configurations are given which minimize the circuit complexity and, hence, the chip area. Computer aided design techniques for the filter using geometrically scaled models and macromodeling are presented and it is shown how a complete simulation of the chip led to a significant improvement in bandstop performance. Finally, the measured responses are presented and the filter performance is discussed in the light of present-day requirements.     

State reduction for efficient digital calibration of analog/RF integrated circuits

Calibration of analog/radio-frequency (RF) integrated circuits addresses the problem of yield loss that is a result of the increased variability commonly observed in nanoscale processes. In order to compensate for increased yield loss, calibration techniques have been developed that are applied to fabricated chips, aiming at the restoration of a circuit’s performance to its acceptable range of values that are defined by the specifications. To allow calibration, adjustable elements are introduced that provide multiple states of a circuit’s operation through built-in tuning knobs. Digital calibration—that refers to the case of discrete tuning knob settings—is performed by switching to a circuit’s state at which all performance characteristics are restored to their specified ranges. Due to the large number of performance characteristics of interest a large space of tuning knob settings should be explored, that leads to a series of practical considerations that need to be addressed, such as increased times required for calibration preparation and conduction, or chip area overhead if built-in tuning knobs are used. In this paper we present a method to maintain a desired level of yield recovery through the exploitation of only a minimum number of calibration states, also ensuring low cost by shortening calibration times and reducing chip area overhead. The proposed method is assessed through case studies conducted on a typical RF mixer designed in a 180 nm CMOS technology.     

管芯S参数的提取技术

介绍了一种新颖的提取管芯S参数的方法。这种方法从电路等效理论出发,把除管芯以外的寄生参数用等效电路表示,用微波仿真软件去除这部分电路的影响,就可得出管芯的S参数。本文使用的微波仿真软件是Microwave Office。此方法简单易行、精确度高,有很好的实用价值。     

A 0.7 V 6.66–9.36 GHz wide tuning range CMOS LC VCO with small chip size

The circuit designs are based on TSMC 0.18 μm CMOS standard technology model. The designed circuit uses transformer coupling technology in order to decrease chip area and increase the Q value. The switched-capacitor topology array enables the voltage-controlled oscillator (VCO) to be tuned between 6.66 and 9.36 GHz with 4.9 mW power consumption at supply voltage of 0.7 V, and the tuning range of the circuit can reach 33.7%. The measured phase noise is ?110.5 dBc/Hz at 1 MHz offset from the carrier frequency of 7.113 GHz. The output power level is about ?1.22 dBm. The figure-of-merit and figure-of-merit-with-tuning range of the VCO are about ?180.7 and ?191.25 dBc/Hz, respectively. The chip area is 0.429 mm² excluding the pads. The presented ultra-wideband VCO leads to a better performance in terms of power consumption, tuning range, chip size and output power level for low supply voltage.