共查询到19条相似文献,搜索用时 811 毫秒
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本文档针对ARM CPU芯片,介绍了支持双核CPU芯片调试功能仿真平台和验证平台的设计及实现方法.调试功能仿真平台主要由验证脚本和Debug Driver程序组成;调试功能验证平台是基于仿真平台进行设计,直接使用仿真平台的Debug Driver程序,由MCU中验证程序替代仿真验证脚本的功能,使用验证设计更加灵活、全面... 相似文献
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64位CPU的FPGA原型验证 总被引:1,自引:0,他引:1
验证是IC设计中非常重要的一个环节。为了在功能验证时达到更快的验证速度,引入了FPGA原型验证。首先介绍了FPGA的原型验证基础,然后重点说明了64位CPU的FPGA原型验证的具体实现。其中主要包括基于验证平台的代码转换、综合、实现、配置及调试等。在充分的测试后,增加了CPU功能的完整性和正确性。本文对于验证设计有重要的指导意义。 相似文献
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基于PC与数据采集系统的DSP&CPU芯片功能验证方案 总被引:1,自引:1,他引:0
随着现代超大规模集成电路设计、制造工艺的快速发展,芯片的测试与验证所需的费用也越来越高.针对这个问题,本文提出了一种数字芯片的功能验证方案,该方案充分利用了PC机的丰富资源和数据采集系统的强大功能,有效地降低了数字芯片功能验证的成本.作者成功地运用该方案对一个百万门级的DSP&CPU芯片进行了功能验证,实际应用证明,该方案使用灵活、可靠,并且可以大幅降低芯片验证所需的费用,为数字芯片的功能验证提供了可以借鉴的有效方案. 相似文献
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基于SoC设计的软硬件协同验证技术研究 总被引:2,自引:0,他引:2
软硬件协同验证是SoC设计的核心技术。其主要目的是验证系统级芯片软硬件接口的功能和时序,验证系统级芯片软硬件设计的正确性,以及在芯片流片回来前开发应用软件。本文介绍了基于SoC设计的软硬件协同验证方法学原理及其验证流程。然后分析了SoC开发中采用的3种软硬件协同验证方案,ISS方案、CVE方案、FPGA/EMULATOR方案,对其验证速度、时间精度、调试性能、准备工作、价格成本、适用范围等各方面性能做出比较并提出应用建议。 相似文献
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针对一款网络协议处理芯片,为了保证其设计的正确性,提升验证效率,基于OVM架构,通过SystemVerilog语言搭建了具有受约束的随机激励生成、错误注入、覆盖率收集、正确性自检查等功能的验证平台。通过该验证平台对芯片进行了全方位的高效验证,实现了一次流片成功。基于OVM的验证平台具有良好的可重用性和可扩展性,相对于传统的编写定向测试激励的方法,在验证的高效性、完备性上具有显著的优势。 相似文献
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讨论了验证平台的设计理论、功能以及结构几方面问题,并使用硬件描述语言搭建了自检查的NAND Flash控制器验证平台,在此基础上对控制器进行了全面的功能验证过程。仿真结果验证了该方法的正确性,此方法提高了验证效率、缩短了芯片的研发周期。 相似文献
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提出了一种基于8 bit CPU的混合信号SoC的验证平台.该平台能够完成IP模块验证、软硬件协同验证、混合验证等关键验证流程.该验证平台已经成功地应用在某混合信号SoC的设计上,并在0.35 μm CMOS工艺上进行了实现.该验证平台对其它混合SoC设计具有一定的参考作用. 相似文献
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Uchiyama K. Aoki H. Nishii O. Hatano S. Nagashima O. Oishi K. Kitano J. 《Solid-State Circuits, IEEE Journal of》1991,26(4):566-571
The design of a second-level cache chip with the most suitable architecture for shared-bus multiprocessing is described. This chip supports high-speed (160-MB/s) burst transfer between multilevel caches and a newly proposed cache-consistency protocol. The chip, which supports a 50-MHz CPU and uses 0.8 μm CMOS technology, includes a 32 kB data memory, 42 kb tag memory. and 21.7 K-gate logic 相似文献
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Tien C.-K.V. Lewis K. Greub H.J. Tsen T. McDonald J.F. 《Very Large Scale Integration (VLSI) Systems, IEEE Transactions on》1997,5(2):238-243
This paper examines the design of a 32-b GaAs Fast RISC microprocessor (F-RISC/I). F-RISC/I is a single chip GaAs Heterojunction MESFET (HMESFET) processor targeted for implementation on a multichip module (MCM) together with cache memories. The CPU architecture, circuit design. Implementation, and testing are optimized for a seven-stage instruction pipeline implemented with GaAs super-buffered FET logic (SBFL). We have been able to verify novel GaAs SBFL standard cells and compare measured CPU performance with performance estimates based on circuit and device models. The prototype 32-b microprocessor has been implemented using an automated standard cell approach because of time constraints and fabricated using an experimental process by Rockwell International. The CPU chip integrates 92340 transistors on a 7×7 mm2 die and dissipates 6.13 W at 180 MHz. Test results from a prototype fabrication run have demonstrated the operation of the ALU, the program counter, and the register file with delays below 6, 5, and 3.4 ns, respectively. The successful modeling and verification indicate that a 0.5 μm HMESFET implementation of F-RISC/I could achieve a peak performance of 350 MHz. The wiring delays account for 42% of the critical path delay 相似文献
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对静态随机存储器(SRAM)全定制设计过程中的版图设计工作量大、重复性强的问题进行了分析,并在此基础上提出了一种新的应用于SRAM设计的快速综合技术。这种技术充分利用SRAM电路重复单元多的特点,在设计过程中尽可能把电路版图的硬件设计转换为使用软件来实现,节省了大量的版图设计和验证的时间,从而提高了工作效率。这种技术在龙芯Ⅱ号CPU的SRAM设计中得到了应用;芯片采用的是中芯国际0.18μm CM O S工艺。流片验证表明,该技术对于大容量的SRAM设计是较为准确而且有效的。 相似文献
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All modern low power system on a chip (SoC) architectures are equipped with an in-built power management system. Every new system is expected to have more features and lower power consumption, resulting in a continuous demand to improve energy efficiency. To cope up with the ever increasing demand, an active power-aware management verification architecture is necessary to minimize the power consumption. Power reduction techniques include clock-gating, power-gating, multi-voltage, and voltage-frequency scaling. The proposed verification architecture utilizes the Unified Power Format (UPF) 2.1 libraries to achieve early design verification at the Electronic System-Level (ESL) of abstraction. The proposed testbench can verify several designs of different power management schemes. The presented work offers a reduction in power states, CPU time and simulation time as compared to existing techniques. The interactive formal and simulation-based verification methods are used in this paper to remove the simulation artifacts during functional and power co-simulation. Additionally, this paper incorporates functional correctness and power-aware checks for different modules of Design Under Verification (DUV) at Transaction-Level Modeling (TLM). 相似文献
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Lotz J. Miller B. Delano E. Lamb J. Forsyth M. Hotchkiss T. 《Solid-State Circuits, IEEE Journal of》1990,25(5):1190-1198
A 90-MHz CMOS CPU has been designed for sustained performance in workstation and commercial/technical multiuser applications. The CPU is part of a multichip system that achieves a 60-MHz operating frequency with 15-ns asynchronous SRAMs. Key performance features include a 3.5-ns 32-b adder, low skew on-chip clock buffers, and cycling large off-chip caches at the operating frequency. The chip has been fabricated using a 1.0-μm CMOS process that utilizes three-level metal and 480000 transistors on a 14×14-mm die 相似文献