共查询到18条相似文献,搜索用时 171 毫秒
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基于多相滤波的正交采样零中频数字化接收及QPSK高速解调的FPGA实现 总被引:1,自引:0,他引:1
针对高速率QPSK数据传输链系统,比较分析了数字中频接收与零中频接收的优、缺点,并提出了一种基于多相滤波的宽带中频正交采样数字零中频接收方案。基于FPGA对此数字零中频正交变换方案进行了实现和验证,同时,对一种全数字零中频QPSK信号的高速解调算法及其FPGA硬件实现进行了介绍。 相似文献
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为了尽可能多地用软件来实现通信接收机的处理功能,需要直接对中频信号进行采样,然后通过数字正交变换的方法得到同相和正交分量。首先对基于多相滤波法的数字正交变换原理进行分析,然后根据多抽样率信号处理理论,详细证明了内插时延滤波器能够用多相滤波器组中的子滤波器实现。 相似文献
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在软件无线电接收机中,普遍采用了中频数字化方案。中频接收机的输入信号为一个带通模拟信号,在进行信号解调前,必须先对其进行数字化正交处理,即将一个实信号变成两个正交数字序列。根据正交数字序列,可以方便地提取信号瞬时参数,同时在一定程度上能克服因衰落或多普勒频移等因素而导致的信号失真。根据A/D转换器在信号解调时所在位置和信号采样率的确定方式,对传统的基于Nyquist采样定理的模拟下变频法和基于中频带通采样的Hilbert滤波法、数字混频法和多相滤波法进行了研究。 相似文献
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针对目前成熟的模拟正交变换处理的信号大多属于窄带信号,而数字处理方法中的希尔伯特正交变换受到带宽限制,不能很好地应用于中频宽带信号的接收。提出应用多相滤波正交变换的方法实现中频频段宽带信号的接收前端处理。该方法可很好地解决宽带接收信号的数字下变频正交变换的问题,并且适合在FPGA上实现,应用于工程实时处理。 相似文献
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在机载雷达或电子战接收系统对大带宽数字中频信号的预处理过程中,针对传统并行多相滤波方式存在FPGA乘法器资源消耗过多的缺陷,提出对并行多相分解系数进行快速滤波算法构建,实现高速ADC采样率在4~8 GS/s之间的数字下变频处理。即先将高速中频采样信号解析为并行32支路,再通过数字混频及2倍抽取将基带复信号的并行度降至16,最后基于短卷积算法构建的16相快速滤波架构,实现对高采样率、大带宽信号的数字下变频预处理。通过基于并行16相快速滤波算法的宽带数字下变频设计与应用,将FPGA乘法器资源降至传统并行多相滤波方式的32%左右,大幅节省资源并提升单片FPGA对多通道、高采样率中频信号的预处理能力。 相似文献
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An all-digital architecture is presented for implementing the front-end signal-processing functions in a quadrature modulator and demodulator for high bit-rate digital radio applications. A pair of CMOS chips has been designed and submitted for fabrication in a 1.25-μm process and is expected to accommodate symbol rates up to 35 MBd. The modulator chip accepts a pair of 8-b in-phase and quadrature data streams and generates a bandlimited IF output with an excess bandwidth factor of 35%. The demodulator chip accepts a digitized IF input signal and generates a pair of filtered in-phase and quadrature baseband signals. The modulator and demodulator chips each incorporate 40-tap multiplierless FIR (finite-impulse response) square-root Nyquist matched filters, and the cascade of the two chips achieves a peak intersymbol interference distortion of -54 dB. The modulator chip can generate any arbitrary signal constellation within a rectangular grid of 256×256 points. Thus, the all-digital implementation results in a generic chip set suitable for a wide variety of high bit-rate digital modem designs using formats such as M -ary PSK and QAM 相似文献
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无人机着陆采用微波着陆系统(MLS)作导航系统具有很大优势,针对MLS信号高精度2DPSK解调和AM解调的要求,提出了一种基于FPGA的中频数字化解调方案;分析了改进科斯塔斯环法(Costas)实现载波同步及数字正交AM解调的原理;重点介绍了利用坐标旋转数字式计算机(CORDIC)算法实现数控振荡器(NCO)、鉴相、AM解调关键模块的设计过程。该算法采用流水线结构,只有加法和移位,资源消耗低、效率高、易于FPGA实现。应用VHDL硬件语言进行编程,采用同一电路完成了2DPSK解调和AM解调。仿真结果证明了方案的可行性和准确性,该方案可广泛应用于多种数字中频接收机,具有广阔的应用前景。 相似文献
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针对频移键控在通信系统应用中其调制解调技术在一定程度上直接影响通信系统的性能,提出了一种FSK数字解调方法,称作反正切差分解调.该方法基于正交反正切算法,正交信号直接相除消除了幅度调制成分.新的方法适用于窄带和宽带的FSK信号并适合于数字接收机.仿真结果表明,该技术能有效解调FSK信号,并适合于多种制式的FSK信号. 相似文献
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An improved digital intermediate frequency (IF) transmitter architecture for wide-band code-division multiple-access (W-CDMA) mobile terminals is proposed. Based on the heterodyne design but without requiring any off-chip IF filter, the transmitter enjoys the advantages of a homodyne architecture (such as circuit simplicity, low power consumption, and a high level of integration) while avoiding the performance problems associated with direct upconversion. By implementing the quadrature modulation in the digital domain and requiring only a single path of analog baseband circuits, inherently perfect I/Q matching and good error vector magnitude (EVM) performance can be achieved. The IF is chosen to be a quarter of the clock rate for a very simple and low-power digital modulator design. The difficulties of on-chip IF filtering were greatly alleviated by 1) performing a careful frequency planning and 2) employing a special-purpose digital-to-analog converter to produce high-order sin(x)/x rolloff. System-level simulation demonstrates that spurious-emission requirements are met with virtually no dedicated reconstruction filter circuits. This architecture takes full advantage of complimentary metal-oxide-semiconductor technology scaling by employing digital processing to ease analog complexities. 相似文献