对通孔消失机理的研究以及相应的解决方案

通孔消失是困扰半导体生产的难点之一.它与产品的生产合格率息息相关,正因为如此这一问题一直摆在业界工程师面前.由于这一问题的成因较多,故在分析和解决问题上存在诸多困扰.本文实验并分析了多种通孔消失的实效模型,结合先进的缺陷测试手段对其给出了不同的解决方案.此外,对相应的光刻胶也进行了研究并将缺陷密度与光刻胶的分辨率相联系,通过研究发现较低的分辨率的光刻胶的缺陷密度也相应较低.     

基于ITO玻璃基板的涂胶工艺研究

光刻胶涂布的厚度和均匀性直接影响细微光刻电路图形的精度,对电子产品的集成度和合格率有着极为重要的影响.基于ITO玻璃基板涂胶工艺实验,研究了影响涂胶厚度和涂胶均匀性的各种因素,包括光刻胶黏度、涂胶辊表面结构、胶辊压入量和涂胶速度等.针对几种常见的典型涂胶缺陷进行了研究分析,并制定了相应的解决对策.     

薄膜电路通孔结构光刻胶喷涂工艺

采用经稀释的光刻胶在喷胶机上对打孔的基片进行了雾化喷涂试验,在通孔结构表面实现了光刻胶的均匀涂覆。在同一基片上选取了十个通孔,采用扫面电镜对基片表面、通孔边缘及通孔侧壁中部和底部四处的光刻胶厚度进行了测量,得到的平均膜厚分别为10.2、8.8、6.1和5.3μm,各处厚度均匀性均小于±10%。     

TSV的工艺缺陷诊断与分析

随着3D集成封装的发展,硅通孔(TSV)成为实现3D堆叠中最有前景的技术之一.通过通孔和微凸点实现上下堆叠IC之间的垂直电连接,先进的TSV技术能够满足3D SIP异构集成、高速宽带、小尺寸及高性能等要求.然而,作为新型互连技术,TSV技术面临许多工艺上的困难和挑战,其可靠性没有得到充分的研究和保证.识别缺陷、分析失效机理对TSV三维集成器件的设计、生产和使用等各环节的优化和改进具有重要作用.对不同形状、不同深宽比的TSV通孔边界层进行了微观物理分析,对通孔形状、边界层均匀性等方面进行了评价,分析了各种工艺缺陷形成的物理机制以及可能带来的失效影响.最后根据其产生的原因提出了相应的改进措施.     

基于神经网络的硅通孔电热瞬态优化方法

针对三维集成微系统中高密度集成导致的热效应和复杂的多物理场耦合问题,提出了一种基于神经网络辅助人工蜂群的硅通孔电热瞬态优化方法,用于高效准确地分析三维微系统中硅通孔阵列的瞬态电热问题.利用有限元分析软件进行了电热耦合协同仿真,分析了设计参数(硅通孔半径、氧化物厚度、硅通孔间距)对硅通孔阵列中铜柱温度、微凸点温度等性能的影响.利用神经网络建立了设计参数与性能参数之间的映射关系.提出了一种具有性能约束的协同优化策略,并采用蜂群优化算法对设计参数进行优化.根据优化后的设计参数,有限元模拟结果与预测性能基本一致,结构的最高温度误差为2.6%.结论不仅证明了优化策略的可行性,且与传统有限元方法相比,该优化设计方法极大地缩短了仿真时间,简化了多场耦合中复杂数学分析.     

盘中孔板黑孔及焊点脱落改善探讨

随着线路的精细化发展,PCB布线密度越来越高,部分BGA板已取消通孔与焊球间的引线设计,为此须将BGA焊点与通孔重叠即制作成盘中孔工艺,以满足更高密度的布线需求。传统的盘中孔制作大多采用油墨或树脂塞孔再沉铜电镀的工艺生产,此工艺总是面临塞孔不饱满/黑孔/结合力不足等缺陷,给后续焊接带来极大的品质隐患。本文主要针对盘中孔黑孔及结合力不足进行了验证分析,并通过工艺优化进行了有效改善,大大提高了生产品质及一次性良率。     

一种用于先进封装的圆台硅通孔的刻蚀方法

在集成电路的制造阶段延续摩尔定律变得越发困难,而在封装阶段利用三维空间可以视作对摩尔定律的拓展。硅通孔是利用三维空间实现先进封装的常用技术手段,现有技术中对于应用于CMOS图像传感器件封装的圆台硅通孔,采用的是在顶部不断横向刻蚀的方式实现的,不利于封装密度的提高,且对于光刻设备的分辨率有一定的要求。针对现有技术中的问题,一种严格控制横向刻蚀尺寸（仅占原始特征尺寸的3%～12%）的圆台硅通孔刻蚀方法被研究探索出来。该方法通过调节下电极功率（≤30 W）,获得了侧壁角度可调（70°～88°）、通孔底部开口尺寸小于光刻定义特征尺寸的圆台硅通孔结构。这一方法有望向三维集成电路领域推广,有助于在封装阶段延续摩尔定律。     

光刻胶材料的研究进展

简单介绍了光刻胶的组成部分,综述了近年来国内外光刻胶成膜树脂合成、开发的研究进展,并根据不同曝光波长所需的不同光刻胶(包括紫外(UV)光刻胶、深紫外光刻胶、极紫外光刻胶等)进行了介绍。重点介绍了各光源下分子量和分子量分散指数对光致抗蚀剂的影响,并对国内外研究中通过不同聚合工艺制备的不同分子量光致抗蚀剂性能进行了评述,总结了近年来含有特定化学结构的光致抗蚀剂以及其制备工艺的研究进展。最后对国内外光刻胶的发展和应用进行了展望,指出进一步提高光刻胶的分辨率、改善其综合性能是今后的研究重点。     

结构化晶圆表面厚胶喷涂工艺

采用超声雾化喷涂技术,以AZ4620光刻胶为研究对象,以硅通孔(TSV)刻蚀后的硅片为基材,在12英寸(1英寸=2.54 cm)结构化晶圆表面喷涂光刻胶形成薄膜。分别研究了稀释质量比、超声功率、氮气体积流量、喷嘴与晶圆表面的间距、载台温度等工艺参数对TSV硅片表面喷涂质量的影响,最终通过优化过程工艺参数,得到表面胶颗粒细小、膜厚均匀性好、台阶覆盖率高的涂覆刻蚀片。实验结果表明,超声雾化喷涂法可以很好地应用于三维结构表面涂覆,克服了旋涂方法在三维结构应用中带来的缺陷,同时有效地提高了光刻胶的利用率,在集成电路(IC)制造和微电子机械系统(MEMS)工艺中有着广阔的应用前景。     

通孔波峰焊透锡不良问题研究

通孔波峰焊透锡不良问题是较严重的质量问题,危害到电子元器件与PCB联接的机械可靠性,会造成焊点锡裂甚至掉件,一直困扰着国内外的PCBA工艺工程师.一般情况下通孔的焊点最少时其透锡面凹进量不允许大于板厚的25%,当镀通孔连接到散热层或起散热作用的导体层,通孔的焊点最少时其透锡面凹进量不允许大于板厚的50%,否则称之为透锡不良.通过分析通孔波峰焊透锡原理,归纳总结抑制通孔波峰焊透锡不良问题发生的因素,并在此基础上探讨抑制该问题发生的技术方案.     

Suppression of pinhole defects in fullerene molecular electron beam resists

Molecular resists, such as fullerenes, are of significant interest for next generation lithographies. They utilize small carbon rich molecules, giving the potential for higher resolution and etch durability, together with lower line width roughness than conventional polymeric resists. The main problem with such materials has historically been low sensitivity, but with the successful implementation of chemical amplification schemes for several of the molecular resist families this is becoming less of a concern. Aside from sensitivity the other main obstacle has been the difficulty of preparing good quality thin films of non-polymeric materials. Here we present a study of pinhole defect density in fullerene films as a function of substrate cleanliness, post-application bake, and incorporation of chemical amplification components. Ultrathin (sub 30 nm) films of the previously studied fullerene resist MF03-01, and the polymeric resist PMMA were prepared on hydrogen terminated silicon by spin coating and the density of pinhole defects in the films was studied using atomic force microscopy. It was seen that pinhole density was strongly affected by the quality of the substrates, with the lowest densities found on films spun on freshly cleaned substrates. Aging of the film subsequent to spin coating was seen to have less effect than similar aging of the substrate prior to spin coating. Additionally, the use of a post-application bake significantly degraded the quality of the films. The addition of an epoxy crosslinker for chemical amplification was found to reduce defect density to very low levels.     

High gain AlInAs/GaInAs/InP HEMT's with individually groundedsource finger vias

High gain, millimeter wave AlInAs/GaInAs/InP HEMT's with individually grounded source finger vias have been fabricated for the first time using a high resolution Cl₂:HBr:BCl₃:Ar RIE process. For comparison of device characteristics at millimeter wave frequencies, HEMT's with end source vias were also fabricated on the same wafer. Fixtured RF characterization has revealed significant reduction in source inductance and reverse transmission in addition to higher gain on devices with individual source vias. These superior RF characteristics exhibited by the HEMT with individually grounded source finger vias illustrate the importance of the via technology for high performance InP-based millimeter wave system applications     

Design and Modeling of a Stopband-Enhanced EBG Structure Using Ground Surface Perturbation Lattice for Power/Ground Noise Suppression

Based on the ground surface perturbation concept, a novel stopband-enhanced electromagnetic-bandgap (EBG) structure has been proposed to suppress the power/ground noise on a three-layer package. This structure consists of a coplanar periodic pattern on the top layer, a ground plane on the third layer, and a ground surface perturbation lattice on the second layer with eight vias connecting to the ground plane. By designing the dimension and via numbers, the ground surface perturbation lattice can significantly enhance the stopband bandwidth. A generic 1-D circuit model is proposed for the three-layer EBG structure. The reason why the proposed structure can possess wider stopband will be explained. Several test samples are fabricated. The agreement of the stopband between the circuit model and measured results are good.      

Coupling of vias in electronic packaging and printed circuit board structures with finite ground plane

A full wave method is presented for modeling and analyzing multiple interactions among vertical vias in densely packaged integrated circuits and printed circuit board with ground plane of finite extent. In such structures, the TEM mode in the planar structure is excited and can propagate and cause interaction of waves among vias. Reflections will also occur at the edges of the finite ground plane. The electromagnetic analysis methodology is an extension of the previous methodology in analyzing multiple scattering among vias for infinite ground plane . The analysis is based upon the cylindrical wave mode expansion of the magnetic field Green's function, the Foldy-Lax multiple scattering formalism and utilizing the resonator modes of a circular cavity. The circular resonator modes are transformed into cylindrical waves onto the cylindrical via structures. Numerical results illustrate the physics of the underlying resonance scattering problems. We consider the cases of a) two coupled active vias of differential mode and b) two coupled vias of common mode. Results are also illustrated for ground plane resonance and the effects of shorting vias on such resonance. The effects of off-centering and the presence of idle vias are also illustrated.     

Electromigration characteristics of tungsten plug vias under pulseand bidirectional current stressing

Using Kelvin test structures, electromigration performances of selective CVD tungsten filled vias under DC, pulsed DC, and AC current signals have been studied. The metallization consists of Al-Cu/TiW multilevel metals. The via electromigration lifetime exhibits a current polarity dependence. The via AC lifetimes are found to be much longer (more than 1000×) than DC lifetimes under the same peak stressing current density. The via lifetimes under pulsed DC stress of 50% duty factor are twice the DC lifetimes at low-frequency regions (<200 Hz) and 4-5 times the DC lifetimes at high-frequency regions (>10 kHz). The results are in agreement with the vacancy relation model     

Equivalent circular defect model of real defect outlines in the ICmanufacturing process

For efficient yield prediction and inductive fault analysis of integrated circuits (IC's), it is usually assumed that defects related to photolithography have the shape of circular discs or squares. Real defects, however, exhibit a great variety of shapes. This paper presents an accurate model to characterize those real defects. The defect outline is used in this model to determine an equivalent circular defect such that the probability that the circular defect causes a fault is the same as the probability that the real defect causes a fault, so a norm is available which ran be used to determine the accuracy of a defect model, and thus estimate approximately the error that will be aroused in the prediction of fault probability of a pattern by using circular defect model. Finally, the new model is illustrated with the real defect outlines obtained by optical inspection     

A through-wafer interconnect in silicon for RFICs

In order to minimize ground inductance in RFICs, we have developed a high-aspect ratio, through-wafer interconnect (or substrate via) in silicon that features a silicon nitride barrier liner and completely filled Cu core. We have fabricated vias with a nominal aspect ratio of 30 and verified the integrity of the insulating liner in vias with an aspect ratio of eight. The inductance of vias with nominal aspect ratios between three and 30 approach the theoretically expected values. This interconnect technology was exploited in a novel Faraday cage structure for substrate crosstalk suppression in system-on-chip applications. The isolation structure consists of a ring of grounded vias that surrounds sensitive or noisy portions of a chip. This Faraday cage structure has shown noise suppression of 30 dB at 10 GHz and 16 dB at 50 GHz at a distance of 100 /spl mu/m when compared to the reference structure.     

Designing a 3-D FPGA: Switch Box Architecture and Thermal Issues

Three-dimensional (3-D) integration is an attractive technology to reduce wirelengths in a field-programmable gate array (FPGA). However, it suffers from two problems: one, the inter-layer vias are limited in number, and second, the increased power density leads to high junction temperatures. In this paper, we tackle the first problem by designing switch boxes that maximize the use of the vias. Compared to the previously used subset switch box, our best switch box reduces the number of vias by about 49% and area-delay product by about 9%. For the second problem, we utilize the difference in power densities between CLBs and some of the hard blocks in modern FPGAs to distribute the power more uniformly across the FPGA. The peak temperature in a two-layer FPGA reduces by about 16degC after our change.     

基于圆对称性的离焦模糊图像还原方法

针对离焦模糊图像,圆盘离焦模型和高斯离焦模型的还原效果并不理想,提出基于圆对称性的离焦模糊图像还原算法。通过刃边函数估算模糊半径,利用信噪比还原图像,进而计算图像的信号功率谱。提出改进的DCT分块加权清晰度评价函数,对DCT系数作指数加权优化,并根据圆对称性模型检测出的多个模糊半径还原出多个图像,并筛选出最清晰图像作为还原结果。实验结果显示,与传统的还原方法相比,该方法提高了还原图像的清晰度和分辨率。