异质栅MOSFET热载流子效应的研究

异质栅MOSFET器件的栅极由具有不同功函数的两种材料拼接而成,能够提高载流子输运速度、抑制阈值电压漂移等.文中比较了异质栅MOSFET和常规MOSFET的热载流子退化特性.通过使用器件数值模拟软件MEDICI,对能有效监测热载流子效应的参数,例如电场、衬底电流和栅电流等参数进行仿真.将仿真结果与常规MOSFET对比,从抑制热载流子效应方面验证了新结构器件的高性能.     

纳米级MOSFET器件模拟的载流子输运模型

随着半导体微细加工技术的发展,预计硅SOC的集成度可达万亿个晶体管,单个晶体管的尺寸将达到10nm范围内。因此从理论上研究纳米尺寸器件的性能和特性对发展超大规模集成电路尤为重要。综述了纳米级MOSFET器件数值模拟的量子模型,以及在该模型下用到的几种载流子输运模型,并结合模拟结果对这一模型作了评价。     

MOSFET中载流子能量输运计算机辅助分析

本文提出了能量输运问题的二维MOSFET的数值模拟,其中计入了产生、复合以及载流子的温度梯度对器件特性的影响;还提出了改进的迁移率模型。对微米和亚微米MOSFET样品的模拟结果表明,本文所提出的模型和方法与实验符合得很好。     

6H-SiC肖特基源漏n沟MOSFET的数值-解析模型

分析了6H-SiC肖特基源漏MOSFET的电流输运机制,并建立了数值-解析模型.模型正确地计入了隧道电流和势垒降低的影响,能准确反映器件的特性.模拟结果显示,源极肖特基的势垒高度是影响器件特性的主要因素,随着温度升高,器件的特性将变得更好.     

6H-SiC肖特基源漏n沟MOSFET的数值-解析模型

分析了6H-SiC肖特基源漏MOSFET的电流输运机制,并建立了数值-解析模型.模型正确地计入了隧道电流和势垒降低的影响,能准确反映器件的特性.模拟结果显示,源极肖特基的势垒高度是影响器件特性的主要因素,随着温度升高,器件的特性将变得更好.     

6H-SiC肖特基源漏n沟MOSFET的数值-解析模型

分析了6 H- Si C肖特基源漏MOSFET的电流输运机制,并建立了数值-解析模型.模型正确地计入了隧道电流和势垒降低的影响,能准确反映器件的特性.模拟结果显示,源极肖特基的势垒高度是影响器件特性的主要因素,随着温度升高,器件的特性将变得更好.     

全耗尽异质栅单Halo SOI MOSFET二维模型

为了抑制深亚微米SOI MOSFET的短沟道效应,并提高电流驱动能力,提出了异质栅单Halo SOI MOSFET器件结构,其栅极由具有不同功函数的两种材料拼接而成,并在沟道源端一侧引入Halo技术.采用分区的抛物线电势近似法和通用边界条件求解二维Poisson方程,为新结构器件建立了全耗尽条件下的表面势及阈值电压二维解析模型.对新结构器件与常规SOI MOSFET性能进行了对比研究.结果表明,新结构器件能有效抑制阈值电压漂移、热载流子效应和漏致势垒降低效应,并显著提高载流子通过沟道的输运速度.解析模型与器件数值模拟软件MEDICI所得结果高度吻合.     

CMOS磁敏器件的两维数值模拟

本文在IBM-PC计算机上,数值模拟了线性区CMOS磁敏器件,即对垂直于器件表面磁场敏感的劈裂漏极MOSFET,并将其推广到饱和区。针对器件的矩形结构,采用非均匀矩形网格有限差分方法求解了在磁场存在下载流子的输运方程,给出了电压分布,且分析了灵敏度和线性度。计算结果与实验相符。     

双栅和环栅MOSFET中短沟效应引起的阈值电压下降

基于电荷分享原理 ,推导了双栅和环栅 MOSFET短沟效应引起的阈值电压下降 ,分析了衬底掺杂浓度、栅氧化层厚度及硅膜厚度等因素对阈值电压下降的影响 ,并用数值模拟验证了理论结果 .这些研究结果对进一步开展纳米 CMOS新器件的研究有很好的参考价值和实际意义     

一种基于载流子的双栅MOSFET解析模型

提出一种全新的基于载流子求解的双栅MOSFET解析模型.针对无掺杂对称双栅MOSFET结构,该模型由求解泊松方程的载流子分布和Pao-Sah电流形式直接发展而来.发展的解析模型完全基于MOSFET的基本器件物理进行直接推导,结果覆盖了双栅MOSFET所有的工作区:从亚阈到强反型和从线性到饱和区,不需要任何额外假设和拟合参数.模型的预言结果被2D数值模拟很好地验证,表明该解析模型是一个理想的双栅MOSFET建模架构.     

高温微电子学—Ⅰ：硅器件的高温特性研究

本文详细介绍了硅器件的高温理论以及制作的进展,分析了MOSFET的高温特性和失效模式,指出了改善MOSFET高温性能和提高上限温度的方法。     

Novel high-voltage silicon-on-insulator MOSFETs

Novel lateral RESURF high voltage SOI MOSFETs capable of withstanding up to 400V are presented in this paper. The design optimization, fabrication and experimental results obtained on these devices are also presented. The devices are implementable using a CMOS-SOI compatible process.     

High-quality deposited gate oxide MOSFET's and the importance ofsurface preparation

The fabrication and electrical characteristics of MOSFETs incorporating thin gate oxides deposited by a modified plasma-enhanced chemical-vapor-deposition (PECVD) process are reported. The gate oxide deposition and all subsequent steps were carried out at or below 400°C. These results represent the first demonstration of near-thermal-gate oxide quality. MOSFETs fabricated using a low-temperature PECVD gate oxide process without requiring a high-temperature anneal. The ultimate performance of the deposited oxide devices is shown to be critically dependent on the degree of process induced microroughness of the starting silicon surface. Low-temperature effective mobility measurements are used to compare inversion-layer scattering mechanisms in these devices     

采用局域注氧技术制备的新型DSOI场效应晶体管的热特性

通过局域注氧工艺 ,在同一管芯上制作了 DSOI、体硅和 SOI三种结构的器件 .通过测量和模拟比较了这三种结构器件的热特性 .模拟和测量的结果证明 DSOI器件与 SOI器件相比 ,具有衬底热阻较低的优点 ,因而 DSOI器件在保持 SOI器件电学特性优势的同时消除了 SOI器件严重的自热效应 .DSOI器件的衬底热阻和体硅器件非常接近 ,并且在进入到深亚微米领域以后能够继续保持这一优势 .     

Impact of gate-leakage currents on CMOS circuit performance

Ultra-thin gate dielectrics are exploited in fabrication of MOSFETs featuring channel lengths in the decananometer range: according to the ITRS oxide thickness in the order of 1 nm will be used in 2005 for ultra-short channel CMOS. For such aggressively scaled devices, gate-leakage currents represent a critical issue. In this paper, a study on the impact of direct-tunneling (DT) current on the performance of a wide variety of CMOS circuits is presented. The approach relies on a mixed-mode simulation approach, which allows for predicting the correlation of major performance indices with oxide thickness.     

采用局域注氧技术制备的新型DSOI场效应晶体管的热特性

通过局域注氧工艺,在同一管芯上制作了DSOI、体硅和SOI三种结构的器件.通过测量和模拟比较了这三种结构器件的热特性.模拟和测量的结果证明DSOI器件与SOI器件相比,具有衬底热阻较低的优点,因而DSOI器件在保持SOI器件电学特性优势的同时消除了SOI器件严重的自热效应.DSOI器件的衬底热阻和体硅器件非常接近,并且在进入到深亚微米领域以后能够继续保持这一优势.     

High-mobility strained SiGe-on-insulator pMOSFETs with Ge-rich surface channels fabricated by local condensation technique

A new approach to form strained SiGe-on-insulator (SGOI) channel transistors, allowing fabrication of MOSFETs with very high Ge fraction in selected areas on a silicon-on-insulator substrate, is demonstrated. This method consists of epitaxial growth of an SiGe layer with a low Ge fraction and local oxidation processes. An obtained SGOI pMOSFET with a Ge fraction of 0.93 exhibits up to a tenfold enhancement in mobility. It is also found that MOSFETs having strained SGOI channels with thicknesses of less than 5 nm exhibit hole-mobility enhancement factors of over two. These results indicate that the local SGOI channels fabricated by the proposed technique are promising for implementation of high-mobility SiGe or Ge-channel MOSFETs in system-on-chip (SoC) devices.     

Seamless On-Wafer Integration of Si(100) MOSFETs and GaN HEMTs

The first on-wafer integration of Si(100) MOSFETs and AlGaN/GaN high electron mobility transistors (HEMTs) is demonstrated. To enable a fully Si-compatible process, we fabricated a novel Si(100)-GaN-Si(100) virtual substrate through a wafer bonding and etch-back technique. The high thermal stability of nitride semiconductors allowed the fabrication of Si MOSFETs on this substrate without degrading the performance of the GaN epilayers. After the Si devices were fabricated, the nitride epilayer is exposed, and the nitride transistors are processed. By using this technology, GaN and Si devices separated by less than 5 mum from each other have been fabricated, which is suitable for building future heterogeneous integrated circuits.