Ag/Bi4Ti3O12栅铁电场效应管ID-VG特性双曲模型

在理论分析的基础上,结合铁电材料特性及实验数据,提出了Ag/Bi4Ti3O12栅n沟道铁电场效应晶体管转换(ID-VG)特性的双曲模型并进行了数值模拟。该模型不但与阈值电压、沟道饱和电流等器件参数相关而且充分反映了剩余极化、矫顽电压等铁电栅介质极化特性对器件ID-VG特性的影响。结果表明:模拟曲线与实验曲线基本一致,能较好地模拟和描述铁电场效应晶体管的ID-VG特性。     

铁电负电容可测试性的仿真研究

铁电材料具有负电容特性,可应用于新一代超低亚阈值摆幅晶体管中。由于铁电负电容具有准静态特性,在实际测试中,难以直接观测到单独铁电电容的负电容现象。基于“Ginzburg-Landau”模型,采用TCAD软件,构建了紧凑的HfO₂铁电电容结构,并通过仿真获得了匹配的RC电路参数,验证了负电容特性。同时,仿真研究了外加电压幅值与串联电阻阻值对铁电电容负电容效应可测试性的影响。     

铁电负电容场效应晶体管器件的研究

铁电负电容场效应晶体管作为一种新型半导体器件,利用铁电材料的负电容效应可使晶体管的亚阈值摆幅突破理论极限值60 mV/dec,是未来低功耗晶体管领域最具有前途的器件之一。该文研究并建立了铁电负电容场效应晶体管的器件模型,采用Matlab软件对负电容场效应晶体管的器件特性进行了研究分析,获得了亚阈值摆幅为33.917 6 mV/dec的负电容场效应晶体管的器件结构,探究了铁电层厚度、等效栅氧化层厚度及不同铁电材料对负电容场效应晶体管亚阈值摆幅的影响。     

SOI铁电负电容晶体管亚阈值特性研究

随着微电子技术进入纳米领域,功耗成为制约技术发展的主要因素,因此,低功耗器件成为半导体器件领域的研究热点。负电容场效应晶体管基于铁电材料的负电容效应可有效地降低器件的亚阈值摆幅,从而降低器件的功耗。该文设计了一种基于绝缘体上硅(SOI)结构的铁电负电容场效应晶体管,利用TCAD Sentaurus仿真工具对负电容晶体管进行仿真研究,得到了亚阈值摆幅为30.931 mV/dec的负电容场效应晶体管的器件结构和参数。最后仿真研究了铁电层厚度、等效栅氧化层厚度对负电容场效应晶体管亚阈值特性的影响。     

高P_r/低P_r栅FFET漏极电流与铁电材料特性的关系

分析了对铁电场效应晶体管漏极电流特性有影响的铁电材料参数,设计了具有单层和双层栅介质结构的铁电场效应晶体管,并进行了仿真研究。仿真结果表明:具有高Pr/低Pr栅介质结构的铁电场效应晶体管在饱和极化后,其极化前后输出漏极电流差最大,有利于存储信号的分辨,提高电路的效率。通过改变该结构中低Pr层的Pr,Ec等铁电材料参数,发现在3~4V间饱和极化,该结构的铁电场效应晶体管的漏极电流输出特性比较稳定,减小了对材料、工艺、Ps/Pr及Ec的依赖性和敏感性,具有易于制造和便于电路设计的优点。     

单电子晶体管的I-V特性数学模型及逻辑应用

基于正统单电子理论，提出了单电子晶体管的I-V特性数学算法改进模型。该模型的优点是：考虑了背景电荷的影响，可由实际物理参数直接获得，支持双栅极工作，便于逻辑电路的分析。研究了背景电荷和各物理参数对I-V特性及跨导的影响，讨论了双栅极单电子晶体管的逻辑应用：简化了“异或”逻辑电路，改进了二叉判别图电路的逻辑单元。     

铁电晶体管存储器的读出电路设计

通过对铁电晶体管电学特性分析,提出了铁电晶体管的仿真模型,并设计了一种新型单管(1T)结构的读出电路。通过此模型进行了仿真验证,并与传统双管(2T)结构的电流放大读出电路的仿真结果进行对比,结果表明,新型1T结构读出电路在读出速度,可靠性及电路结构大小等方面均有提高。     

单电子晶体管的Ⅰ-Ⅴ特性数学模型及逻辑应用

基于正统单电子理论,提出了单电子晶体管的Ⅰ-Ⅴ特性数学算法改进模型.该模型的优点是考虑了背景电荷的影响,可由实际物理参数直接获得,支持双栅极工作,便于逻辑电路的分析.研究了背景电荷和各物理参数对Ⅰ-Ⅴ特性及跨导的影响,讨论了双栅极单电子晶体管的逻辑应用简化了"异或"逻辑电路,改进了二叉判别图电路的逻辑单元.     

非线性双极晶体管模型的研究

本文对非线性双极晶体管的模型进行了研究,非线性晶体管模型对微波CAD和无线电系统仿真都是非常关键的。本文采用等效电路模拟非线性双极晶体管,给出了等效电路模型及模型参数,并用这些参数描述了非线性双极晶体管工作过程中的直流特性和各种效应:基区宽度调制效应、电荷储存效应;正向电流增益(BF)随电流的变化以及温度的影响等。为准确地建立不同用途双极晶体管的模型提供了依据。     

SiGe HBT的Mextram 504模型温度参数提取与模型改进

针对IMEC 0.13μm准自对准SiGe BiCMOS工艺制成的基区Ge组分二阶分布结构SiGe异质结双极晶体管,在25～125℃温度范围内,对其进行了包括Early电压,Gummel图形等在内的完整双极晶体管特性曲线测量,提取了该器件在25～125℃范围内的温度可变Mextram 504模型参数.在此基础上,为Mextram 504模型对0.13μm基区Ge组分二阶分布SiGe异质结双极晶体管探索了完整的模型提取方案.提出了对Mextram 504模型温度参数提取方法的改进,优化了提取流程.对SiGe异质结双极晶体管雪崩电流受温度影响的特性进行了讨论,为Mextram模型提出了雪崩外延层的有效厚度的温度变化经验公式和新的雪崩电流温度变化参数,提高了Mextram模型对不同温度下SiGe双极型晶体管进行模拟仿真的精确度.     

Operation of single transistor type ferroelectric random access memory

Verification was sought for the memory operation of a single transistor type ferroelectric random access memory (1T type FeRAM) with a circuit model for a memory cell transistor combined with a precharged capacitive decoupling sensing scheme. The wiring scheme of the 1T type FeRAM array was also proposed based on the operation of the fabricated memory cell transistor. As a result, the memory operation of 1T type FeRAM was confirmed at a low current level with high sensing speed and no reference cell, and the design and verification of the full chip were achieved.     

Why is nonvolatile ferroelectric memory field-effect transistorstill elusive?

In principle, a memory field-effect transistor (FET) based on the metal-ferroelectric-semiconductor gate stack could be the building block of an ideal memory technology that offers random access, high speed, low power, high density and nonvolatility. In practice, however, so far none of the reported ferroelectric memory transistors has achieved a memory retention time of more than a few days, a far cry from the ten-year retention requirement for a nonvolatile memory device. This work will examine two major causes of the short retention (assuming no significant mobile ionic charge motion in the ferroelectric film): 1) depolarization field and 2) finite gate leakage current. A possible solution to the memory retention problem will be suggested, which involves the growth of single-crystal, single domain ferroelectric on Si. The use of the ferroelectric memory transistor as a capacitor-less DRAM cell will also be proposed     

铁电存储器的研究进展

介绍了铁电存储器的存储原理,同时对两种铁电存储器(铁电随机存取存储器和铁电场效应晶体管存储器)的研究进展、当前存在的问题以及我国目前在这一领域的研究现状进行了简单介绍,并对今后的技术发展进行了展望。     

Memory performance and retention of an all-organic ferroelectric-like memory transistor

We have built a nonvolatile memory field-effect transistor (FET)-based on organic compounds. The gate-insulating polymer features ferroelectric-like characteristics when spun from solution into an amorphous phase. Thus, the memory transistor is built using techniques developed for organic transistors without requiring high temperature annealing steps. The memory exhibits channel resistance modulations and retention times close in performance to inorganic ferroelectric FETs (FEFETs), yet at a fraction of the cost.     

High-density chain ferroelectric random access memory (chain FRAM)

A new chain ferroelectric random access memory-a chain FRAM-has been proposed. A memory cell consists of parallel connection of one transistor and one ferroelectric capacitor, and one memory cell block consists of plural memory cells connected in series and a block selecting transistor. This configuration realizes the smallest 4 F² size memory cell using the planar transistor so far reported, and random access. The chip size of the proposed chain FRAM can be reduced to 63% of that of the conventional FRAM when 16 cells are connected in series. The fast nondriven half-V_dd cell-plate scheme, as well as the driven cell-plate scheme, are applicable to the chain FRAM without polarization switching during the standby cycle thanks to short-circuiting ferroelectric capacitors. It results in fast access time of 45 ns and cycle time of 70 ns without refresh operation     

A quasi-matrix ferroelectric memory for future silicon storage

We proposed a new quasi-matrix ferroelectric memory for use in future silicon-storage media. The memory unit consists of multiple ferroelectric capacitors and one access transistor. Each capacitor stores 1 bit of data, and the access transistor is shared by several capacitors. Compared with conventional crosspoint matrix type FeRAMs, which cause a signal degradation by read/write disturbance, this memory limits the disturbing frequency to an acceptable level by accessing the memory unit as a whole. Crosstalk noise was also minimized by applying a unique access scheme. This memory has a scalability by adopting built-in sense circuits, and enables an extremely high packing density with three-dimensional multistacking structures of memory cells.     

Designing Multi‐Level Resistance States in Graphene Ferroelectric Transistors

Conventional memory elements code information in the Boolean “0” and “1” form. Devices that exceed bistability in their resistance are useful as memory for future data storage due to their enhanced memory capacity, and are also a necessity for contemporary applications such as neuromorphic computing. Here, with the aid of an experimentally validated device model, design rules are outlined and more than two stable resistance states in a graphene ferroelectric field‐effect transistor are experimentally demonstrated. The design methodology can be extrapolated for on‐demand introduction of multiple resistance states in ferroelectric transistors for applications both in data storage and neuromorphic computing.     

Voltage-readable nonvolatile memory cell with programmable ferroelectric multistates in organic inverter configuration

We demonstrate a voltage-readable nonvolatile memory cell with programmable ferroelectric multistates in an organic inverter configuration. The intermediate memory states of a ferroelectric gate insulator, varying with the magnitude of the programming voltage, allow the multilevels of the drain current at zero gate-source voltage in a ferroelectric organic field-effect transistor (OFET). The current output from the ferroelectric memory is directly converted into the voltage-readable output in a zero-gate load inverter configuration where both a driving paraelectric OFET having a paraelectric buffer layer and a load ferroelectric OFET are monolithically integrated in a single substrate. The multilevel voltage-readable output characteristics are obtained from the ferroelectric multistates as a function of the programming voltage.     

A Solar Transistor and Photoferroelectric Memory

This study presents a new self‐powered electronic transistor concept “the solar transistor.” The transistor effect is enabled by the functional integration of a ferroelectric‐oxide thin film and an organic bulk heterojunction. The organic heterojunction efficiently harvests photon energy and splits photogenerated excitons into free electron and holes, and the ferroelectric film acts as a switchable electron transport layer with tuneable conduction band offsets that depend on its polarization state. This results in the device photoconductivity modulation. All this (i.e., carrier extraction and poling) is achieved with only two sandwiched electrodes and therefore, with the role of the gating electrode being taken by light. The two‐terminal solar‐powered phototransistor (or solaristor) thus has the added advantages of a compact photodiode architecture in addition to the nonvolatile functionality of a ferroelectric memory that is written by voltage and nondestructively read by light.