SOS膜生长及性能的改善

一 引言 SOS器件具有速度快,功耗低,集成密度高,抗辐射等优点。经过较长时间的研制,最近几年有了很大的进展。已从实验室进入了市场,并日益显示出它的优越性。为越来越多的器件制作者所注目和研制。 SOS器件制作的关键,在于制备高质量的SOS外延膜。首先,它受硅和衬底之间晶格匹配、热膨胀系数差别,以及衬底     

外延迁移技术制作用于光电子单片集成的Si上GaAs／GaAlAsDHLED

描述了在国内首次采用外延迁移技术研制适合于制作光电子集成电路的硅上硬化镓双异质结发光二极管的工艺过程及实验结果。发光器件是在外延迁移以后流片制作的，克服了光子器件的对准问题，可与电子器件大规模集成。     

CMOS/SOS器件长期可靠性试验

用本所研制的CMOS/SOS器件作了两项试验,即CMOS/SOS4012长期可靠性试验和不同版图设计、不同器件工艺研制的CMOS/SOS长期可靠性对比试验。试验结果表明:不同版图设计和器件工艺对CMOS/SOS器件可靠性有较大的影响;改进了版图和器件工艺研制的CMOS/SOS器件达到了较高的可靠性;不同栅介质结构的CMOS/SOS器件在高温加电运行中,阈值电压的变化是不同的。     

CdS红外λ／4波片

根据CO_2相干激光雷达系统的要求,用CdS单晶制作了10.6μm的四分之一波片,并建立了精密测试系统,对所研制的波片进行了性能测试。     

1T02取向白宝石的位错显示

1 引言 随着宇航技术、空间技术、核技术的发展,要求集成电路必须有较好的抗辐射性能。体硅器件通过精心的设计,严格的制造工艺,虽然能够增强器件的抗辐射能力,但在航天技术和卫星工程高技术领域中仍不能满足要求。而宝石上外延薄硅层,即SOS,作成的CMOS集成电路,可以穿通扩散直到硅-宝石界面,大面积的水平扩散结被小面积的垂直扩散结所代替,结区面积可以减少两个数量级。加之半导体材料和金属接触是介质隔离的,因而寄生电容最小。应用SOS做成的集成电路具有它独有的特点:功耗低,速度高,特别是它抗辐射能力强的性能是其他集成电路望尘莫及。目前,国际上公认SOS电路是能够进入大规模集成电路的四种电路之一。     

硅双结型色敏器件蓝紫响应度的研究与改善

尝试选择不同的衬底材料、不同的工艺条件,以及合理的结构,来改善硅双结色敏器件的蓝紫光响应,并在此基础上制作了蓝紫响应较好的器件。通过测试与分析,得出采用单晶衬底材料、深结较浅工艺的N PN型器件蓝紫响应度较好的结论。     

脉冲压缩开关DBD研究

延迟击穿器件(DBD)是一种新型的半导体导通式开关,它具有重复工作频率高、体积小、重量轻、稳定性好等优点。利用此种开关对基于半导体断路开关(sem iconductoropening switches,SOS)开关输出的高重复频率的脉冲波形进行压缩,可制作出高重复频率的超宽带脉冲源。介绍了DBD开关的基本工作原理和研制结果,给出了在相同测试条件下,与国外同类开关的测试结果对比波形,结果表明,研制的DBD开关和国外开关的指标基本相同,其中某些指标优于国外开关水平。     

AlGaInP/GaAs HBT发射结空间电荷区复合电流的研究

本文采用深能级瞬态谱（DLTS）方法直接对Al0.3Ga0.22In0.48P／GaAs异质结双极型晶体管（HBT）的发射结（N－P+结）进行了测试，得到了N型AlGaInP发射区中的深能级的位置、俘获截面以及缺陷浓度．利用这些数据通过单一能级复合的Shockley－Read-Hall公式，计算了发射结空间电荷区（SCR）中的复合电流，探讨了深能级中心对HBT器件特性的影响．本文的理论分析方法可为研制高性能HBT器件所需的材料质量提高提供参考依据．     

兰宝石上外延硅工艺及其应用

本文着重于SOS材料制备及提高其性能的工艺.并用它研制成硅-兰宝石半导体压力传感器及LC4023和LC4027辐射加固的CMOS/SOS集成电路.其主要性能为国内领先,达到八十年代的国际同类产品的水平,并已用于工业部门.     

5000小时室温连续激射GaAs/GaAlAs双异质结激光器

简述了所研制的质子轰击条形双异质结激光器的结构和工艺。在直流正向电流下对激光器性能进行了测试分析,大部分激光器的阈电流I为50～150毫安,微分量子效率η_d为30～70％,部分激光器得     

薄膜亚微米CMOS／SOS工艺的开发及其器件的研制

本文较为详细地介绍了薄膜亚微米ＣＭＯＳ／ＳＯＳ工艺技术的开发过程，薄膜亚微米ＣＭＯＳ／ＳＯＳ工艺主要包括双固相外延，双层胶光刻形成亚微米细线条硅栅、Ｈ２－Ｏ２合成氧化薄栅氧化层以及快速退火等新的工艺技术，利用这套工艺成功地研制出了高性能薄膜来微米ＣＭＯＳ／ＳＯＳ器件和门延迟时间仅为１７７ｐｓ的１９级ＣＭＯＳ／ＳＯＳ环形振荡器，与厚膜器件相比，薄膜全耗尺器件和电路的性能得到了明显的提高。     

IMMA applications to ion implantation in silicon-on-sapphire

Application of ion-microprobe mass analysis (IMMA) technique for the characterization of the silicon-on-sapphire (SOS) epitaxial layers and ion implantation in SOS axe described. A significantly high level of aluminum and oxygen concentration was observed in the thin (O.5-µm) epitaxial film. Ion-implant profiles of boron and phosphorus before and after high-temperature activation and oxidation procedures commonly used in SOS fabrication process are characterized and correlated to SUPREM calculations, spreading resistance, and resistivity measurements.     

Short-channel C-MOS/SOS technology

Design, fabrication, and characterization of Si-gate short-channel C-MOS/SOS devices with channel length ranging from 1 to 3 µm are presented. Basic device parameters and their interrelations are discussed and illustrated in detail. Extremely-high-speed and low-power capability has been demonstrated for short-channel devices operating from a 5-V supply voltage. The process reproducibility and circuit performance point to the suitability of short-channel C-MOS/SOS technology for VLSI applications.     

4-µm LSI on SOS using coplanar-II process

SOS Si-gate 4-µm NMOS devices using a coplanar process (Coplanar-II process) have been investigated for the purpose of improving thé power-delay product and SOS LSI reliability. The gate breakdown field is improved by more than a factor of two (8.7 MV/cm) over that of transistors fabricated by a conventional SOS process. Two types of anomalous drain leakage currents which flow along the edge of the silicon island formed by using the conventional SOS process are suppressed. A typical drain leakage current is7 times 10^{-11}A/8 µm. The typical values of speed and power-delay product are 0.70 ns and 0.21 pJ for 4-µm channel length devices and 0.57 ns and 0.17 pJ for 3-µm devices. These values are 1.6 times faster than that of MOS/bulk due to a lack of stray capacitance in MOS/SOS. The temperature dependence of the delay time in NMOS/SOS E/D devices can be minimized by choosing the load transistor threshold voltage (VTD) to be -2.1 V. This is attributed to the higher temperature dependence of VTDthan that of MOS/bulk. The Coplanar-II process with Si-gate 4-µm NMOS/SOS is successfully applied to the fabrication of a 1300-gate LSI, RF0 (Register File 0). The circuitry has a unique register port which can be addressed from two independent ports simultaneously. In order to obtain higher speed and lower power, four kinds of threshold voltages are used. The circuits give rise to stable operation without any timing pulse such as a precharge and a higher internal access time of 25 ns in RF0, which consists of 256-bit memory and peripheral control circuit.     

16K CMOS/SOS asynchronous static RAM

A new CMOS/SOS `buried-contact' process allows fabrication of dense static memory cells. The technology is applied in a 16K RAM with 1150 /spl mu/m/SUP 2/ (1.78 mil/SUP 2/) cells based on 5 /spl mu/m design rules.     

Study of the Structural Properties of Silicon-on-Sapphire Layers in Hydride-Chloride Vapor-Phase Epitaxy

The surface of silicon-on-sapphire (SOS) epitaxial layers is studied by atomic-force microscopy and the UV (ultraviolet) scattering method. X-Ray diffraction analysis of the SOS layers is carried out. The silicon-sapphire transition region is studied by the photovoltage method. The problem of the accumulation of by-products formed during the synthesis of silicon from monosilane is considered and experimentally confirmed. It is found that the addition of chlorine-containing reagents to the epitaxial process makes it possible to exclude the influence exerted by these products on the growing layer and also to modify the surface microprofile. Analysis of the surface and structure of the SOS layers demonstrates that film growth occurs by the Stranski–Krastanov mechanism. It is shown that a combined method in which a 30–60-nm-thick SOS layer is preliminarily grown from pure SiH₄ and then a layer is additionally grown at a 2SiH₄:1SiC1₄ ratio of gas component flow rates is the most preferable method for the fabrication of SOS structures with layer thicknesses of 300 nm and more.     

Submicrometer polysilicon gate CMOS/SOS technology

A process is described for the fabrication of CMOS/SOS submicrometer devices and integrated circuits. The process utilizes the lateral diffusion of boron into polycrystalline silicon and a subsequent anisotropic etchant to define the narrow poly gates. Devices with channel lengths as small as 0.3 µm have been fabricated and characterized. Both avalanche and tunnel injection of carriers into the gate dielectric have been measured and both can have an impact on the limit of voltage operation. At present, these mechanisms appear to place an upper limit of about 8 V on the operating voltage of dynamic circuits containing 0.5- µm channel length devices. The propagation delay of 0.5-µm channel length CMOS/SOS inverters is about 200 ps at 5 V and dynamic binary counters will operate with a maximum input frequency of 550 MHz and 8 V while dissipating 130 mW.     

On the compatibility of X-ray lithography and SOS device fabrication

If X-ray lithography is applied to the fabrication of silicon-on-sapphire devices (SOS), the average radiation absorbed dose in the sapphire at the silicon-sapphire interface is in excess of ten Mrad. Recent experiments indicate that the resulting radiation damage may not be easily annealed. These results suggest that X-ray lithography and SOS may not be compatible technologies.     

The subthreshold behavior of SOS MOST's

MOST subthreshold behavior is of importance in many modern dynamic and very-low-power circuits. SOS MOST's exhibit quite generally a lower transconductance than bulk Si MOST's. Comparison between SOS and bulk Si MOST's is made on the basis of a simple model in the weak inversion region. Experiments with n-and p-channel SOS MOST's fabricated with epi Si layer thicknesses ranging from 0.1 to 3 µm confirm the predicted decrease of transconductance in weak inversion with decreasing thickness. Quantitative agreement between model and experience is obtained if a ∼350-Å thick nonconductive Si layer near the Si-sapphire interface is assumed. A transconductance jump observed for epi Si thickness equal to the surface maximum depletion width has not yet been explained. Further experiments including fabrication process, back-gate voltage measurements, and device dimensions were performed in order to investigate the low-transconductance origin. It is concluded that the only relevant parameters are the epi Si layer thickness and the high density of fast states at the Si-sapphire interface.     

A CMOS/SOS gate array with a new customization technique of cutting

A 770-gate single-level metallized Si-gate CMOS/SOS gate array has been fabricated using a new customization technique: cutting pre-defined n⁺epitaxial silicon lines. Simple process and quick turnaround time are both realized. Total fabrication steps are reduced to 53 percent of those of the double-level metallized CMOS/bulk gate array because of a simplified CMOS/SOS process and only three-mask customization. Customization steps are also reduced to 55 percent. High packing density and high switching speed comparable to those of the double-level metallized CMOS/bulk gate array are also obtained. The number of the silicon wiring channels of the conventional single-level metallized gate array is reduced by a factor of two by the cutting technique. This value corresponds to a 24 percent decrease in the chip area. Even with a conservative 4-µm technology, gate delay of 0.8 ns is obtained at the power-supply voltage VDDof 5 V. Up to 25 MHz operations are verified for a shift register. On this gate array a control unit for a CCD camera is fabricated; 95 percent of the internal basic cells are utilized. The active power dissipation of this unit is 1.0 mW at VDDof 5 V.