Continuous time sigma delta ADC design and non-idealities analysis

A wide bandwidth continuous time sigma delta ADC is implemented in 130 nm CMOS.A detailed non-idealities analysis(excess loop delay,clock jitter,finite gain and GBW,comparator offset and DAC mismatch) is performed developed in Matlab/Simulink.This design is targeted for wide bandwidth applications such as video or wireless base-stations.A third-order continuous time sigma delta modulator comprises a third-order RC operational-amplifier -based loop filter and 3-bit internal quantizer operated at 512 MHz clock frequency.The sigma delta ADC achieves 60 dB SNR and 59.3 dB SNDR over a 16-MHz signal band at an OSR of 16.The power consumption of the CT sigma delta modulator is 22 mW from the 1.2-V supply.     

连续时间Sigma Delta ADC设计和非理想因素分析

文章设计了一个用于物联网模拟基带的、低压、低功耗、宽带、连续时间Sigma Delta ADC,特别是对各种非理想因素（时钟抖动,环路延时,运放有限增益和带宽,比较器offset,DAC失配等）,基于matlab和simulink等工具进行了系统级仿真并得到各种非理想因素对系统性能的影响。电路架构采用3阶3bit前馈加反馈结构,电源电压1.2V,输入信号带宽为16MHz,过采样率为16,采样频率为512MHz。测试结果显示,SNR为60dB,SNDR为59.3dB,总功耗为22mW。     

A 20-mW 640-MHz CMOS Continuous-Time Σ∆ ADC With 20-MHz Signal Bandwidth, 80-dB Dynamic Range and 12-bit ENOB

A wide bandwidth continuous-time sigma-delta ADC, operating between 20 and 40 MS/s output data rate, is implemented in 130-nm CMOS. The circuit is targeted for applications that demand high bandwidth, high resolution, and low power, such as wireless and wireline communications, medical imaging, video, and instrumentation. The third-order continuous-time SigmaDelta modulator comprises a third-order RC operational-amplifier-based loop filter and 4-bit internal quantizer operating at 640 MHz. A 400-fs rms jitter LC PLL with 450-kHz bandwidth is integrated, generating the low-jitter clock for the jitter-sensitive continuous-time SigmaDelta ADC from a single-ended input clock between 13.5 and 40 MHz. To reduce clock jitter sensitivity, nonreturn-to-zero (NRZ) DAC pulse shaping is used. The excess loop delay is set to half the sampling period of the quantizer and the degradation of modulator stability due to excess loop delay is avoided with a new architecture. The SigmaDelta ADC achieves 76-dB SNR, -78-dB THD, and a 74-dB SNDR or 12 ENOB over a 20-MHz signal band at an OSR of 16. The power consumption of the CT SigmaDelta modulator itself is 20 mW and in total the ADC dissipates 58 mW from the 1.2-V supply     

A 22?mW 512?MHz CMOS continuous time sigma delta ADC in 1.2?V with 16?MHz signal bandwidth and 70?dB dynamic range

A wide bandwidth continuous time sigma delta analog-to-digital conversion is implemented in 130?nm process. The circuit is targeted for wide bandwidth applications such as video or wireless base-stations. The third-order continuous time sigma delta modulator comprises a third-order RC operational-amplifier-based loop filter and 3-bit internal quantizer operated at 512?MHz clock frequency. To reduce the clock jitter sensitivity, nonreturn-to-zero DAC pulse shaping is used. The excess loop delay is set to half the sampling period of the quantizer, and the degradation of modulator stability due to excess loop delay is avoided with this architecture. The sigma delta ADC achieves a 60?dB SNR and a 59.3?dB signal-to-noise-plus-distortion ratio over a 16?MHz signal band at an oversampling ratio of 16. The power consumption of the continuous time sigma delta modulator is 22 mW from the 1.2?V supply.     

A Reduced Delay Method for Improving the Performance of Sigma-Delta Analog-to-Digital Converters (ADC)

Excess loop delay in a continuous-time switched-current modulator causes a stability problem and degrades the modulator's dynamic range. This paper presents a simple and effective way to reduce the loop delay and improve the modulator's performance. The loop delay of the ADC is reduced by feeding the predicted next state to the comparator. With reduced loop delay, a larger loop gain is allowed without a stability problem, and hence, the dynamic range of the ADC is improved. A new circuit architecture to realize a second-order modulator with this method is also presented. From the simulation result, the new architecture shows a 6–10 dB improvement in dynamic range for a second-order modulator.     

一种高速连续时问Sigma—DeltaADC设计

在TSMC0．18／zmCMOS工艺下设计了一款宽带宽、低功耗的连续时间Sigma—DeltaADC调制器。该调制器可以应用于无线通信、视频、医疗和工业成像等领域,它采用三阶RC积分环路滤波结构,提高了可达到的精度。针对环路延时降低系统稳定性的问题,在环路中引入半个采样周期的延时,以此提高调制器的精度;同时采用非回零的DAC结构来减小系统对时钟抖动的敏感度。通过结构的选取和非回零的DAC结构的使用,调制器对时钟抖动有很强的忍受能力。该Sigma—DeltaADC的带宽可以达到5MHz,信噪比可达63．6dB（10位）,整个调制器在1．8V的电压下,功耗仅为32mw。     

5.2 mW 61 dB SNDR 15 MHz Bandwidth CT ΔΣ Modulator Using Single Operational Amplifier and Single Feedback DAC

We propose an architecture that reduces the power consumption and active area of such a modulator through a reduction in the number of active components and a simplification of the topology. The proposed architecture reduces the power consumption and active area by reducing the number of active components and simplifying the modulator topology. A novel second‐order loop filter that uses a single operational amplifier resonator reduces the number of active elements and enhances the controllability of the transfer function. A trapezoidal‐shape half‐delayed return‐to‐zero feedback DAC eliminates the loop‐delay compensation circuitry and improves pulse‐delay sensitivity. These simple features of the modulator allow higher frequency operation and more design flexibility. Implemented in a 130 nm CMOS technology, the prototype modulator occupies an active area of 0.098 mm² and consumes 5.23 mW power from a 1.2 V supply. It achieves a dynamic range of 62 dB and a peak SNDR of 60.95 dB over a 15 MHz signal bandwidth with a sampling frequency of 780 MHz. The figure‐of‐merit of the modulator is 191 fJ/conversion‐step.     

一款使用低功耗多级运放实现的12位，20兆带宽，18毫瓦的连续时间型过采样调制器

本文在130纳米CMOS工艺下实现了一种具有20兆赫兹带宽,四阶连续时间型过采样调制器。调制器由有源积分环路滤波器、4位内部量化器和3个电流舵型反馈数模转换器构成。本文提出了一种三级运算放大器,它可以在获得高带内增益和高带宽的同时消耗较小的功耗。为了减小时钟抖动对连续时间型过采样调制器的影响,内部反馈数模转化器采用了不自归零的反馈波形。同时采用特殊的版图技术保证数模转换器的线性度,同时避免使用动态器件匹配技术引入的额外环路延时。芯片工作在1. 2 V 电源电压和480 M Hz 时钟频率, 在20 MHz 的信号带宽内, 调制器的动态范围为66 dB, 峰值SNR为64.6 dB, 功耗为18 mW。     

A 18-mW,20-MHz bandwidth,12-bit continuous-time∑△modulator using a power-efficient multi-stage amplifier

正A fourth-order continuous-time sigma delta modulator with 20-MHz bandwidth,implemented in 130nm CMOS technology is presented.The modulator is comprised of an active-RC operational-amplifier based loop filter,a 4-bit internal quantizer and three current steering feedback DACs.A three-stage amplifier with low power is designed to satisfy the requirement of high dc gain and high gain-bandwidth product of the loop filter.Non-return-to -zero DAC pulse shaping is utilized to reduce clock jitter sensitivity.A special layout technique guarantees that the main feedback DAC reaches 12-bit match accuracy,avoiding the use of a dynamic element matching algorithm to induce excess loop delay.The experimental results demonstrate a 64.6-dB peak signal-to-noise ratio,and 66-dB dynamic range over a 20-MHz signal bandwidth when clocked at 480 MHz with 18-mW power consumption from a 1.2-V supply.     

一种低功耗高精度Sigma-Delta调制器

提出了一种改进的三阶单环Sigma-Delta调制器,噪声传递函数采用前馈方式实现极点,降低了积分器输出信号的幅度,从而降低功耗;采用局部反馈实现零点,从而优化了输出信噪比。采用0.35μm CMOS工艺设计了该调制器,过采样率128,信号带宽24kHz,分辨率16bit,在3.3V工作电压下,模拟电路部分功耗2.7mW,数字部分功耗0.5mW。电路用开关电容技术实现,在HSPICE中通过多工艺角验证。     

Dynamic range extension technique for high-order ΣΔADCs by digital level control

A new architecture is presented for a high-order multi-bit ΣΔ ADC which does not require a precision multi-bit DAC in the feedback loop. Local digital level control is employed to extend integrator output dynamic range. A prototype fourth-order modulator is simulated with circuit non-idealities, showing an SNR of ~110 dB     

Excess-loop-delay compensation technique for CT ΔΣ modulator with hybrid active–passive loop-filters

The design and optimization methodology for CT ΣΔ modulators with hybrid Active–Passive (AP) loop-filters is indicated in this work. From the discussion, by appropriately scaling the passive filter gain and cooperating with a single-bit quantizer, the hybrid AP loop filtering can achieve an approximated noise-shaping function as a fully active ΔΣ modulator with the same order. The ELD effect in the hybrid AP CT ΔΣ modulator which influences the poles and zeros locations of the Noise Transfer Function (NTF) in the modulator is depicted. This paper also investigates the feasibility of applying the ELD compensation techniques that were used to be implemented in the active integrator’s case to the hybrid AP CT ΔΣ modulator; however, some of them cannot be practically applied since the passive loop-filter cannot perform proportional feedback signal summation. After the discussion and analysis, the technique similar to Vadipour et al. (In: Symposium on VLSI circuits digest of technical papers, 2008) can be easily implemented at circuit-level and after applying it, there is one additional zero to compensate the peak in the NTF. With the help of this technique, the maximum quantizer delay tolerance can be a full clock period. The mentioned ELD compensation technique was applied in a 2nd order CT ΔΣ modulator with an active-RC integrator as the 1st stage and a passive RC filter as the 2nd stage, which was verified by transistor-level simulations in 65 nm CMOS. The circuit exhibits either 67.3 dB or 65.3 of SNDR, under the effect of half clock period or one clock period ELD, respectively; by contrast, without compensation, the system is unstable with both half or one clock period ELD effect. The designed hybrid CT ΔΣ modulator achieves 2 MHz signal bandwidth and consumes 2.54 mW of power.     

Theory and design of a CT \Updelta\Upsigma modulator with low sensitivity to loop-delay variations

This paper presents a 3rd-order, 3-bit continuous-time (CT) $\Updelta\Upsigma$ Δ Σ modulator for an LTE radio receiver. A return-to-zero (RZ) pulse, centered in the sampling period by a quadrature clock, is used in the innermost DAC to reduce the sensitivity to loop-delay variations in the modulator, and omit implementing the additional loop delay compensation usually needed in CT modulators. The performance and stability of the NRZ/NRZ/RZ feedback scheme is thoroughly analysed using a discrete-time model. The modulator has been implemented in a 65 nm CMOS process, where it occupies an area of 0.2 × 0.4 mm². It achieves an SNR of 71 dB and an SNDR of 69 dB over a 9 MHz bandwidth with an oversampling ratio of 16, and a power consumption of 7.5 mW from a 1.2 V supply.     

On the Stability Analysis of High Order Sigma-Delta Modulators

In this paper we present an approach for stability analysis of high order Sigma-Delta modulators. The approach is based on a parallel decomposition of the modulator. In this representation, the general N-th order modulator is transformed into decomposition of low order modulators, which interact only through the quantizer function. In the simplest case of the loop filter transfer function with real distinct poles, the low order modulators are N first order ones. The decomposition considered helps to extract the sufficient conditions for stability of the N-th order modulator. They are determined by the stability conditions of each of the low order modulators but shifted with respect to the origin of the quantizer function, because of the influence of all other low order modulators. The approach is generalized for the case of repeated poles of the loop filter transfer function.     

Non-ideal behavior of a driving resonator loop in a vibratory capacitive microgyroscope

Many researches have been carried out on the dynamic characteristics of vibratory microgyroscope, but only a few have been carried out on the non-ideal behaviors observed in the driving loop of the vibratory microgyroscope. In this paper, characterization and evaluation of the non-ideal behavior of the vibratory microgyroscope, “peak-and-valley” magnitude phenomenon and phase lag distortion, are discussed. To characterize the non-ideal behavior of a microgyroscope driving loop, a new electro-mechanical simulation model based on the HSPICE of microgyroscope driving loop is proposed. The parasitic capacitive components of the driving loop are found to be the major sources of non-ideal behavior in microgyroscope and it is verified with the simulation results. The validity of the proposed simulation model and the parasitic effects on microgyroscope driving loop is evaluated with the actual fabricated gyroscope.     

Design and implementation of a band-pass sigma delta modulator with distributed resonators

Continuous time band-pass sigma delta converters require the realization of high frequency resonators, which have been usually implemented with g _m-C or LC circuits. However, transmission lines have been for a long time a standard way to implement high Q resonators in RF circuits. Recently, some continuous-time sigma–delta (SD) modulator architectures using transmission lines have been proposed. Theoretical analyses have shown that this kind of architectures share some of the properties of both continuous-time (CT) and discrete-time (DT) modulators. On the other hand they have specific implementation problems which are not present in other modulator architectures. This paper makes a brief review of the particularities of these modulators and shows the experimental results of a band-pass modulator implemented in BiCMOS technology. As an advantage compared to standard continuous time designs, this modulator can be operated as a subsampling ADC, displays a better immunity to clock jitter and is tolerant to loop delay.     

Effects of non-ideal Hadamard modulators on the performance ofΠΔΣ ADC

A non-ideal Hadamard modulator in the front-end of ΠΔΣ ADC can be modelled as an ideal Hadamard modulator with gain error in parallel with an offset error. The effects of non-ideal Hadamard modulators can be partially removed by using chopper stabilisation and adaptive channel gain equalisation     

A continuous-time sigma-delta modulator with 88-dB dynamic range and 1.1-MHz signal bandwidth

This paper presents the design and experimental results of a continuous-time /spl Sigma//spl Delta/ modulator for ADSL applications. Multibit nonreturn-to-zero (NRZ) DAC pulse shaping is used to reduce clock jitter sensitivity. The nonzero excess loop delay problem in conventional continuous-time /spl Sigma//spl Delta/ modulators is solved by our proposed architecture. A prototype third-order continuous-time /spl Sigma//spl Delta/ modulator with 5-bit internal quantization was realized in a 0.5-/spl mu/m double-poly triple-metal CMOS technology, with a chip area of 2.4 /spl times/ 2.4 mm/sup 2/. Experimental results show that the modulator achieves 88-dB dynamic range, 84-dB SNR, and 83-dB SNDR over a 1.1-MHz signal bandwidth with an oversampling ratio of 16, while dissipating 62 mW from a 3.3-V supply.     

A monolithic CMOS 20-b analog-to-digital converter

The authors present a monolithic 20-b analog-to-digital converter (ADC) based on an oversampling feedback architecture. The converter consists of a time-continuous integrator at the input, a pulsewidth modulator in the forward branch of the loop (corresponding to a 10-b ADC), and a 1-b DAC (digital-to-analog converter) to generate the feedback voltage. The digital evaluation is carried out with a uniformly weighted rectangular window filter. The circuit is implemented in a standard 2-μm CMOS n-well process and requires 14 mm² of silicon, including the pads. Measurement results are presented that demonstrate the feasibility of this architecture for 20-b accuracy. The complete circuit has a power consumption of 6.7 mW     

Description of a Differential Pulse-Frequency Modulator

The operation of a novel differential pulse-frequency modulator based on the Asynchronous Delta Modulation principle is described in this paper. The complete modulator consists of a Voltage Controlled Oscillator (VCO) in a feedback configuration and generates an output pulse train whose frequency is proportional to the slope of the input signal. It is shown that the proposed system allows substantially larger input signal amplitudes for linear operation than those permitted by open loop VCO schemes or other voltage-to-frequency converters. In addition, the feedback path provides locally a signal that tracks the input, so that the feedback arrangement can be readily used as a demodulator at the receiver end.