基于四值脉冲参数模型的单粒子瞬态传播机理与软错误率分析方法

随着工艺尺寸的不断缩小,由单粒子瞬态(Single Event Transient, SET)效应引起的软错误已经成为影响宇航用深亚微米VLSI电路可靠性的主要威胁,而SET脉冲的产生和传播也成为电路软错误研究的热点问题。通过研究SET脉冲在逻辑链路中的传播发现:脉冲上升时间和下降时间的差异能够引起输出脉冲宽度的展宽或衰减;脉冲的宽度和幅度可决定其是否会被门的电气效应所屏蔽。该文提出一种四值脉冲参数模型可准确模拟SET脉冲形状,并采用结合查找表和经验公式的方法来模拟SET脉冲在电路中的传播过程。该文提出的四值脉冲参数模型可模拟SET脉冲在传播过程中的展宽和衰减效应,与单参数脉冲模型相比计算精度提高了2.4%。该文应用基于图的故障传播概率算法模拟SET脉冲传播过程中的逻辑屏蔽,可快速计算电路的软错误率。对ISCAS89及ISCAS85电路进行分析的实验结果表明:该方法与HSPICE仿真方法的平均偏差为4.12%,计算速度提升10000倍。该文方法可对大规模集成电路的软错误率进行快速分析。     

Soft Error Rate Reduction Using Circuit Optimization and Transient Filter Insertion

This paper describes a tunable transient filter (TTF) design for soft error rate reduction in combinational logic circuits. TTFs can be inserted into combinational circuits to suppress propagated single-event transients (SETs) before they can be captured in latches or flip-flops. TTFs are tuned by adjusting the maximum width of the propagated SET that can be suppressed. A TTF requires 6–14 transistors, making it an attractive cost-effective option to reduce the soft error rate in combinational circuits. A global optimization approach based on geometric programming that integrates TTF insertion with dual-V _DD and gate sizing is described. Simulation results for the 65 nm process technology indicate that a 17–48× reduction in the soft error rate can be achieved with this approach.     

量子逻辑电路故障检测定位及自修复方法研究

针对量子逻辑电路规模逐渐增大,电路可靠性逐渐下降的问题,提出基于单个量子逻辑门在线故障检测定位方法,该方法使用新构造的检测信号生成门与故障检测门,利用奇偶保持特性判断待测量子逻辑门是否发生故障,同时在设计过程中对信号检测电路进行检验,保证检测电路的正确性。此外提出了基于硬件冗余的量子逻辑电路自修复设计方法。实验结果表明,文中故障检测方法在量子门和垃圾位等性能指标上相对已有方法均有了改进,首次实现的量子逻辑电路的自修复设计大大提高了电路的容错能力和可靠性。     

Extended phase-mode logic-circuits with resistive ground contact

We present extended phase-mode logic (EPL) circuits which have resistive ground contact. The phase-mode logic utilizes magnetic flux-transfer and is based on pulse propagation, i.e., it is one of single flux quantum systems. The proposed logic circuits of the EPL family can have the same ground reference, contrary to the original phase-mode circuits, Therefore, it is possible to couple different EPL elements on a single ground reference. Basic components of the EPL family (a phase-conserving branch, a phase-distributing branch, and an INHIBIT gate controlled by fluxon) are presented. The phase-distributing branch and the INHIBIT gate have been fabricated using a Nb/AlO_x /Nb Josephson-junction technology and tested. A fan-in operation of the phase-distributing branch and the first full operation of the INHIBIT gate are successfully demonstrated. As an example of the EPL logic circuits consisting of plural gates on a single ground reference, a simulation of a 2-bit full adder circuit is also presented     

Characterizing,modeling, and analyzing soft error propagation in asynchronous and synchronous digital circuits

Soft errors, due to cosmic radiations, are one of the major challenges for reliable VLSI designs. In this paper, we present a symbolic framework to model soft errors in both synchronous and asynchronous designs. The proposed methodology utilizes Multiway Decision Graphs (MDGs) and glitch-propagation sets (GP sets) to obtain soft error rate (SER) estimation at gate level. This work helps mitigate design for testability (DFT) issues in relation to identifying the controllable and the observable circuit nodes, when the circuit is subject to soft errors. Also, this methodology allows designers to apply radiation tolerance techniques on reduced sets of internal nodes. To demonstrate the effectiveness of our technique, several ISCAS89 sequential and combinational benchmark circuits, and multiple asynchronous handshake circuits have been analyzed. Results indicate that the proposed technique is on average 4.29 times faster than the best contemporary state-of-the-art techniques. The proposed technique is capable to exhaustively identify soft error glitch propagation paths, which are then used to estimate the SER. To the best of our knowledge, this is the first time that a decision diagram based soft error identification approach is proposed for asynchronous circuits.     

Coupling induced soft error mechanisms in nanoscale CMOS technologies

Due to scaling induced effects, CMOS circuits become increasingly more sensitive to transient pulses caused by single event (SE) particles. Researchers mostly considered SE transients as the main cause for combinational logic (CL) related radiation-induced soft errors. However, for high-reliability applications such as avionics, military and medical applications, additional sources such as SE induced soft delays, clock jitters, false clock pulses and crosstalk effects need to be included in soft-error reliability analysis. As technologies advance, coupling effects among interconnects increasingly cause SE transients to contaminate electronically unrelated circuit paths, which can in turn increase the “SE susceptibility” of CMOS circuits. This work focuses on such coupling induced soft error mechanisms in CL, namely the SE crosstalk noise and delay effects. An attempt has been made to compare SE crosstalk noise and SE transient effects, and crosstalk contribution to soft error rate has been examined. In addition, the SE induced coupling delay effect has been studied and compared to radiation induced soft delay effect for various technologies. Results show that, in newer technologies, the SE coupling delay becomes quite comparable to soft delay effect, although caused indirectly by cross-coupling effects. In comparisons, the distributed nature of interconnects has been taken into account and results are demonstrated using HSPICE simulations with interconnect and device parameters derived in 130, 90 and 65 nm technologies.     

基于保护门的纳米CMOS电路抗单粒子瞬态加固技术研究

随着器件特征尺寸的缩减,单粒子瞬态效应(SET)成为空间辐射环境中先进集成电路可靠性的主要威胁之一。基于保护门,提出了一种抗SET的加固单元。该加固单元不仅可以过滤组合逻辑电路传播的SET脉冲,而且因逻辑门的电气遮掩效应和电气隔离,可对SET脉冲产生衰减作用,进而减弱到达时序电路的SET脉冲。在45 nm工艺节点下,开展了电路的随机SET故障注入仿真分析。结果表明,与其他加固单元相比,所提出的加固单元的功耗时延积(PDP)尽管平均增加了17.42%,但容忍SET的最大脉冲宽度平均提高了113.65%,且时延平均降低了38.24%。     

Switch-level soft error emulation for SET-induced pulses of variable strengths

Due to the increased complexity of modern digital circuits, the use of simulation-based soft error detection methods has become cumbersome and very time-consuming. FPGA-based emulation provides an attractive alternative, as it can not only provide faster speed, but also handle highly complex circuits. In this work, a novel FPGA-based soft error detection technique is proposed, which enables detection of soft errors resulting from voltage pulses of different magnitudes induced by single-event transients (SETs). The paper analyzes the effect of transient injection location on soft error rate (SER) and applies the idea of transient equivalence to minimize resource overhead as well as speed-up emulation process. Switch-level implementations of ISCAS’85 benchmarks are designed using gate-level structures and experimental results are reported. The results show that an application of transient equivalence results in an emulation speed-up of 2.875 and reduces the memory utilization by 65%. An average soft error rate (SER) of 0.7-0.8 was achieved using the proposed strength-based detection with drain as transient injection location, showing that voltage pulses of magnitude smaller than logic threshold can eventually result in soft errors. Furthermore, the presented emulation-based soft error detection technique achieved significant speed-up of the order of 10⁶ compared to a customized simulation-based method.     

RTD多值逻辑(MVL)电路

RTD具有双稳和自锁特性,用RTD构成电路可节省大量器件,这一优点在构建多值逻辑电路(MVL RTD)时显得尤为突出。在引用"遏止"概念的基础上介绍了几种典型的MVL RTD电路,包括多幅输入脉冲信号具有选幅功能的文字逻辑门、能提供三个不同电平输出的三态反相器、将一输入斜坡电压信号变成脉冲输出信号的折线量化器等电路;用"遏止"概念分析了异或门电路的工作原理。     

低电压下CMOS数字电路概率模型研究

为解决数字电路低功耗问题,电路工作电压被不断降低,导致电路逻辑器件呈现概率特性。本文提出了低电压下CMOS数字电路的错误概率模型,并完成硬件电路测试验证。本文首先详述了深亚微米（DSM）量级的门电路及模块在低电压供电条件下导致器件出错的因素,结合概率器件结构模型推导基本逻辑门概率模型,并提出了状态转移法用于完成由门级到模块级的概率分析模型;我们搭建硬件平台对CMOS逻辑芯片进行了低供电压测试,通过分析理论推导结果与实测结果,验证并完善了分析模型。实验结果表明,由状态转移法推导的电路概率模型符合电路实际性能,从而为构建低电压下数字电路概率模型提供了可靠分析模型。      

Efficient algorithm for glitch power reduction [CMOS logiccircuits]

An efficient algorithm is proposed for reducing glitch power dissipation in CMOS logic circuits. The proposed algorithm takes a path balancing approach that is achieved using gate sizing and buffer insertion methods. The gate sizing technique reduces not only glitches but also the effective circuit capacitance. After gate sizing, buffers are inserted into the remaining unbalanced paths which have not been subjected to gate sizing. ILP has been employed to determine the location of inserted buffers. The proposed algorithm has been tested on LGSynth91 benchmark circuits. Experimental results show that 61.5% of glitches are reduced on average     

Graphene nanoribbon crossbar architecture for low power and dense circuit implementations

Crossbar array is a promising nanoscale architecture which can be used for logic circuit implementation. In this work, a graphene nanoribbon (GNR) based crossbar architecture is proposed. This design uses parallel GNRs as device channel and metal as gate, source and drain contacts. Schottky-barrier type graphene nanoribbon field-effect transistors (SB-GNRFETs) are formed at the cross points of the GNRs and the metallic gates. Benchmark circuits are implemented using the proposed crossbar, Si-CMOS and multi-gate Si-CMOS approaches to evaluate the performance of the crossbar architecture compared to the conventional CMOS logic design. The compact SPICE model of SB-GNRFET was used to simulate crossbar-based circuits. The CMOS circuits are also simulated using 16 nm technology parameters. Simulation results of benchmark circuits using SIS synthesis tool indicate that the GNR-based crossbar circuits outperform conventional CMOS circuits in low power applications. Area optimized cell libraries are implemented based on the asymmetric crossbar architecture. The area of the circuit can be more reduced using this architecture at the expense of higher delay. The crossbar cells can be combined with CMOS cells to exhibit better performance in terms of EDP.     

Interconnect accelerating techniques for sub-100-nm gigascale systems

This work describes new circuits called capacitor coupling trigger and capacitor coupling accelerator (CCA) circuits used to reduce the long interconnect RC delay in sub-100-nm processes. The proposed circuits use capacitors to split the output driving paths to eliminate the short-circuit current and thus improve the signal transition time. Besides, the capacitor coupling technique is applied to adjust the gate threshold voltage of the proposed circuits and isolate the input signal from the output driving transistors. The proposed circuits are faster than the prior circuits. Furthermore, the CCA can be applied to bi-directional interface, multiports bus, field-programmable gate array interconnections, and complex dynamic logic circuits.     

Noise Analysis of Soft Errors in Combinational Digital Circuits Via Walsh Transforms

The noise produced at the output of combinational logic circuits by individual gate failures is analyzed through the use of Walsh functions. Soft errors are modeled by allowing the output of each gate in a particular realization to fail temporarily, possibly introducing an error in the single binary output. The input variables also are allowed to be stochastically driven. The output probability of error contains the Walsh transform of an extended logic function and the Walsh characteristic functions of the input variables as well as the individual gate failure variables. These results are specialized to the case where the inputs are statistically independent of the soft errors. A discussion of the transform of the extended logic function is included.     

Design and Application of a 20K Gate Array

This paper describes the design and architecture of a novel VLSI gate array in CMOS technology and its application for a 3-bit error checking and correcting (ECC) unit. The cell rows of the master are arranged without intermediate channels for routing (``sea of gates'). This scheme can be utilized to build large macro cells and functional blocks like data paths or systolic array cells which are very area consuming to realize in conventional gate arrays. In addition, special pull-up/pull-down cells are included on the chip which can be used for data buses and timing circuits. The technology used is an advanced p-well CMOS process with 1.8-μm geometric channel lengths and a two-layer metallization. There are 260 programmable pads for input/output functions and 20 additional power pads (280 pads in total). Depending on the logic, circuits with up to 25 000 gates can be realized with this device.     

基于时序优先的电路容错混合加固方案

为了有效降低容忍软错误设计的硬件和时序开销,该文提出一种时序优先的电路容错混合加固方案。该方案使用两阶段加固策略,综合运用触发器替换和复制门法。第1阶段,基于时序优先的原则,在电路时序松弛的路径上使用高可靠性时空冗余触发器来加固电路;第2阶段,在时序紧张的路径使用复制门法进行加固。和传统方案相比,该方案既有效屏蔽单粒子瞬态(SET)和单粒子翻转(SEU),又减少了面积开销。ISCAS89电路在45 nm工艺下的实验表明,平均面积开销为36.84%,电路平均软错误率降低99%以上。     

Formal Methods Based Synthesis of Single Event Transient Tolerant Combinational Circuits

Recent radiation ground testing campaigns of digital designs have demonstrated that the probability for Single Event Transient (SET) propagation is increasing in advanced technologies. This paper presents a hierarchical reliability-aware synthesis framework to design combinational circuits at gate level with minimal area overhead. This framework starts by estimating the vulnerability of the circuit to SETs. This is done by modeling the SET propagation as a Satisfiability problem by utilizing Satisfiability Modulo Theories (SMTs). An all-solution SMT solver is adapted to estimate the soft error rate due to SETs. Different strategies to mitigate SETs are integrated in the proposed framework to selectively harden vulnerable nodes in the design. Both logical and temporal masking factors of the target circuit are improved to harden sensitive paths or sub-circuits, whose SET propagation probability is relatively high. This process is repeated until the desired soft error rate is achieved or a given area overhead constraint is met. The proposed framework was implemented on different combinational designs. The reliability of a circuit can be improved by 64% with less than 20% area overhead.     

Switch-level emulation of strength-base soft error detection

Modern nanometer circuits have become more prone to soft errors necessitating faster and more reliable error detection techniques. Simulation-based soft error detection has been popular but is limited by its inability to handle complex circuits and high run-time. FPGA-based soft error detection methods can be effectively used to overcome the speed limitation of simulation as well as handle circuits with much higher complexity. The paper presents a novel strength-based soft error emulation method targeting soft errors caused by transient pulses of magnitude less than logic threshold. The impact of transient injection location on soft error coverage is analyzed and the idea of using drain of a transistor as transient injection location is presented. Furthermore, the concept of transient equivalence is applied to minimize resource overhead as well as speed-up soft error detection process. Advanced switch-level models are designed using gate-level structure and used to implement switch-level equivalents of ISCAS’85 benchmarks. The experimental results reported for ISCAS’85 benchmarks show that an average soft error coverage of 0.7-0.8 was achieved using the proposed strength-based detection with drain as transient injection location. The application of transient equivalence resulted in speed-up of emulation by 2.875 and reduced the memory utilization by 65%. The emulation-based soft error detection achieved significant speed-up of the order of 10⁶ as compared to a customized simulation-based method.     

Timing-driven logic restructuring for nano-hybrid circuits

As the feature size of the integrated circuits (ICs) scales down, the future of nano-hybrid circuit looks bright in extending Moore's Law. However, mapping a circuit to a nano-fabric structure is vexing due to connectivity constraints. A mainstream methodology is that a circuit is transformed into a nano-fabric preferred structure by buffer insertion to high fan-out gates. However, it may result in timing degradation. Logic replication is a traditional way to split high fan-out gates in logic synthesis but may not be suitable for high fan-out gates with high fan-ins. In this article, a timing-driven logic restructuring framework at the gate level is proposed. The proposed framework identifies the high fan-out gates from a given gate netlist according to the fan-out threshold, following by the restructuring of high fan-out gates through the application of logic replication and buffer insertion. To improve circuit timing from a global perspective, latent critical edges are identified to avoid entrapping critical paths during the restructuring. Experimental results on ISCAS benchmarks indicate that 8.51% timing improvement and 6.13% CPU time reduction can be obtained traded with 4.16% area increase on an average.     

Analyzing Vulnerability of Asynchronous Pipeline to Soft Errors: Leveraging Formal Verification

Glitches due to the secondary neutron particles from cosmic rays cause soft errors in integrated circuits (IC) that are becoming a major threat in modern sub 45nm ICs. Therefore, researchers have developed many techniques to mitigate the soft errors and some of them utilize the built in error detection schemes of low-power asynchronous null conventional logic (NCL). However, it requires extensive simulations and emulations for careful and complete analysis of the design, which can be costly, time consuming and cannot encompass all the possible input conditions. In this paper, we propose a framework to improve the soft error tolerant asynchronous pipelines by identifying and formally analyzing the vulnerable paths using the nuXmv model checker. The proposed framework translates the design behavior and specification into a state-space model and the potential vulnerabilities against soft errors in the pipeline as linear temporal logical (LTL) properties. These formally specified properties are then verified on the state-space model and in case of failure counterexamples are obtained. These counterexamples can then be further analyzed to obtain the soft error propagation paths and thus give insights about soft error tolerant approaches to the designers. For illustration, this work provides an analysis and comparison of three state-of-the-art asynchronous pipelines. Formal model and analysis of all the pipelines show that the soft error hardened pipeline is comparatively superior against soft errors but at the expense of almost two times area overhead.