Design of dual‐outputs‐single‐stage a‐Si:H TFT gate driver for high resolution TFT‐LCD application

A new gate driver has been designed and fabricated by amorphous silicon technology. With utilizing the concept of sharing the noise free block in a single stage for gate driver, dual‐outputs signals could be generated in sequence. By increasing the number of output circuit block in proposed gate driver, number of outputs per stage could also be adding that improves the efficiency for area reduction. Besides, using single driving thin‐film‐transistor (TFT) for charging and discharging, the area of circuit is also decreased by diminishing the size of pulling down TFT. Moreover, the proposed gate driver has been successfully demonstrated in a 5.5‐inch Full HD (1080xRGBx1920) TFT‐liquid‐crystal display panel and passed reliability tests of the supporting foundry.     

Amorphous‐silicon gate‐driver circuits of shared‐node dual pull‐down structure with overlapped output signals

Abstract— A novel gate‐driver circuit using amorphous‐silicon (a‐Si) TFTs has been developed. The circuit has a shared‐node dual pull‐down AC (SDAC) structure with a common‐node controller for two neighboring stages, resulting in a reduced number of TFTs. The overlapped clock signals widen the temperature range for stable operation due to the extended charging time of the inner nodes of the circuit. The accelerated lifetime was found to be over 1000 hours at 60°C with good bias‐temperature‐stress (BTS) characteristics. Accordingly, the a‐Si gate‐driver circuit was successfully integrated into a 14.1‐in. XGA (1024 × RGB × 768) TFT‐LCD panel having a single bank form.     

Highly robust oxide TFT with bulk accumulation and source/drain/active layer splitting

We report stable and high performance amorphous indium‐gallium‐zinc oxide (a‐IGZO) thin‐film transistor (TFT) by using bulk‐accumulation (BA) and split active/source/drain layers. The a‐IGZO TFTs exhibit the mobility over 80 cm²/Vs and extremely stable under bias and mechanical stresses. We demonstrated a 4‐inch semitransparent AMOLED using the oxide TFT backplane with the gate driver integrated.     

Novel top‐gate zinc oxide thin‐film transistors (ZnO TFTs) for AMLCDs

Abstract— High‐performance top‐gate thin‐film transistors (TFTs) with a transparent zinc oxide (ZnO) channel have been developed. ZnO thin films used as active channels were deposited by rf magnetron sputtering. The electrical properties and thermal stability of the ZnO films are controlled by the deposition conditions. A gate insulator made of silicon nitride (SiN_x) was deposited on the ZnO films by conventional P‐CVD. A novel ZnO‐TFT process based on photolithography is proposed for AMLCDs. AMLCDs having an aperture ratio and pixel density comparable to those of a‐Si:H TFT‐LCDs are driven by ZnO TFTs using the same driving scheme of conventional AMLCDs.     

Design of a low‐power‐consumption a‐IGZO TFT‐based Vcom driver circuit with long‐term reliability

Abstract— An amorphous‐InGaZnO (a‐IGZO) thin‐film transistor (TFT)‐based Vcom driver circuit that has long‐term reliability and can be integrated with the pixel array on a panel has been designed. Owing to the Vcom inversion, the power consumed by the proposed driving scheme is 40% less than that consumed by the conventional line‐inversion method. The high mobility (>10 cm²/V‐sec) of the a‐IGZO TFTs allows the integration of devices with small channel widths (<750 μm) and thus keeps the overall device size small, which is important for displays with narrow bezels. The lifetime of the Vcom driver is improved by AC driving (by clocking the n‐th and (n + 1)‐th frame with 20 and 0 V, respectively) of the buffer TFTs.     

Amorphous‐oxide TFT backplane for large‐sized AMOLED TVs

Abstract— Amorphous‐oxide thin‐film‐transistor (TFT) arrays have been developed as TFT backplanes for large‐sized active‐matrix organic light‐emitting‐diode (AMOLED) displays. An amorphous‐IGZO (indium gallium zinc oxide) bottom‐gate TFT with an etch‐stop layer (ESL) delivered excel lent electrical performance with a field‐effect mobility of 21 cm²/V‐sec, an on/off ratio of >10⁸, and a subthreshold slope (SS) of 0.29 V/dec. Also, a new pixel circuit for AMOLED displays based on amorphous‐oxide semiconductor TFTs is proposed. The circuit consists of four switching TFTs and one driving TFT. The circuit simulation results showed that the new pixel circuit has better performance than conventional threshold‐voltage (VTH) compensation pixel circuits, especially in the negative state. A full‐color 19‐in. AMOLED display with the new pixel circuit was fabricated, and the pixel circuit operation was verified in a 19‐in. AMOLED display. The AMOLED display with a‐IGZO TFT array is promising for large‐sized TV because a‐IGZO TFTs can provide a large‐sized backplane with excellent uniformity and device reliability.     

In‐pixel temperature sensor for high‐luminance active matrix micro‐light‐emitting diode display using low‐temperature polycrystalline silicon and oxide thin‐film‐transistors

We propose an in‐pixel temperature sensor using low‐temperature polycrystalline silicon and oxide (LTPO) thin‐film transistor (TFTs) for high‐luminance active matrix (AM) micro‐light‐emitting diode (LED) displays. By taking advantage of the different off‐current characteristics of p‐type LTPS TFTs and n‐type a‐IGZO TFTs under temperature change, we designed and fabricated a temperature sensor consists of only LTPO TFTs without additional sensing component or material. The fabricated sensor exhibits excellent temperature sensitivity of up to 71.8 mV/°C. In addition, a 64 × 64 temperature sensor array with 3T sensing pixel and integrated gate driver has also been fabricated, which demonstrates potential approach for maxing out the performance of high‐luminance AM micro‐LED display with real‐time in‐pixel temperature monitoring.     

Novel self‐aligned top‐gate oxide TFT for AMOLED displays

Abstract— A novel highly reliable self‐aligned top‐gate oxide‐semiconductor thin‐film transistor (TFT) formed by using the aluminum (Al) reaction method has been developed. This TFT structure has advantages such as small‐sized TFTs, lower mask count, and small parasitic capacitance. The TFT with a 4‐μm channel length exhibited a field‐effect mobility of 21.6 cm²/V‐sec, a threshold voltage of ?1.2 V, and a subthreshold swing of 0.12 V/decade. Highly reliable TFTs were obtained after 300°C annealing without increasing the sheet resistivity of the source/drain region. A 9.9‐in.‐diagonal qHD AMOLED display was demonstrated with self‐aligned top‐gate oxide‐semiconductor TFTs for a low‐cost and ultra‐high‐definition OLED display. Excellent brightness uniformity could be achieved due to small parasitic capacitance.     

Driver‐circuits‐integrated LCDs based on novel amorphous In‐Ga‐Zn‐oxide TFT

Abstract— A liquid‐crystal panel integrated with a gate driver and a source driver by using amorphous In—Ga—Zn‐oxide TFTs was designed, prototyped, and evaluated. By using the process of bottom‐gate bottom‐contact (BGBC) TFTs, amorphous In—Ga—Zn‐oxide TFTs with superior characteristics were provided. Further, for the first time in the world, a 4‐in. QVGA liquid‐crystal panel integrated with a gate driver and a source driver was developed by using BGBC TFTs formed from an oxide semiconductor. By evaluating the liquid‐crystal panel, its functionality was successfully demonstrate. Based on the findings, it is believed that the novel BGBC amorphous In—Ga—Zn‐oxide TFT will be a promising candidate for future large‐screen backplanes having high definition.     

High‐reliability gate driver circuit to prevent ripple voltage

In this paper, a high‐reliability gate driver circuit is proposed to prevent multiple outputs. The proposed circuit ensures reliability of the pull‐up thin‐film transistor (TFT) by periodically discharging the Q node voltage to the low‐level voltage (VGL) in the off stage. In addition, the output node is composed of two pull‐down TFTs that are driven alternately to ensure stability against bias stress. Thus, because the reliabilities of the pull‐up and pull‐down TFTs can be guaranteed simultaneously, the stability of the entire circuit is improved. Based on the simulation results, the rising and falling times of the output pulse are stable within 1.77 and 1.28 μs, respectively, even when the threshold voltage of the entire TFT is shifted by +10.0 V. In addition, the ripple voltage of the proposed circuit is almost eliminated and is within 0.79% of the total swing voltage. Moreover, through current is prevented in the proposed circuit because the turn‐on durations of the pull‐up and pull‐down units are completely nonoverlapping, which suggests that unnecessary power consumption can be eliminated. Therefore, based on 2,160 stages, the total power consumption of the proposed circuit is reduced by 34.7 mW from 276.3 to 241.6 mW.     

High performance a‐IGZO thin‐film transistors with mf‐PVD SiO2 as an etch‐stop‐layer

In this work, we report on high‐performance bottom‐gate top‐contact (BGTC) amorphous‐Indium‐Gallium‐Zinc‐Oxide (a‐IGZO) thin‐film transistor (TFT) with SiO₂ as an etch‐stop‐layer (ESL) deposited by medium frequency physical vapor deposition (mf‐PVD). The TFTs show field‐effect mobility (μ_FE) of 16.0 cm²/(V.s), sub‐threshold slope (SS^?1) of 0.23 V/decade and off‐currents (I_OFF) < 1.0 pA. The TFTs with mf‐PVD SiO₂ ESL deposited at room temperature were compared with TFTs made with the conventional plasma‐enhanced chemical vapor deposition (PECVD) SiO₂ ESL deposited at 300 °C and at 200 °C. The TFTs with different ESLs showed a comparable performance regarding μ_FE, SS^?1, and I_OFF, however, significant differences were measured in gate bias‐stress stability when stressed under a gate field of +/?1 MV/cm for duration of 10⁴ s. The TFTs with mf‐PVD SiO₂ ESL showed lower threshold‐voltage (V_TH) shifts compared with TFTs with 300 °C PECVD SiO₂ ESL and TFTs with 200 °C PECVD SiO₂ ESL. We associate the improved bias‐stress stability of the mf‐PVD SiO₂ ESL TFTs to the low hydrogen content of the mf‐PVD SiO₂ layer, which has been verified by Rutherford‐Back‐Scattering‐Elastic‐Recoil‐Detection technique.     

Bezel free design of organic light emitting diode display via a‐InGaZnO gate driver circuit integration within active array

In this article, we described an innovative design technology of active matrix organic light emitting diode (AMOLED) display, to provide a bezel free design. We designed gate driver circuit of amorphous indium‐gallium‐zinc oxide thin‐film transistors (TFTs) not on the bezel area but within the active array. Although we applied challengeable design, no degradation of electrical/optical properties of panel was observed. Because we effectively prevented capacitive coupling and interference between the emission circuit and integrated gate driver circuit in active array, finally, we successfully demonstrated a bezel free designed AMOLED display of 18.3″ HD (1366 × 768) driven by a‐InGaZnO TFTs.     

Development of 8‐in. oxide‐TFT‐driven flexible AMOLED display using high‐performance red phosphorescent OLED

An 8‐in. flexible active‐matrix organic light‐emitting diode (AMOLED) display driven by oxide thin‐film transistors (TFTs) has been developed. In‐Ga‐Zn‐O (IGZO)‐TFTs used as driving devices were fabricated directly on a plastic film at a low temperature below 200 °C. To form a SiO_x layer for use as the gate insulator of the TFTs, direct current pulse sputtering was used for the deposition at a low temperature. The fabricated TFT shows a good transfer characteristic and enough carrier mobility to drive OLED displays with Video Graphic Array pixels. A solution‐processable photo‐sensitive polymer was also used as a passivation layer of the TFTs. Furthermore, a high‐performance phosphorescent OLED was developed as a red‐light‐emitting device. Both lower power consumption and longer lifetime were achieved in the OLED, which used an efficient energy transfer from the host material to the guest material in the emission layer. By assembling these technologies, a flexible AMOLED display was fabricated on the plastic film. We obtained a clear and uniform moving color image on the display.     

Active‐matrix organic light‐emitting displays employing two thin‐film‐transistor a‐Si:H pixels on flexible stainless‐steel foil

Abstract— An active‐matrix organic light‐emitting diode (AMOLED) display driven by hydrogenated amorphous‐silicon thin‐film transistors (a‐Si:H TFTs) on flexible, stainless‐steel foil was demonstrated. The 2‐TFT voltage‐programmed pixel circuits were fabricated using a standard a‐Si:H process at maximum temperature of 280°C in a bottom‐gate staggered source‐drain geometry. The 70‐ppi monochrome display consists of (48 × 4) × 48 subpixels of 92 ×369 μm each, with an aperture ratio of 48%. The a‐Si:H TFT pixel circuits drive top‐emitting green electrophosphorescent OLEDs to a peak luminance of 2000 cd/m².     

A novel gate driver circuit for depletion‐mode a‐IGZO TFTs

In this paper, a novel gate driver circuit, which can achieve high reliability for depletion mode in a‐InGaZnO thin‐film transistors (TFTs), was proposed. To prevent the leakage current paths for Q node effectively, the new driving method was proposed by adopting the negative gate‐to‐source voltage (V_GS) value for pull‐down units. The results showed all the V_OUT voltage waveforms were maintained at VGH voltage despite depletion‐mode operation. The proposed circuit could also obtain stable V_OUT voltage when the threshold voltage for all TFTs was changed from ?6.5 to +11.5 V. Therefore, the circuit can achieve high reliability regardless of threshold voltage value for a‐IGZO TFTs. In addition, the output characteristics and total power consumption were shown for the alternating current (AC)–driven and direct current (DC)–driven methods based on 120‐Hz full‐HD graphics (1920 × 1080) display panel. The results showed that the AC‐driven method could achieve improved V_OUT characteristics compared with DC‐driven method since the leakage current path for Q node can be completely eliminated. Although power consumption of the AC‐driven method can be slightly increased compared with the DC‐driven method for enhancement mode, consumption can be lower when the operation has depletion‐mode characteristics by preventing a leakage current path for pull‐down units. Consequently, the proposed gate driver circuit can overcome the problems caused by the characteristics of a‐IGZO TFTs.     

Modeling of current—voltage characteristics for double‐gate a‐IGZO TFTs and its application to AMLCDs

Abstract— The equations for the transfer characteristics, subthreshold swing, and saturation voltage of double‐gate (DG) a‐IGZO TFTs, when the top‐ and bottom‐gate electrodes are connected together (synchronized), were developed. From these equations, it is found thatsynchronized DG a‐IGZO TFTs can be considered as conventional TFTs with a modified gate capacitance and threshold voltage. The developed models were compared with the top or bottom gate only bias conditions. The validity of the models is discussed by using the extracted TFT parameters for DG coplanar homojunction TFTs. Lastly, the new pixel circuit and layout based on a synchronized DG a‐IGZO TFT is introduced.     

Robust integrated shift register circuit over clock noises for in‐cell touch applications

This paper proposes an integrated shift register circuit for an in‐cell touch panel that is robust over clock noises. It is composed of 10 thin film transistors and 1 capacitor, and the time division driving method is adopted to prevent the negative effect of display signals on the touch sensing. Two pre‐charging nodes are employed for reducing the uniformity degradation of gate pulses over time. In particular, the proposed circuit connects a drain of the first pre‐charging node's pull‐up thin film transistor (TFT) to the positive supply voltage instead of clock signals. This facilitates to lower coupling noises as well as to clock power consumption. The simulation program with an integrated circuit emphasis is conducted for the proposed circuit with low temperature poly‐silicon TFTs. The positive threshold voltage that shifts up to 12 V at the first pre‐charging pull‐up TFT can be compensated for without the uniformity degradation of gate pulses. For a 60‐Hz full‐HD display with a 120‐Hz reporting rate of touches, the clock power consumption of the proposed gate driver circuit is estimated as 7.13 mW with 160 stages of shift registers. In addition, the noise level at the first pre‐charging node is lowered to ?28.95 dB compared with 2.37 dB of the previous circuit.     

Development of 55” 4K UHD OLED TV employing the internal gate IC with high reliability and short channel IGZO TFTs

We investigated oxide TFT backplane technology to employ the internal gate driver IC (GIP circuit) on 55” 4K OLED TV panel. For the GIP circuit, we developed the high reliability oxide TFTs, especially only ?0.4 V Vth degradation under 100‐h long‐term PBTS stress and the short channel length TFTs (L = 4.5um) for narrow bezel. Consequently, we demonstrated the 55‐in 4K OLED TV employing the internal gate IC with high reliability and short channel IGZO TFTs.     

An averaging pixel structure using microcrystalline‐silicon films prepared at high temperature for AMOLED displays

Abstract— A new voltage‐addressed pixel using a multiple drive distribution has been developed to improve, in a simple way, the brightness uniformity of active‐matrix organic light‐emitting‐diode (AMOLED) displays. Moreover, circuits were realized using microcrystalline‐silicon (μc‐Si) films prepared at 600°C using a standard low‐pressure CVD system. The developed p‐channel TFTs exhibit a field‐effect mobility close to 6 cm²/V‐sec. The experimental results show that the proposed spatial distribution of driving TFTs improves the uniformity of current levels, in contrast to the conventional two‐TFT pixel structure. Backplane performances have been compared using circuits based on μc‐Si and furnace‐annealed polysilicon materials. Finally, this technology has been used to make an AMOLED demonstration unit using a top‐emission OLED structure. Thus, by combining both an μc‐Si active‐layer and a current‐averaging driver, an unsophisticated solution is provided to solve the inter‐pixel non‐uniformity issue.     

Layer‐by‐layer nitrogenation of microcrystalline silicon for TFT applications

Abstract— We have optimized the low‐temperature growth of microcrystalline silicon at 80°C. This material has been used to fabricate bottom‐gate μc‐Si:H TFTs by using a layer‐by‐layer nitrogenation process. By using this process, the amorphous incubation layer can be converted into silicon nitride and leads to an increase in a field‐effect mobility of the TFT.