高速实时数据采集智能控制器的设计与实现

文章以嵌入式和数据采集技术为基础,研究设计并实现了基于ARM+FPGA体系架构面向高速实时数据采集应用的一种实用新型智能控制器。本文阐述了主处理器ARM最小系统、协处理器FPGA最小系统和ARM与FPGA通信接口等硬件系统技术的实现,以及Linux FPGA字符设备驱动程序开发、协处理器FPGA控制程序和主处理器ARM应用程序设计。智能控制器运用FPGA并行运算处理结构的优势,控制ADC进行高速数据采集。FPGA还可配置成软核处理器-Nios II嵌入式处理器,与ARM构成双核处理器系统。智能控制器通过ARM实现对FPGA的管理控制、实时数据采集和丰富外围接口的通信。     

Mapping of generalized template matching onto reconfigurable computers

Image processing algorithms for template matching, two-dimensional (2-D) digital filtering, morphologic operations, and motion estimation share some common properties. They can all benefit from using reconfigurable computers that use coprocessor boards based on field-programmable gate array (FPGA) chips. This paper characterizes those applications as generalized template matching (GTM) operations and describes the mapping of the GTM operations onto reconfigurable computers. A three-step approach is described. The first two steps enumerate and prune the design space of basic GTM building blocks, which consist of FPGA buffers and GTM computation cores. The last step is to achieve a solution through an optimal combination of these building blocks where the cost function is the FPGA computation time and the constraints are FPGA coprocessor board resources. Various FPGA buffers are presented so as to introduce design options of basic GTM building blocks. Algorithms used for the mapping are described. Experimental results are summarized to reveal the relationship between the GTM mapping results and FPGA board resource parameters.     

基于DSP+FPGA的嵌入式图像处理系统设计

为满足数据量大、算法复杂度高的应用需求,使用高性能DSP完成复杂图像算法处理,FPGA作为协处理器,完成图像采集、存储和显示等功能,构建了一种高性能的嵌入式图像处理系统。DSP和FPGA通过EMIF接口实现了高速无缝互联。采用三重缓冲读写机制解决了采集和显示的异步时钟域问题及算法处理时间不确定的问题。介绍了基于BIOS和NDK开发的C6455软件流程,展示了该系统图像处理算法运行周期的统计结果。该系统运行稳定可靠,具有较高的实用价值。     

基于ARM和FPGA的视频监控系统设计

设计并实现了一种基于ARM+FPGA的视频监控系统,以ARM9处理器为主控制器,FPGA为协处理器,构造ARM与FPGA间的高速数据传输通道和基于Linux的轻量级的图形驱动,完成实时视频采集和显示。实验结果表明,该设计能够流畅播放PAL/NTSC两种制式视频信号,具有良好的扩展性、稳定性和较快的响应速度。     

嵌入式粗颗粒度可重构处理器的软硬件协同设计流程

 面向多媒体应用的可重构处理器架构由主处理器和动态配置的可重构阵列(Reconfigurable Cell Array,RCA)组成.协同设计流程以循环流水线和流水线配置技术为基础,采用启发式算法对应用中较大的关键循环进行了软硬件划分,使用表格调度算法实现了任务在RCA上的映射.经过FPGA验证,H.264基准中的核心算法平均执行速度相比于PipeRench,MorphoSys,以及TI DSP TMS320C64X提高了3.34倍.     

Modbus通信协议的FPGA实现

Modbus协议是一个应用广泛的工业现场总线协议,鉴于其简单、开放、帧格式紧凑等优点,于2008年正式成为我国国家标准。介绍一种通过Cyclone系列FPGA实现Modbus RTU模式的方法,首先给出一个可以通用于Modbus主设备和从设备的协议接口单元,然后基于该接口设计了一个通用的Modbus从设备协处理器。实践证明该方法能够满足工业环境的通讯要求,此外,该方法在其他FPGA上也具有一定通用性和推广价值。     

红外电视跟踪器的数据处理系统设计

针对红外电视跟踪器对导弹等高速运动目标跟踪实时性的要求和数据流量大、处理速度高的特点,设计了基于DSP+FPGA架构的电视跟踪器数据处理系统.该系统采用高速数字信号处理器TMS32ODM642作为核心处理器完成目标的识别与跟踪,计算脱靶量信息;FPGA作为协处理器完成图像的采集和预处理.该系统能够完成对海面舰船目标和空...     

Design and implementation of an FPGA-based control IC forAC-voltage regulation

This paper presents a field-programmable gate army (FPGA)-based control integrated circuit (IC) for controlling the pulsewidth modulation (PWM) inverters used in power conditioning systems for AC-voltage regulation. We also propose a multiple-loop control scheme for this PWM inverter control IC to achieve sinusoidal voltage regulation under large load variations. The control scheme is simple in architecture and thus facilitates realization of the proposed digital controller for the PWM inverter using the FPGA-based circuit design approach. Bit-length effect of the digital PWM inverter controller has also been examined in this paper. The designed PWM inverter control IC has been realized using a single FPGA XC4005 from Xilinx Inc., which can be used as a coprocessor with a general-purpose microprocessor in application of AC-voltage regulation. Owing to the high-speed nature of FPGA, the sampling frequency of the constructed IC can be raised up to the range that cannot be reached using a conventional digital controller based merely on microcontrollers or a digital signal processor (DSP). Experimental results show the designed PWM inverter control IC using the proposed control scheme can achieve good voltage regulation against large load variations     

顺序形态图像处理器的硬件实现

该文在阐述了灰度图像顺序形态变换的基础上,介绍了顺序形态变换硬件实现的图像处理系统。该系统采用DSP+FPGA的框架结构,利用FPGA的可重构特性将其中一片FPGA作为协处理器可以实现不同的图像处理功能。文中将软硬件实现的顺序形态图像处理图片在处理效果和速度两个方面作了比较。算法在FPGA芯片上的高速实现特征使数学形态学在图像实时处理领域的应用成为可能。     

基于DSP+FPGA的实时视频信号处理系统设计

实时视频信号处理的实时性和跟踪算法的复杂性是一对矛盾,为此采用DSP+FPGA的架构设计,同时满足实时性和复杂性的要求,提高了系统的整体性能。DSP作为主处理器,利用其高速的运算能力,快速有效地处理复杂的跟踪算法;FPGA作为协处理器,完成视频图像的接收、存储、预处理,使设计具有更大的灵活性。系统采用了形心跟踪和相关跟踪两种算法。实验证明,该系统可以稳定地实时跟踪运动目标。     

基于SoC平台设计的H.264/AVC CAVLC解码器

提出了一种基于SoC平台的CAVLC解码器.在尽量减少时钟消耗的前提下,此解码器可以解码每个变换块中变换系数的熵编码码流,并将结果按照块扫描顺序并行输出.通过在XILJNX的ISE6.0 FPGA开发软件下仿真及分析表明,在120MHz时钟时可以满足10 Mb/s码率下H.264标准中Level3.0的性能要求.     

基于VCP的卷积码译码算法研究

目前,Viterbi译码算法主要是在DSP或FPGA中用软件算法来实现,算法复杂度高,译码效率低。针对此问题,介绍TI公司的TMS320C6416 DSP芯片上的维特比协处理(VCP)的结构与原理。对无线通信系统广泛采用的卷积码译码进行研究,用VCP单独进行译码,与DSP的数据交换可以采用增强型DMA(EDMA)来完成,从而用硬件方法实现并行处理,提高译码效率。仿真结果表明使用VCP译码可在降低运算量和占用资源的基础上取得良好系统性能。     

A Configurable Logic Based Architecture for Real-Time Continuous Speech Recognition Using Hidden Markov Models

An architecture is presented for real-time continuous speech recognition based on a modified hidden Markov model. The algorithm is adapted to the needs of continuous speech recognition by efficient encoding of the state space, and logarithmic encoding of the weights so that products can be computed as sums. The paper presents the algorithm and its application related modifications, the mapping of the algorithm to a special purpose architecture, and the detailed design of this architecture using configurable logic. Emphasis is given on how the attributes of the algorithm are exploited in a configurable logic based design. A concrete design example is presented with a coprocessor engine having one large FPGA, 64 Mbytes of synchronous DRAM (SDRAM), a small FPGA as a SDRAM controller, and 2 Mbytes SRAM. This engine operating at 66 MHz performs roughly nine times as fast as a high end personal computer running a fully optimized version of the same algorithm.     

Measuring and Modeling the Power Consumption of Energy-Efficient FPGA Coprocessors for GEMM and FFT

In this paper we analyze the power consumption and energy efficiency of general matrix-matrix multiplication (GEMM) and Fast Fourier Transform (FFT) implemented as streaming applications for an FPGA-based coprocessor card. The power consumption is measured with internal voltage sensors and the power draw is broken down onto the systems components in order to classify the energy consumed by the processor cores, the memory, the I/O links and the FPGA card. We present an abstract model that allows for estimating the power consumption of FPGA accelerators on the system level and validate the model using the measured kernels. The performance and energy consumption is compared against optimized multi-threaded software running on the POWER7 host CPUs. Our experimental results show that the accelerator can improve the energy efficiency by an order of magnitude when the computations can be undertaken in a fixed point format. Using floating point data, the gain in energy-efficiency was measured as up to 30 % for the double precision GEMM accelerator and up to 5 × for a 1k complex FFT.     

一种适用于智能卡应用的RSA协处理器

Based on the microprocessor structure,an RSA coprocessor for improved Montgomery algorithm has been designed．The functional units of this coprocessor operate concurrently,and up to three instructions can be issued in one cycle．A mixed form of three-stage and two-stage pipelined structure is used for instruction execution,and the coprocessor and CPU core can share a common RAM memory through a set of switches under control．The structure of the coprocessor can be expanded to contain more than one multiplier-accumulator units for higher performance．     

基于VLIW体系结构的椭圆曲线密码专用指令处理器

The requirement of the flexible and effective implementation of the Elliptic Curve Cryptography (ECC) has become more and more exigent since its dominant position in the public-key cryptography application. Based on analyzing the basic structure features of Elliptic Curve Cryptography (ECC) algorithms, the parallel schedule algorithm of point addition and doubling is presented. And based on parallel schedule algorithm, the Application Specific Instruction-Set Co-Processor of ECC that adopting VLIW architecture is also proposed in this paper. The coprocessor for ECC is implemented and validated using Altera’s FPGA. The experimental result shows that our proposed coprocessor has advantage in high performance and flexibility.     

A Special-Purpose Architecture for Solving the Breakpoint Median Problem

In this paper, we describe the design for a co-processor for whole-genome phylogenetic reconstruction. Our current design performs a parallelized breakpoint median computation, which is an expensive component of the overall application. When implemented on a field-programmable gate array (FPGA), our hardware breakpoint median achieves a maximum speedup of 1005$times$ over software. When the coprocessor is used to accelerate the entire reconstruction procedure, we achieve a maximum application speedup of 417$times$ . The results in this paper suggest that FPGA-based acceleration is a promising approach for computationally expensive phylogenetic problems, in spite of the fact that the involved algorithms are based on complex, control-dependent combinatorial optimization.      

红外小目标实时检测系统实现

采用TI的C6416为核心处理器,辅以FPGA,构建了一套红外小目标实时检测系统,主要算法由两片C6416并行处理实现,FPGA完成图像预处理和对外接口.算法上提出了基于双滑窗的局部阈值二值化方法,并采用图像预处理技术来改善图像分割效果,利用目标在连续帧间运动的关联性来剔除干扰目标、降低虚警概率.实验表明,系统的目标检测效果和实时性均达到了要求.     

SPI在TD-SCDMA/GSM双模移动开发平台中的应用

本文简要介绍了基于软件无线电技术的新型TD-SCDMA/GSM双模移动终端开发平台,该平台中的主要模块及FPGA作为协处理器在该平台中实现的功能。根据SPI的协议标准和在该平台中的通信协议要求,介绍了SPI在双模开发平台中的实现应用方法。设计中采用Verilog HDL语言并在Xilinx公司的Virtex-Ⅱ系列FPGA芯片内成功模拟出一个SPI接口,其仿真测试和实际应用均完全符合此双模平台通信的要求。     

基于FPGA和DSP的音视频采集处理系统设计

为了实时记录飞机飞行及作业过程中的各种信息,提出了一种基于FPGA和DSP的机载音视频采集处理系统。FPGA作为协处理器,完成对高清视频信号和音频信号的采集、解码以及格式的转换。DSP作为主处理器,在Linux系统的开发环境下,以视频H.264编码算法和音频G.711编码算法为核心完成了对音视频信号的压缩和存储。该系统性能稳定,实用性强,能够满足飞机飞行6小时的5路视频和2路音频信号的采集、存储和回放,达到了设计要求,具有一定的参考价值。