基于不完全分解预优共轭梯度法的电源和地线网络求解器

在超大规模集成电路的电源和地线网络的设计中,求解由该网络上每个节点的电压和每条边上的电流是最基本的运算,它对电源和地线网络拓扑结构设计和线宽优化算法的质量具有直接的影响.针对电源和地线网络的特殊性,提出了一个高效的电源和地线网络求解器,包括电路网络中树结构的合并与恢复和用不完全分解的预优共轭梯度法来求解节点电压方程.该求解器的运算速度很快,所耗费的内存很小,同时具有很强的鲁棒性.     

超深亚微米下快速电源网格节点电压求解器

提出了利用预处理器来提供强大的压缩节点功能,大大提高了电源网格节点电压求解器的求解能力和求解速度.实验证明,该求解器能处理大规模电路设计,速度快,精度高.     

超深亚微米下快速电源网格节点电压求解器

提出了利用预处理器来提供强大的压缩节点功能,大大提高了电源网格节点电压求解器的求解能力和求解速度.实验证明,该求解器能处理大规模电路设计,速度快,精度高     

基于等效电路降阶的电源/地线网络快速瞬态模拟

提出了一种电源/地线网络的快速时域分析方法.本算法在每一模拟时刻,首先离散化原始电路并且利用诺顿定律简化电路,继而针对电路中的链式结构的串联支路,提出了一种无误差的等效电路的模型降阶算法,将原始电路压缩为仅由交叉节点组成的电路.然后用预条件共轭梯度法求解被压缩的电路,最后恢复求解中间节点的电压值.有效地提高了算法的分析效率,在不损失精度的情况下,比目前工业界普遍采用的SPICE软件快两个数量级.     

基于等效电路降阶的电源/地线网络快速瞬态模拟

提出了一种电源/地线网络的快速时域分析方法.本算法在每一模拟时刻,首先离散化原始电路并且利用诺顿定律简化电路,继而针对电路中的链式结构的串联支路,提出了一种无误差的等效电路的模型降阶算法,将原始电路压缩为仅由交叉节点组成的电路.然后用预条件共轭梯度法求解被压缩的电路,最后恢复求解中间节点的电压值.有效地提高了算法的分析效率,在不损失精度的情况下,比目前工业界普遍采用的SPICE软件快两个数量级.     

BBL模式下电源/地线拓扑结构的设计与优化

在超大规模集成电路的设计中,BBL是一种新的具有良好发展前景的布图模式.对于这种模式下电源和地线的设计和优化,至今还没有很好的讨论.本文提出了一种针对BBL模式的高效电源/地线网络的设计与优化算法.该算法分为三个步骤:首先扫描出布线通道,然后按照几个布线原则和代价函数形成供电森林的拓扑结构,最后使用拉格朗日乘子法对线宽进行迭代优化以求得最小的布线面积.实验证明,该算法的运算速度很快,而且能够大幅度降低电源和地线所占用的布线资源,同时耗费的内存很小.     

压缩改进节点法及其应用

在改进节点法的基础上,提出了针对含有受控源的线性有源网络分析的压缩改进节点法,建立了对应的压缩改进节点电压方程。该方法不但克服了改进节点法对于含有VCVS、CCVS和无伴电压源的电路处理难度较大,甚至有时无法建立网络的节点电压方程的不足,而且解决了改进节点法中由于方程数目增加以及主对角元素出现零元素时所引起的求解困难。该方法概念清晰,列写过程简单,对于小型网络的分析具有一定的实用价值。     

基于DC/DC转换器的WSN节点电源模块设计

无线传感网络节点大多采用干电池供电,而干电池在使用过程中其输出电压持续下降导致节点供电电源不稳定,且不能充分利用电池内部所存储能量。本文的电源管理模块可对干电池的进行DC/DC转换,采用升压转换结构,高效率地实现额定电压输出。通过分析节点的工作特性,给出了元器件的选型方案。经实际测得数据分析,该模块的转换效率最高可达90%以上,极大地提高了电池的使用效率以及网络节点的能量利用率。同时由于该模块体积较小,便于与其他产品相结合,因此具有良好的扩展性和通用性。     

无线传感器网络节点太阳能电源系统设计

对于无线传感器网络节点而言,电源是系统的关键部分之一。在此提出一种收集环境中太阳能为传感器节点供能的电源系统。该系统采用了高效安全的充电控制技术,独特的电池电压监测电路,以及低功耗的DC—DC转换电路。通过实验验证,基于此太阳能电源的传感器节点功耗动态调整节性能好,生存周期显著增加。该系统可应用于各种户外监测的节点,如环境监测,精细农业,森林防火等。     

用CMOS/TTL兼容工艺实现的模拟乘除器

本文报道首次用发射区自对准CMOS/TTL兼容工艺实现的模拟四象限乘除器.实验测得这种乘除器在输入电压是电源电压1/3范围内具有非线性失真小于1％,偏离电压小至几毫伏和输入动态范围超过电源电压一半等特性.     

Supply Switching With Ground Collapse: Simultaneous Control of Subthreshold and Gate Leakage Current in Nanometer-Scale CMOS Circuits

Power gating has been widely used to reduce subthreshold leakage. However, the efficiency of power gating degrades very fast with technology scaling, which we demonstrate by experiment. This is due to the gate leakage of circuits specific to power gating, such as storage elements and output interface circuits with a data-retention capability. A new scheme called supply switching with ground collapse is proposed to control both gate and subthreshold leakage in nanometer-scale CMOS circuits. Compared to power gating, the leakage is cut by a factor of 6.3 with 65-nm and 8.6 with 45-nm technology. Various issues in implementing the proposed scheme using standard-cell elements are addressed, from register transfer level to layout. These include the choice of standby supply voltage with circuits that support it, a power network architecture for designs based on standard-cell elements, a current switch design methodology, several circuit elements specific to the proposed scheme, and the design flow that encompasses all the components. The proposed design flow is demonstrated on a commercial design with 90-nm technology, and the leakage saving by a factor of 32 is observed with 3% and 6% of increase in area and wirelength, respectively.     

Design of Symmetrical Class E Power Amplifiers for Very Low Harmonic-Content Applications

Class E power amplifier circuits are very suitable for high efficiency power amplification applications in the radio-frequency and microwave ranges. However, due to the inherent asymmetrical driving arrangement, they suffer significant harmonic contents in the output voltage and current, and usually require substantial design efforts in achieving the desired load matching networks for applications requiring very low harmonic contents. In this paper, the design of a Class E power amplifier with resonant tank being symmetrically driven by two Class E circuits is studied. The symmetrical Class E circuit, under nominal operating conditions, has extremely low harmonic distortions, and the design of the impedance matching network for harmonic filtering becomes less critical. Practical steady-state design equations for Class E operation are derived and graphically presented. Experimental circuits are constructed for distortion evaluation. It has been found that this circuit offers total harmonic distortions which are about an order of magnitude lower than those of the conventional Class E power amplifier.     

A realization of a high-frequency monolithic integrator with low power dissipation and its application to an active RC filter

According as the fine LSI process technique develops, the technique to reduce power dissipation of high-frequency integrated analog circuits is getting more important. This paper describes a design of high-frequency integrator with low power dissipation for monolithic leapfrog filters. In the design of the conventional monolithic integrators, there has been a great difficulty that a high-frequency integrator which can operate at low supply voltage cannot be realized without additional circuits, such as unbalanced-to-balanced conversion circuits and common-mode feedback circuits. The proposed integrator is based on the Miller integrator. By a PNP current mirror circuit, high CMRR is realized. However, the high-frequency characteristic of the integrator is independent of PNP transistors. In addition, it can operate at low supply voltage. The excess phase shift of the integrator is compensated by insertion of the compensation capacitance. The effectiveness of the proposed technique is confirmed by PSPICE simulation. The simulation results of the integrator shows that the common-mode gain is efficiently low and the virtual ground is realized, and that moderate phase compensation can be achieved. The simulation results of the 3rd-order leapfrog filter using the integrator shows that the 50 MHz-cutoff frequency filter is obtained. Its power dissipation in operating 2 V-supply voltage is 5.22 mW.     

Fast modeling of core switching noise on distributed LRC power gridin ULSI circuits

As technology scales, power supply noise caused by core logic switching becomes critical. Shorter signal rise edge, high integration density, and necessity of using on-chip decoupling capacitors require that the on-chip power distribution should be modeled as an LRC transmission line network with millions of switching devices. In this paper, we propose a sophisticated power grid model consisting of distributed LRC elements excited by constant voltage sources and switching capacitors. Based on this, fast equations for core switching noise estimations were formulated. Full-chip noise distribution on the power grid with any topology was efficiently and accurately computed. SPICE simulations confirmed its efficiency and accuracy. Experimental results obtained on our benchmark circuits revealed that the proposed technique speeded up simulations by several orders of magnitude compared with SPICE, whereas typical relative error was between 0±5%. By integrating a packaging model, the new model predicts accurately the upper boundaries of noise level for power bounce, ground bounce, and differential-mode power noise. Meanwhile, locations of hot spots in the power network are precisely identified. The model is suitable for full-chip rapid simulations for on-chip power distribution design in advanced ultra large scale integration (ULSI) circuits, particularly for early stage analysis, in which global and local optimization such as topology selection, power bus sizing, and on-chip decoupling capacitor placement can be easily conducted     

Analysis of power delivery network constructed by irregular-shaped power/ground plane including densely populated via-hole

The high speed and low power trend has imposed more and more importance on the design of the power distribution network (PDN) using multilayer printed circuit boards (PCBs) for modern microelectronic packages. This paper presents a fast and efficient analysis methodology in frequency domain for the design of a PDN with a power/ground plane pair, which considers the effect of irregular shape of the power/ground plane and densely populated via-holes. The presented method uses parallel-plate transmission line theory with equivalent circuit model of unit-cell grid considering three-dimensional geometric boundary conditions. Characteristics of PDNs implemented by perforated planes including a densely populated via-hole structure is quantitatively determined based on full-wave analysis using the finite-difference time-domain (FDTD) periodic structure modeling method and full-wave electromagnetic field solver. Using a circuit simulator such as popularly used SPICE and equivalent circuit models for via-hole structure and perforations, the authors have analyzed input-impedance of the power/ground plane pair. Since the presented method gives an accurate and fast solution, it is very useful for an early design of multilayer PCBs.     

Ternary CAM Power and Delay Model: Extensions and Uses

Applications in computer networks often require high throughput access to large data structures for lookup and classification. While advanced algorithms exist to speed these search primitives on network processors and even custom application-specific integrated circuits (ASICs), achieving tight bounds on worst case performance with standard memories often requires a very careful analysis of all possible access patterns. An alternative, and often times more simple solution, is possible if a ternary CAM (TCAM) is used to perform a fully parallel search across the entire data set. Unfortunately, this parallelism means that large portions of the chip are switching during each cycle, causing large amounts of power to be consumed. While researchers at all levels of design (from algorithms to circuits) have begun to explore new ways of managing the power consumption, quantifying design alternatives is difficult due to a lack of available models. In this paper, we examine the structure of a modern TCAM and present a simple, yet accurate, power and delay model. We present techniques to estimate the dynamic power consumption and leakage power of a TCAM structure and validate the model using a combination of industrial TCAM datasheets and prior published works. Such a model is a critical first step in bridging the intellectual divide between circuit-level and algorithm-level optimizations. To demonstrate the utility of our model, we present an extensive analysis of the model by varying various architectural parameters and describe how our model can be easily extended to handle several circuit optimizations in the TCAM structure. In addition, we present a comparative study of SRAM and TCAM energy consumption to directly quantify the many design options which will be very useful for network designers to explore various power management schemes.     

应用于配电网单相接地在线故障指示器电源

配电网单向接地故障指示器在配电网自动化方面应用广泛,但其在线故障诊断所需的能量不能靠低压侧供给,只能在高压端获取,因此文中设计了特殊的取电电路和控制电路,根据故障指示器各个元器件的需求,此取能电源可以为故障指示器提供5V、-4V和3．2V3路电压,以满足故障指示器信号采集和处理以及无线通信的需要。整机实验结果表明,该取能电源在15—800A的变化范围内,能提供不少于1．5W的功率,可满足故障指示器的需要。     

Estimation of high performance in Schmitt triggers with stacking power‐gating techniques in 45 nm CMOS technology

In the complementary metal oxide semiconductor (CMOS) nanoscale technology ground bounce noise and power consumption are becoming important metric. In presented paper, low leakage Schmitt trigger circuits are proposed for wave shaping or cleaning process with low ground bounce noise. Schmitt trigger play important role in communication electronics. Power‐gating and stacking power‐gating techniques have provided for maintaining the parameter of Schmitt trigger. An ideal approach has been investigated with stacking power‐gating technique. For further reduction in peak of ground bounce noise during sleep to active (power) mode transition, we have performed simulations using cadence specter 45 nm standard CMOS technology at nominal temperature (27°C) with supply voltage V_dd = 0.7 V and input voltage vary from 0.7 V to 1.5 V. The simulation results show that a proposed design provide efficient 6 T and 4 T Schmitt triggers in term of minimum leakage power (8.18 fW), active power (17.80 pW), ground bounce noise (1.65 μV) and propagation delay (1.98 ns), transconductance (4.51 × 10^?14 S), voltage gain (29.44 dB), hysteresis width (11.07 V) and efficiency (64.68%). Reported devices use for low‐power communication systems. Copyright © 2013 John Wiley & Sons, Ltd.     

Pass transistor with dual threshold voltage domino logic design using standby switch for reduced subthreshold leakage current

Dual threshold voltages domino design methodology utilizes low threshold voltages for all transistors that can switch during the evaluate mode and utilizes high threshold voltages for all transistors that can switch during the precharge modes. We employed standby switch can strongly turn off all of the high threshold voltage transistors which enhances the effectiveness of a dual threshold voltage CMOS technology to reduce the subthreshold leakage current. Subthreshold leakage currents are especially important in burst mode type integrated circuits where the majority of the time for system is in an idle mode. The standby switch allowed a domino system enters and leaves a low leakage standby mode within a single clock cycle. In addition, we combined domino dynamic circuits style with pass transistor XNOR and CMOS NAND gates to realize logic 1 output during its precharge phase, but not affects circuits operation in its evaluation and standby phase. The first stage NAND gates output logic 1 can guarantee the second stage computation its correct logic function when system is in a cascaded operation mode. The processing required for dual threshold voltage circuit configuration is to provide an extra threshold voltage involves only an additional implant processing step, but performs lower dynamic power consumption, lower delay and high fan-out, high switching frequencies circuits characteristics. SPICE simulation for our proposed circuits were made using a 0.18 µm CMOS process from TSMC, with 10 fF capacitive loads in all output nodes, using the parameters for typical process corner at 25 °C, the simulation results demonstrated that our designed 8-bit carry look-ahead adders reduced chip area, power consumption and propagation delay time more than 40%, 45% and around 20%, respectively. Wafer based our design were fabricated and measured, the measured data were listed and compared with simulation data and prior works. SPICE simulation also manifested lower sensitivity of our design to power supply, temperature, capacitive load and process variations than the dynamic CMOS technologies.     

TMS320C6678 DSP的电源设计

针对TI公司最新发布的TMS320C6678 DSP设计出一种实用有效的电源。采用统一的12 V电源供电,制作出满足电压幅值要求与时序要求的开关电源。该设计主要由各类电源转换电路组成,并通过使用Fusion Digital PowerDesigner软件对电源芯片进行编程。仿真结果表明,该电源工作稳定,各方面的参数均符合要求。