利用双低温缓冲层和插入应变超晶格技术制备高质量InP-on-GaAs复合衬底的MOCVD生长

提出一种结合双低温缓冲层和应变超晶格优势的高质量InP-on-GaAs复合衬底制备技术. 研究发现LT-InP/LT-GaAs的双低温缓冲层比单一低温InP缓冲层的聚集应变的效果更为显著. 并且,双低温缓冲层中的低温GaAs层存在一个最优生长厚度. 当低温InP生长厚度一定,低温GaAs层的生长厚度达到优化生长厚度时,LT-InP/LT-GaAs双低温缓冲层能达到调节应变的最佳状态. 最后,通过插入InGaP/InP应变超晶格,并且优化其在外延层中的插入位置,得到了高质量的InP-on-GaAs的复合衬底,2μm厚的InP外延层XRD-ω/2θ扫描的半高宽小于200" .     

基于异变缓冲层与应变层超晶格的InP/GaAs异质外延

利用低压金属有机化学气相沉积技术, 开展InP/GaAs异质外延实验。由450 ℃生长的低温GaAs层与超薄低温InP层组成双异变缓冲层, 并进一步在正常InP外延层中插入In1-xGaxP/InP(x=7.4%)应变层超晶格。在不同低温GaAs缓冲层厚度、应变层超晶格插入位置及应变层超晶格周期数等条件下, 详细比较了InP外延层(004)晶面的X射线衍射谱, 还尝试插入双应变层超晶格。实验中, 1.2 μm和2.5 μm厚InP外延层的ω扫描曲线半峰全宽仅370 arcsec和219 arcsec; 在2.5 μm厚InP层上生长了10周期In0.53Ga0.47As/InP 多量子阱, 室温PL谱峰值波长位于1625 nm, 半峰全宽为60 meV。实验结果表明, 该异质外延方案有可能成为实现InP-GaAs单片光电子集成的一种有效途径。     

GaAs衬底上InP的直接外延生长及性能表征

用低压金属有机物气相外延(LP-MOCVD)技术,采用低温缓冲层生长法,在GaAs(100)衬底上直接生长了高质量的InP外延层.1.2 μm InP(004)面X射线衍射(XRD) ω-2θ和ω扫描半高全宽(FWHM)分别为373 arcsec和455 arcsec,在外延层中插入10周期Ga0.1In0.9P/InP应变超晶格后,其半高全宽分别下降为338 arcsec和391 arcsec.透射电子显微镜(TEM)测试显示,应变超晶格有效地抑制了失配位错穿进外延层,表明晶体质量得到了较大提高.     

InP/GaAs异质外延及异变InGaAs光探测器制备

借助超薄低温InP缓冲层,在GaAs衬底上生长出了高质量的InP外延层,在InP外延层中插入了15周期In0.93Ga0.07P/InP应变层超晶格(SLS),进一步阻断了失配位错穿透到晶体表面,提高了外延层的晶体质量,这样2.5 μm厚InP外延层的双晶X射线衍射(DCXRD)ω扫描半高全宽(FWHM)值降低至219 arcsec,该InP外延层的室温光荧光(PL)谱线宽度仅为42 meV.在此基础上,只利用超薄低温InP缓冲层技术就在半绝缘GaAs衬底上成功地制备出了长波长异变In0.53Ga0.47As PIN光电探测器,器件的台面面积为50 μm×50 μm,In0.53Ga0.47As吸收层厚度为300 nm,在3 V反偏压下器件的3 dB带宽达到了6 GHz,在1 550 nm波长处器件的响应度达到了0.12 A/W,对应的外量子效率为9.6%.     

基于MOCVD的InP/GaAs异质外延生长

使用金属有机物气相沉积方法(MOCVD),在GaAs衬底上生长InP外延层.先在GaAs衬底上生长一层低温InP缓冲层,然后再生长InP外延层.通过比较不同缓冲层生长条件下的外延层晶体质量,发现在生长温度为450℃,厚度约15nm的缓冲层上外延所得到的晶体质量最理想;此外,外延层厚度的增加对其晶体质量有明显改善作用.实验在优化生长条件的同时,也考虑了热退火等辅助工艺,最后所获得的外延层的双晶X射线衍射(DCXRD)的ω/2θ扫描外延峰半高全宽(FWHM)值为238.5".     

基于MOCVD的InP/GaAs异质外延生长

使用金属有机物气相沉积方法(MOCVD),在GaAs衬底上生长InP外延层.先在GaAs衬底上生长一层低温InP缓冲层,然后再生长InP外延层.通过比较不同缓冲层生长条件下的外延层晶体质量,发现在生长温度为450℃,厚度约15nm的缓冲层上外延所得到的晶体质量最理想;此外,外延层厚度的增加对其晶体质量有明显改善作用.实验在优化生长条件的同时,也考虑了热退火等辅助工艺,最后所获得的外延层的双晶X射线衍射(DCXRD)的ω/2θ扫描外延峰半高全宽(FWHM)值为238.5".     

基于低温In_xGa_(1-x)P组分渐变缓冲层的InP/GaAs异质外延

采用低温GaAs与低温组分渐变InxGa1-xP作为缓冲层,利用低压金属有机化学气相外延(LP-MOCVD)技术,在GaAs(001)衬底上进行了InP/GaAs异质外延实验。实验中,InxGa1-xP缓冲层选用组分线性渐变生长模式(xIn0.49→1)。通过对InP/GaAs异质外延样品进行双晶X射线衍射(DCXRD)测试,并比较1.2μm厚InP外延层(004)晶面ω扫描及ω-2θ扫描的半高全宽(FWHM),确定了InxGa1-xP组分渐变缓冲层的最佳生长温度为450℃、渐变时间为500s。由透射电子显微镜(TEM)测试可知,InxGa1-xP组分渐变缓冲层的生长厚度约为250nm。在最佳生长条件下的InP/GaAs外延层中插入生长厚度为48nm的In0.53Ga0.47As,并对所得样品进行了室温光致发光(PL)谱测试,测试结果表明,中心波长为1643nm,FWHM为60meV。     

基于低温缓冲层的单片集成长波长可调谐光探测器

实现了一种单片集成的长波长可调谐光探测器.通过外延实验,摸索出低温缓冲层的最佳生长条件,成功地在GaAs衬底上生长出晶格失配度约4%的高质量的InP基材料.基于此低温缓冲层,在GaAs衬底上首先生长GaAs/AlAs材料的F-P腔滤波器,然后异质外延InP-In0.53 Ga0.47 As-InP材料的PIN结构.制作出的器件通过热调谐,峰值波长从1533.1nm红移到1543.1nm,实现了10.0nm的调谐范围,同时响应线宽维持在0.8nm以下,量子效率保持在23%以上,响应速率达到6.2GHz.     

基于低温缓冲层的单片集成长波长可调谐光探测器

实现了一种单片集成的长波长可调谐光探测器.通过外延实验,摸索出低温缓冲层的最佳生长条件,成功地在GaAs衬底上生长出晶格失配度约4%的高质量的InP基材料.基于此低温缓冲层,在GaAs衬底上首先生长GaAs/AlAs材料的F-P腔滤波器,然后异质外延InP-In0.53 Ga0.47 As-InP材料的PIN结构.制作出的器件通过热调谐,峰值波长从1533.1nm红移到1543.1nm,实现了10.0nm的调谐范围,同时响应线宽维持在0.8nm以下,量子效率保持在23%以上,响应速率达到6.2GHz.     

用于单片集成光接收机前端的GaAs基InP/InGaAs HBT

实现了一种可用于单片集成光接收机前端的GaAs基InP/InGaAs HBT。借助超薄低温InP缓冲层在GaAs衬底上生长出了高质量的InP外延层。在此基础上,只利用超薄低温InP缓冲层技术就在半绝缘GaAs衬底上成功制备出了InP/InGaAsHBT,器件的电流截止频率达到4.4GHz,开启电压0.4V,反向击穿电压大于4V,直流放大倍数约为20。该HBT器件和GaAs基长波长、可调谐InP光探测器单片集成为实现适用于WDM光纤通信系统的高性能、集成化光接收机前端提供了一种新的解决方法。     

TEM study of dislocations structure in In0.82Ga0.18As/InP heterostructure with InGaAs as buffer layer

In order to improve the quality of detector, InxGa1-xAs (x=0.82) buffer layer has been introduced in In0.82Ga0.18As/InP heterostructure. Dislocation behavior of the multilayer is analyzed through plane and cross section [110] by transmission electron microscopy (TEM) and high resolution transmission electron microscopy (HRTEM). The dislocations are effectively suppressed in InxGa1-xAs (x=0.82) buffer layer, and the density of dislocations in epilayer is reduced obviously. No lattice mismatch between buffer layer and epilayer results in no misfit dislocation (MD). The threading dislocations (TDs) are directly related to the multiplication of the MDs in buffer layer.     

Low threading dislocation density GaAs on Si(100) with InGaAs/GaAs strained-layer superlattice grown by migration-enhanced epitaxy

This paper reports a promising approach for reducing the density of threading dislocations in GaAs on Si. In _x Ga_1-x As/GaAs strained-layer superlattices (SLSs) grown by migration-enhanced epitaxy at 300° C on GaAs/Si acted as barriers to threading dislocations. Unlike conventional high-temperature-grown SLSs, the low-temperature-grown SLSs were hardly relaxed by the formation of misfit dislocations at GaAs/SLS interfaces, and this allowed them to accumulate considerable strain. New threading dislocation generation due to the misfit dislocation was also suppressed. These factors caused effective bending of threading dislocations and significantly reduced the dislocation density. For the samples that had an SLS withx = 0.3, the average etch-pit density was 7 × 10⁴ cm^-2, which is comparable to that of GaAs substrates.     

Comparison of Continuously- and Step-Graded ZnS y Se1−y /GaAs (001) Metamorphic Buffer Layers

The design of metamorphic buffer layers for semiconductor devices with reduced defect densities requires control of lattice relaxation and dislocation dynamics. Graded layers are beneficial for the design of these buffers because they reduce the threading dislocation density by (1) allowing the distribution of the misfit dislocations throughout the buffer layer therefore reducing pinning interactions, and (2) enhancing mobility from the high built-in surface strain which helps to sweep out threading arms. In this work, we considered heterostructures involving a linearly-graded (type A) or step-graded (type B) buffer grown on a GaAs (001) substrate. For each structure type, we studied the equilibrium configuration and the kinetically-limited lattice relaxation and non-equilibrium threading dislocations by utilizing a dislocation dynamics model. In this work, we have also considered heterostructures involving a constant composition ZnS _y Se_1?y device layer grown on top of a GaAs (001) substrate with an intermediate buffer layer of linearly-graded (type C) or step-graded (type D) ZnS _y Se_1?y . For each structure type, we studied the requirements on the thickness and compositional profile in the buffer layer for the elimination of all mobile threading dislocations from the device layer by the dislocation compensation mechanism.     

Effects of high-temperature AIN buffer on the microstructure of AlGaN/GaN HEMTs

Effects on AlGaN/GaN high-electron-mobility transistor structure of a high-temperature AlN buffer on sapphire substrate have been studied by high-resolution x-ray diffraction and atomic force microscopy techniques. The buffer improves the microstructural quality of GaN epilayer and reduces approximately one order of magnitude the edge-type threading dislocation density. As expected, the buffer also leads an atomically flat surface with a low root-mean-square of 0.25 nm and a step termination density in the range of 10⁸ cm^?2. Due to the high-temperature buffer layer, no change on the strain character of the GaN and AlGaN epitaxial layers has been observed. Both epilayers exhibit compressive strain in parallel to the growth direction and tensile strain in perpendicular to the growth direction. However, an high-temperature AlN buffer layer on sapphire substrate in the HEMT structure reduces the tensile stress in the AlGaN layer.     

Design of Dislocation-Compensated ZnS y Se1−y /GaAs (001) Heterostructures

The understanding of lattice relaxation and dislocation dynamics in lattice-mismatched semiconductors makes it possible to design metamorphic device structures utilizing the dislocation compensation mechanism for reduced defects, improved performance, and enhanced reliability. We have developed a dislocation dynamics model accounting for misfit–threading interactions and have applied it to ZnS _y Se_1?y /GaAs (001) heterostructures.1 Dislocation compensation involves the removal of threading dislocations associated with one sense of misfit dislocations by bending them over to create misfit dislocations of the opposite sense at an intentionally mismatched interface. Here we investigated the design of dislocation-compensated ZnS _y Se_1?y /GaAs (001) heterostructures and considered the sulfur mole fraction tolerances applicable to such structures. We considered two types of structures: type A involved a uniform-composition (ungraded) layer on top of a uniform-composition buffer, while type B involved a uniform-composition layer on a linearly graded buffer. For each structure type we studied the requirements on the thickness and compositional profile of the buffer layer to optimize the removal of mobile threading dislocations from the top uniform (device) layer as well as the allowed tolerance in compositional overshoot to achieve structures with low threading dislocation density. We show for both types of structure that (i) for given compositional overshoot at the buffer–device layer interface, there is an optimum buffer thickness which minimizes the dislocation density; and (ii) for given buffer thickness there is an optimum overshoot which minimizes the dislocation density.     

Dislocation density reduction in GaAs epilayers on Si using strained layer superlattices

Defects such as dislocations and interfaces play a crucial role in the performance of heterostructure devices. The full potential of GaAs on Si heterostructures can only be realized by controlling the defect density. The reduction of threading dislocations by the use of strained layer superlattices has been studied in these heterostructures. Several superlattice structures have been used to reduce the density of threading dislocations in the GaAs epilayer. In this study, we have optimized the use of strained layer superlattices with respect to the position, period and number to reduce and control the dislocation density. The use of strained layer superlattices in conjunction with rapid thermal annealing was found to be a most effective method for reducing the threading dislocation density. Transmission electron microscopy has been used to study the dislocation density reduction and the interaction of threading dislocations with the strained layers. A model has been developed based on energy considerations to determine the critical thickness required for the bending of threading dislocations.     

Si间隔层对利用低温Si缓冲层生长高弛豫SiGe层的影响

利用低温生长Si缓冲层与Si间隔层相结合的方法生长高弛豫SiGe层,研究了Si间隔层在其中的作用. 利用化学腐蚀和光学显微镜，观察了不同外延层厚度处位错的腐蚀图样. 研究了不同温度下生长的Si间隔层对SiGe外延层中位错形成、传播及其对应变弛豫的影响. 结果表明Si间隔层的引入，显著改变了外延层中位错的形成和传播，进而使得样品表面形貌也呈现出较大的差异.