共查询到19条相似文献,搜索用时 685 毫秒
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介绍了一个200kHz信号带宽、用于低中频结构GSM射频接收机的高精度ΣΔ调制器. 为了达到高线性和稳定性,调制器采用2-1级联单比特的结构实现. 电路在0.18μm CMOS工艺下流片验证,核心面积为0.5mm×1.1mm. 调制器工作在19.2MHz的采样频率,在3V电源电压下功耗为5.88mW. 测试结果表明,在200kHz信号带宽,过采样率为64的条件下,调制器达到84.4dB动态范围,峰值SNDR达到73.8dB,峰值SNR达到80dB. 相似文献
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实现了一种适用于信号检测的低功耗∑-△调制器.调制器采用2阶3位量化器结构,并使用数据加权平均算法降低多位DAC产生的非线性.调制器采用TSMC 0.18 μm混合信号CMOS工艺实现.该调制器工作于1.8V电源电压,在50 kHz信号带宽和12.8 MHz采样频率下,整体功耗为3 mW,整体版图尺寸为1.25 mm×1.15 mm.后仿真结果显示,在电容随机失配5‰的情况下,该调制器可以达到91.4 dB的信噪失真比(SNDR)和93.6 dB的动态范围(DR). 相似文献
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设计了一个用于GSM系统的Sigma-Delta调制器.GSM系统要求信号带宽大于200 kHz,动态范围大于80dB.为了能取得较低的过采样率以降低功耗,采用了级联结构(MASH)来实现,与单环高阶结构相比,它具有稳定及易于实现的优点.设计工作时钟为16MHz,过采样率为32,基带带宽为250 kHz,电路仿真可以达到最高82dB的SNDR和87dB的动态范围.芯片采用SMIC 0.18μm工艺进行流片,面积为1.2mm×1.8mm.芯片测试效果最高SNDR=74.4dB,动态范围超过80dB,测试结果与电路仿真结果相近,达到了预定的设计目标.芯片工作在1.8V电源电压下,功耗为16.7mW. 相似文献
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设计了一个用于GSM系统的Sigma-Delta调制器.GSM系统要求信号带宽大于200 kHz,动态范围大于80dB.为了能取得较低的过采样率以降低功耗,采用了级联结构(MASH)来实现,与单环高阶结构相比,它具有稳定及易于实现的优点.设计工作时钟为16MHz,过采样率为32,基带带宽为250 kHz,电路仿真可以达到最高82dB的SNDR和87dB的动态范围.芯片采用SMIC 0.18μm工艺进行流片,面积为1.2mm×1.8mm.芯片测试效果最高SNDR=74.4dB,动态范围超过80dB,测试结果与电路仿真结果相近,达到了预定的设计目标.芯片工作在1.8V电源电压下,功耗为16.7mW. 相似文献
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A new ∑Δ modulator architecture for thermal vacuum sensor ASICs is proposed.The micro-hotplate thermal vacuum sensor fabricated by surface-micromachining technology can detect the gas pressure from 1 to 105 Pa.The amplified differential output voltage signal of the sensor feeds to the ∑Δ modulator to be converted into digital domain.The presented ∑Δ modulator makes use of a feed-forward path to suppress the harmonic distortions and attain high linearity.Compared with other feed-forward architectures presented before,the circuit complexity,chip area and power dissipation of the proposed architecture are significantly decreased.The correlated double sampling technique is introduced in the 1st integrator to reduce the flicker noise.The measurement results demonstrate that the modulator achieves an SNDR of 79.7 dB and a DR of 80 dB over a bandwidth of 7.8 kHz at a sampling rate of 4 MHz.The circuit has been fabricated in a 0.5μm 2P3M standard CMOS technology.It occupies an area of 5 mm2 and dissipates9 mW from a single 3 V power supply.The performance of the modulator meets the requirements of the considered application. 相似文献
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Xu Xiaomei 《电子科学学刊(英文版)》2002,19(3)
An anti-aliasing filter for ∑△ ADCs using a combination of active RC and analog FIR filters is presented in this letter. The first order active RC filter is set at 100kHz to minimize the die size and variations of linear phase and gain in 0-4kHz passband. The 2-tap FIR filter provides more than -53dB attenuation at 2MHz ±4kHz frequency range. The proposed filter achieved more than -76dB attenuation at sampling frequency with ±0.01° phase linearity and ±0.02dB gain variation within 0-4kHz bandwidth. The active die area of the fully differential filter is 0.17mm2 in 0.5μm CMOS technology. The experimental and simulation results have been obtained and the feasibility of the proposed method is shown. 相似文献
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A sixth-order cascaded sigma-delta modulator isreported aiming low power data-converter architectures.Behavioral simulation shows that the cascaded (2-1-1-2)architecture is the most robust in terms of noiseperformance and accuracy. A prototype of this architecture was fabricated using a 2 m analogCMOS process. Measured results indicate that the modulator achieved 89 dB (14.8-b) peak in-bandsignal-to-noise ratio (SNR) and 92 dB (15.3-b) dynamicrange (DR) for a 32 kHz bandwidth, at a sampling rate ofonly 1 MHz. The modulator dissipated 79 mW from a±3.3 V supply voltage and only 45 mW from a±2.5 V supply voltage with negligible SNRdeterioration. Process scaling and supply-voltagescaling can thus drastically reduce power dissipationusing this architecture while maintaining high SNR andDR performance. 相似文献
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This paper presents a 1.1 mW 87 dB dynamic range third order AS modulator implemented in 0.18 μm CMOS technology for audio applications.By adopting a feed-forward multi-bit topology,the signal swing at the output of the first integrator can be suppressed.A simple current mirror single stage OTA with 34 dB DC gain working under 1 V power supply is used in the first integrator.The prototype modulator achieves 87 dB DR and 83.8 dB peak SNDR across the bandwidth from 100 Hz to 24 kHz with 3 kHz input signal. 相似文献
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采用TSMC0.18μm CMOS混合信号1P6M工艺实现了一种应用于信号检测系统的低功耗Delta--Sigma调制器.该调制器采用单环积分器级联反馈(CIFB)结构降低了电路的复杂度,并采用Chopper-Stabilization技术降低了系统的直流失调和1/f噪声,提高了电路的低频特性.调制器采用1.8V电源电压,整体功耗仅为2mW,版图尺寸1.25×1.3mm^2.仿真结果表明,该调制器在50kHz信号带宽范围内,可以达到92dB的信噪失真比,99.3dB的动态范围和15bits的有效位数,满足传感器信号检测系统的要求. 相似文献
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实现了一种适用于信号检测的低功耗Σ-Δ调制器。调制器采用2阶3位量化器结构,并使用数据加权平均算法降低多位DAC产生的非线性。调制器采用TSMC 0.18μm混合信号CMOS工艺实现。该调制器工作于1.8V电源电压,在50kHz信号带宽和12.8MHz采样频率下,整体功耗为3mW,整体版图尺寸为1.25mm×1.15mm。后仿真结果显示,在电容随机失配5‰的情况下,该调制器可以达到91.4dB的信噪失真比(SNDR)和93.6dB的动态范围(DR)。 相似文献
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Very low-voltage digital-audio ΔΣ modulator with 88-dBdynamic range using local switch bootstrapping
A 1-V 1-mW 14-bit ΔΣ modulator in a standard CMOS 0.35-μm technology is presented. Special attention has been given to device reliability and power consumption in a switched-capacitor implementation. A locally bootstrapped symmetrical switch that avoids gate dielectric overstress is used in order to allow rail-to-rail signal switching. The switch constant overdrive also enhances considerably circuit linearity. Modulator coefficients of a single-loop third-order topology have been optimized for low power. Further reduction in the power consumption is obtained through a modified two-stage opamp. Measurement results show that for an oversampling ratio of 100, the modulator achieves a dynamic range of 88 dB, a peak signal-to-noise ratio of 87 dB and a peak signal-to-noise-plus-distortion ratio of 85 dB in a signal bandwidth of 25 kHz 相似文献
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A fractional-N frequency synthesizer fabricated in a 0.13 μm CMOS technology is presented for the application of IEEE 802.11 b/g wireless local area network (WLAN) transceivers.A monolithic LC voltage controlled oscillator (VCO) is implemented with an on-chip symmetric inductor.The fractional-N frequency divider consists of a pulse swallow frequency divider and a 3rd-order multistage noise shaping (MASH) △ ∑ modulator with noise-shaped dithering techniques.Measurement results show that in all channels,phase noise of the synthesizer achieves -93 dBc/Hz and -118 dBc/Hz in band and out of band respectively with a phase-frequency detector (PFD) frequency of 20 MHz and a loop bandwidth of 100 kHz.The integrated RMS phase error is no more than 0.8°.The proposed synthesizer consumes 8.4 mW from a 1.2 V supply and occupies an area of 0.86 mm2. 相似文献