A VLSI demodulator for digital RF network applications: theory andresults

An all-digital demodulator/detector which is suitable for both analog FM and digital phase/frequency modulations is presented. The system uses complex sampling, which employs a single A/D (analog/digital) converter to sample the signal at an intermediate frequency (IF) and produce baseband in-phase (I) and quadrature phase (Q) signals, and a simplified technique for reducing the effect of the I/Q timing misalignment usually associated with this approach. The system also includes two detectors which operate simultaneously to provide noncoherent and differentially coherent detection, as well as automatic gain control (AGC) and automatic frequency control (AFC). The flexibility afforded by the two concurrent detectors in this all-digital system is shown to make it suitable for a wide range of applications. The theory behind the demodulator/detector system is described, and an implementation using a 1.25-μm bulk CMOS VLSI process is presented. Methods are shown for extending and improving the I/Q sampling misalignment correction technique, as well as for reducing the A/D sampling rate for a given IF frequency. Simulation and experimental results illustrate system performance for both analog and digital modulations     

Variable-delay, sine/cosine noncoherent detector

The letter describes an all-digital, noncoherent demodulator suitable for the detection of CPFSK and PSK signalling schemes. A single A/D convertor demodulates the input signal and generates baseband in-phase (I) and quadrature (Q) signals. The I and Q signals are then processed with sine and cosine detectors to produce AFC information and the regenerated transmit data.     

A frequency agile monolithic QPSK modulator with spectral filteringand 75 Ω differential line driver

This monolithic modulator combines both digital signal processing and analog techniques to realize a high bit-rate quadrature phase-shift keyed (QPSK) modulator. It includes a digital baseband pulse shaping network, analog quadrature modulator, agile carrier generator, spectral shaping, and transmit power control for interfacing to wireline transmission media. Nominal data rates are 256 kbit/s with a carrier range of 8.096-20.128 MHz in 32 kHz steps. Maximum output level is 62 dBmV into a 75 Ω load. The features of 1.2 μm mixed signal BiCMOS technology permit both signal processing and power line drivers to be collocated while achieving better than 85 dB cross-talk isolation     

一种改进结构的数字混频正交变换法

数字正交解调器是软件无线电（SDR）接收机的重要部件,数字混频正交变换法是实现正交解调器的常用算法。本文针对软件无线电中传统数字混频正交变换法算法,根据理论推导,提出一种适用于多频段中频信号的改进结构的数字混频正交变换法。该改进算法将正交解调与低通滤波两个过程结合在一起实现,并且每输入M个输入采样值做一次输出滤波。通过分析和在可编程器件FPGA上的实验表明,该新结构完全实现了数字混频正交变换法,且能较大地减少所占用的FPGA上的RAM和乘法器资源,在相同的FPGA资源条件下,可以较大地提高中频数字正交解调器的邻道隔离性能,或者大幅度提高所允许的前端模数采样器（ADC）的采样频率。      

A frequency-agile single-chip QAM modulator with beamformingdiversity

Architecture and circuit design techniques for VLSI implementation of a single-chip quadrature amplitude modulation (QAM) modulator with frequency agility and antenna beamforming characteristics are presented. In order to achieve reliable wireless communication modem function, the single chip all-digital QAM modulator implements various features, including high data rates with bandwidth efficiency, flexibility, meeting a wide variety of user throughput requirements with variable and width and data rates in a multi-user system, and robustness, incorporating diversity and redundancy techniques to guarantee robust communication for various operating environments. The modulator components consist of several digital processing building blocks, including various finite-impulse-response (FIR) filters, an innovative variable interpolation filter, a four-channel frequency translator with quadrature mixer for antenna beamforming diversity, a quadrature direct digital frequency synthesizer (QDDFS), a numerically controlled oscillator (NCO), a QAM formatter, a pseudorandom noise (PN) generator, an x/sinx filter, and a microcontroller interface. An optimized architecture and chip implementation for the variable modulator is derived and evaluated which will support symbol rates from 6 kBaud to 8.75 MBaud continuously and digitally flexible IF frequencies up to 70 MHz with four-channel antenna beamforming function     

Nonobvious correlation properties of quadrature GMSK, a modulationtechnique adopted worldwide

GMSK is the world's most widely used modulation technique for mobile digital telephony and digital wireless applications. We describe two GMSK modulator structures, the voltage controlled oscillator (VCO) and the quadrature modulator structure. The tremendous advantages of the quadrature modulator structure for practical GMSK modulator implementations are emphasized. We present the results of computer simulations and hardware experimental measurements performed on GSM-standardized IC chips which are used by several million subscribers in order to illustrate the operation of a GMSK modulator. Since quadrature modulator structures are used in nearly all practical GMSK chipsets, the properties of this structure are of wide interest. In this paper we highlight the crosscorrelation properties of the GMSK in-phase and quadrature-phase baseband signals, which are part of the quadrature modulator structure. While uncorrelated in-phase and quadrature-phase baseband signals are used in traditional QPSK and OQPSK modulated systems, we demonstrate that there is strong crosscorrelation between the in-phase and quadrature-phase baseband signals. The crosscorrelation is stronger if the observation interval is shorter. Nonobvious quadrature modulator/radio crosscorrelation advantages were patented by Kato/Feher (1986). Design with crosscorrelated quadrature transmitter is “contrary to the wisdom of classical linear communications theory”. Crosscorrelated quadrature modulated systems include FQPSK-KF and GMSK     

A 270-kb/s 35-mW modulator IC for GSM cellular radio hand-heldterminals

The modulator IC is a mixed analog/digital transceiver component in a chip set that is designed for the hand-held terminals of the pan-European 900-MHz Groupe Special Mobile (GSM) digital cellular radio network. The concept of the radio-frequency environment in which the circuit is used is explained, focusing on the differences in existing systems. The architecture and different functions of the modulator circuit and details of the digital and analog processing in the transmission mode are discussed. The receiving mode, which is mostly based on analog processing, is highlighted. The device generates Gaussian minimum-shift-keying (GMSK) modulation and converts the received signal to 8-b words after filtering. The modulator IC uses digital waveform generation and a quadrature signal representation. This device is implemented in a 1.5-μm CMOS technology. The power consumption is less than 35 mW from a 5-V supply     

A compact, monolithic microwave demodulator-modulator for 64-QAMdigital radio links

The design, fabrication and performance of a monolithic microwave direct modulation modulator-demodulator are presented. The subsystem is designed to work in a 64-QAM digital radio link. At this level of modulation, it is necessary to have some possibilities of phase and amplitude trimming by external voltages to achieve sufficient accuracy. The circuit includes elementary functions such as quadrature and in-phase splitters, and circuits giving the possibility to adjust phases and amplitudes for 64 QAM and higher level modulation. The design is such that the same chip can be used either as a direct demodulator or as a modulator. This complex circuit of small dimensions (2.7 mm×3.65 mm) exhibits good demodulation and modulation performances. The overall performances of this monolithic circuit are achieved without degrading the DC yield     

一种多模式合成孔径雷达数字接收机

针对一种多模式极化合成孔径雷达（SAR）,给出了中频数字接收机工作参数选择,混频滤波方法,实现了三种带宽信号的数字正交解调。通过分析同相、正交通道误差对正交解调性能的影响,确定了滤波器最佳设计准则。最后给出了基于FPGA的实现结构,仿真试验结果表明中频数字接收机性能比一般模拟接收机有显著提高。     

A 1.5-V 0.7–2.5-GHz CMOS Quadrature Demodulator for Multiband Direct-Conversion Receivers

An integrated quadrature demodulator with an on-chip frequency divider is reported. The mixer consists of a transconductance stage, a passive current switching stage, and an operational amplifier output stage. A complementary input architecture has been used to increase the transconductance for a given bias current. The circuit is inductorless and is capable of operating over a broad frequency range. The chip was implemented in a 0.13-mum CMOS technology. From 700 MHz to 2.5 GHz, the demodulator achieves 35 dB of conversion voltage gain with 250-kHz IF bandwidth, a double-sideband NF of 10 dB with 9-33 kHz 1/f-noise corner. The measured IIP3 is 4 dBm for a 0.1-MHz IF frequency and 10 dBm for a 1-MHz IF frequency. The total chip draws 20 to 24 mA from a single 1.5-V supply.     

A novel demodulator/detector for digital and analog signals on LMRchannels

The design, implementation, and performance of an all-digital demodulator/detector suitable for differential phase-shift keying (DPSK), continuous-phase frequency-shift keying (CPFSK), frequency-shift keying (FSK), and analog FM are discussed. In this modulator/detector, two detectors, one noncoherent and another differentially coherent, operate simultaneously to provide data detection and automatic frequency control (AFC). Test results indicate that the system provides improved performance over the conventional analog quadrature detector for two-period raised-cosine (2RC) CPFSK modulation in additive white Gaussian noise (AWGN) and Rayleigh fading channels. Being all-digital, the demodulator/detector is well suited for integrated circuit implementation. In addition, the system performs as well as the analog quadrature detector for analog FM voice transmissions, thereby maintaining full compatibility with analog land mobile radio (LMR) transmissions     

A 2-V CMOS 455-kHz FM/FSK demodulator using feedforward offsetcancellation limiting amplifier

This paper presents a low-voltage low-power IF 455-kHz signal processor that contains a three-stage limiting amplifier and an FM/FSK demodulator. The limiting amplifier uses an on-chip feedforward offset cancellation circuit. The FM/FSK demodulator employs a quadrature detector that is composed of an on-chip phase detector and an external tank phase shifter. The demodulation constant is 20 mV/kHz with masimum ±10-kHz frequency deviation. The IF signal processor that consumes 2.3 mW from a single 2-V power supply demonstrates a high sensitivity of -72 dBm. It occupies an active area of 0.2 mm² using 0.6-μm digital CMOS technology     

A CMOS GSM IF-sampling circuit with reduced in-channel aliasing

A complex intermediate frequency (IF) sampling technique with intrinsic rejection of even-order aliasing channels is demonstrated. The circuit subsamples in-phase and quadrature IF signals and uses a discrete-time analog delay and an adder to notch out the undesired aliasing frequencies. A chip designed in 0.25-/spl mu/m CMOS technology demonstrates 27-dB antialiasing rejection for a 377-MHz IF GSM signal with 52-MHz sampling rate and 70-dB dynamic range.     

A digital quadrature modulator with on-chip D/A converter

The first analog IF mixer stage of a transmitter can be replaced with this digital quadrature modulator. The modulator interpolates orthogonal input carriers by 16 and performs digital quadrature modulation at carrier frequencies f/sub s//4, -f/sub s//4,f/sub s//2 (f/sub s/ is the sampling frequency). A 12-b digital-to-analog (D/A) converter is integrated with the digital quadrature modulator. A segmented current source architecture is combined with a proper switching technique to reduce spurious components and to enhance dynamic performance. The digital quadrature modulator is designed to fulfill the spectral, phase, and EVM specifications of GSM, EDGE, and WCDMA base stations. The die area of the chip is 27.09 mm/sup 2/ (0.35-/spl mu/m CMOS technology) and the total power consumption is 1.02 W with 2.8 V at 500-MHz output sampling rate (0.78-W digital modulator, 0.24-W D/A converter).     

Implementation of coded modems

Modem implementation techniques that have been proposed to achieve good error probability (P_e) performance in various channel environments and to allow miniaturization of trellis-coded modems are presented. The application of trellis-coded modems, coding and mapping, a quadrature modulator subsystem, and quadrature demodulator subsystem, including carrier-phase offset, carrier slip, automatic frequency control (AFC), and automatic gain control (AGC), is discussed. Also addressed are Viterbi decoder design techniques and the implementation by digital signal processors and LSI circuits, as well as demodulators for Rician fading channels     

一种用于信号分析的数字正交解调电路设计

阐述了数字正交解调的原理以及与传统模拟正交解调相比所体现出的优越性。详细介绍了一种用于信号分析的数字正交解调电路设计方案和工作原理,并结合信号分析类仪器的特点和要求说明电路的硬件和软件设计方法。通过对数字滤波环节的仿真和在具体应用中所得到的实验结果说明设计电路的优越性。     

Cascaded Complex ADCs With Adaptive Digital Calibration for $I/Q$ Mismatch

A complex analog-to-digital converter (ADC) intended for digital intermediate frequency (IF) receiver applications digitizes analog signals at IFs with excellent power/bandwidth efficiency. However, it is vulnerable to mismatches between its in-phase and quadrature (I/Q) paths that can dramatically degrade its performance. The proposed solution mitigates I/Q mismatch effects using a complex sigma-delta (SigmaDelta) modulator cascaded with 9-bit pipeline converters in each of the I and Q paths. The quantization noise of the first stage complex modulator is eliminated using an adaptive scheme to calibrate finite-impulse response digital filters in the digital noise-cancellation logic block. Although low-pass SigmaDelta cascade ADCs are widely used because of their inherent stability and high-order noise shaping, the complex bandpass cascade architecture introduced herein maintains these advantages and doubles the noise shaping bandwidth. Digital calibration also reduces the effects of analog circuit limitations such as finite operational amplifier gain, which enables high performance and low power consumption with high-speed deep-submicrometer CMOS technology. Behavioral simulations of the complex SigmaDelta/pipeline cascade bandpass ADC using the adaptive digital calibration algorithm predict a signal-to-noise ratio (SNR) of 78 dB over a 20-MHz signal bandwidth at a sampling rate of 160 MHz in the presence of a 1% I/Q mismatch.     

35–65-GHz CMOS Broadband Modulator and Demodulator With Sub-Harmonic Pumping for MMW Wireless Gigabit Applications

Sub-harmonic modulator and demodulator are presented in this paper using 0.13-mum standard CMOS technology for millimeter-wave (MMW) wireless gigabit direct-conversion systems. To overcome the main problem of local oscillator (LO) leakage in direct-conversion systems, the sub-harmonically pumped scheme is selected in this mixer design. An embedded four-way quadrature divider is utilized in the sub-harmonic Gilbert-cell design to generate quadrature-phases LO signals at MMW frequency. For broadband applications, a broadband matching design formula is provided in this paper to extend the operational frequency range from 35 to 65 GHz. To improve the flatness of conversion loss at high frequency, high-impedance compensation lines are incorporated between the transconductance stage and LO switching quad of the Gilbert-cell mixer to compensate the parasitic capacitance. The sub-harmonic modulator and demodulator exhibit 6 plusmn1.5 dB and 7.5 plusmn1.5 dB measured conversion loss, respectively, from 35 to 65 GHz. For MMW wireless gigabit applications, the gigabit modulation signal test is successfully performed through the direct-conversion system in this paper. To our knowledge, this is the first demonstration of the MMW CMOS sub-harmonic modulator and demodulator that feature broadband and gigabit applications.     

A general purpose differential digital modulator implementationincorporating a direct digital synthesis method

A highly versatile digital modulator that uses a direct digital synthesis method to perform signal modulation is described. In contrast to the customary methods of implementing I-Q modulation schemes utilizing in-phase and quadrature branches, this design approach is based on directly accessing many of the digitally stored carrier modulating symbols according to the information bearing input signals. Apart from the digital-to-analog converter, all the previous stages are digital. To demonstrate the concept, a differential 16-QAM modulator was implemented. The technique lends itself to VLSI implementation. It can be considered as a digital implementation of a digital modulator     

基于FPGA的超声信号数字正交解调器

利用FPGA设计用于检测微弱超声信号的数字正交解调器.将经高速A/D采样的数字信号分为两路正交的基带信号,通过数字混频、低通滤波和数据抽取,最后从两路正交基带信号中提取出超声回波信号的幅度信息.本文对数字正交解调进行了理论分析,并分别利用FPGA中的内建RAM实现数控振荡器,内嵌乘法器实现数字混频,IP核实现低通滤波器,及宏模块实现数学运算.对玻璃杯的扫描成像实验结果,证明了设计的正确性.