Modeling of the intrinsic retention characteristics of FLOTOXEEPROM cells under elevated temperature conditions

A model for the intrinsic retention characteristics of FLOTOX EEPROM cells is presented, which is based on the temperature dependence of the Fowler-Nordheim emission current. This model which has been successfully tested on single-poly-FLOTOX EEPROM cells, enables the device lifetime to be calculated for given memory operating conditions, instead of being extrapolated as is usually done. The sensitivity of the retention characteristics to several technological parameters is also investigated. It is expected that this intrinsic retention model (with minor modifications) will also be applicable to FLASH EEPROM cells     

Non-ideal base current in bipolar transistors at low temperatures

Bipolar transistors havetraditionally been considered not useful in low-temperature applications. This assumption, however, is based upon an incomplete physical understanding of bipolar device physics at low temperatures. This paper shows experimentally that recombination mechanisms play a substantially larger role in determining base current at low temperatures than at room temperature. The results are explained and quantitatively modeled using conventional Shockley-Read-Hall theory, with the addition of the Poole-Frenkel high field effect. It is concluded that trap levels in the silicon bandgap due to bulk traps or interface states are very important in determining bipolar transistor base currents at low temperatures. Non-ideality factors larger than 2 are often observed. Such trap levels will have to be carefully controlled if low-temperature operation of bipolar transistors is to be considered.     

Hot-carrier-induced interface state generation in submicrometerreoxidized nitrided oxide transistors stressed at 77 K

The hot carrier degradation at 77 K of silicon MOSFETs fabricated with reoxidized nitrided oxide (ONO) gate dielectrics has been investigated. Measurements have been performed at both room and LN₂ temperatures on n-channel FETs for both ONO and conventional SiO ₂ films. It is found that the hot-carrier immunity of ONO transistors is substantially larger than that of conventional SiO₂ devices, and that the degree of improvement is much larger at room temperature that an 77 K. While the interface state generation does increase dramatically as a result of 77-K stressing, the dominant degradation mechanism can be attributed to a large increase in the drain resistance of the device due to localized charge trapping at the drain side of the channel     

标准CMOS工艺栅控Si-LED设计与制备

采用新加坡半导体制备有限公司的0.35um EEPROM双栅标准CMOS工艺设计和制备了U型Si-LED发光器件。器件结构采用P+-N+-P+-P+-P+-N+-P+-P+-P+-N+-P+叉指结构形成U型器件,外部的两个P+区为保护环,在相邻的内部两个P+区之间使用多晶硅作为栅极来调控LED的正偏发光。使用奥林巴斯IC显示镜测得了硅LED实际器件的显微图形,并对器件进行了电学的正反向I-V特性测量。器件在室温下正向偏置,在100～140mA电流下对器件进行了光功率的检测,发光峰值在1089nm处。结果表明,器件发光功率随着栅控电压偏置电流的增加而增加。     

Distributed-feedback quantum cascade lasers emitting in the 9-μmband with InP top cladding layers

Two different high performance quantum cascade distributed-feedback lasers with four quantum-well-based active regions and InP top cladding layers are presented. The first device, which emitted at 9.5 μm, was mounted junction down in order to get high average powers of up to 71 mW at -30°C and 30 mW at room temperature. The other device, which lased at 9.1 μm, was optimized for high pulsed operating temperatures and tested up to 150°C at 1.5% duty cycle. The emission of both lasers stayed single mode with more than 20-dB side-mode suppression ratio over the entire investigated power and temperature range     

Comparison of NMOS and PMOS hot carrier effects from 300 to 77 K

Since hot carrier effects can pose a potential limit to device scaling, hot-carrier-induced device degradation has been one of the major concerns in modern device technology. Currently, there is a great interest in pursuing low-temperature operation of MOS devices since it offers many advantages compared to room temperature operation. Also, low-temperature operation is often required for space applications. However, low-temperature operation exacerbates hot carrier reliability of MOS devices. Even though hot carrier effects are significantly worse at low temperature, most of the studies on hot-carrier-induced device degradation were done at room temperature and little has been done at low temperature. In this work, hot-carrier-induced device degradation is characterized from 77 K to room temperature for both NMOS and PMOS devices with the emphasis on low-temperature behavior of hot carrier degradation. For NMOS devices, the worst case bias condition for hot carrier effects is found to be a function of temperature. It is also determined that one of the primary reasons for the great reduction on hot carrier device lifetime at low temperature is that a given amount of damage simply induces a greater reduction on device performance at low temperature. For PMOS devices, the initial damage appears similar for both room temperature and 77 K; however, subsequent annealing indicates that the damage mechanism at 77 K differs markedly from that at 300 K. Hot carrier stressing on PMOS devices at low temperature appears to induce hole generation and substantial interface state creation upon annealing unlike 300 K stressed devices. This finding may have serious reliability implications for PMOS devices operated at cryogenic temperatures     

浮栅隧道氧化层EEPROM中浮栅上电荷泄漏研究

本文从研究不同单元尺寸浮栅隧道氧化层EEPROM在不同状态、不同温度保存下阈值电压的变化入手,论述了浮栅隧道氧化层EEPROM中浮栅上电荷的泄漏机理,并提出了改进EEPROM保持特性的措施.     

Very small MOSFET's for low-temperature operation

The improvements in the device characteristics of n-channel MOSFET's that occur at low temperatures are considered in this paper. The device parameters for polysilicon gate FET's with channel lengths of the order of 1 µm have been studied both experimentally and theoretically at temperatures ranging from room temperature down to liquid nitrogen temperature. Excellent agreement was found between the experimental dc device characteristics and those predicted by a two-dimensional current transport model, indicating that device behavior is well understood and predictable over this entire temperature range. A device design is presented for an enhancement mode FET with a channel length of I µm that is suitable for operation at liquid nitrogen temperature.     

EEPROM as an analog storage device, with particular applications inneutral networks

The use of EEPROM as a compact, high-precision, nonvolatile, and reconfigurable analog storage element is investigated, with particular consideration given to the modifiable weight storage and analog multiplication problems in the hardware implementation of a neural network. Industry-standard digital EEPROM cells can be programmed to any analog value of threshold voltage, but programming characteristics of different devices on the same chip vary. The programming window of a single device also narrows with cycling. These phenomena necessitate the use of a feedback-based programming scheme. Stressing at high temperature suggests that charge retention is good even at 175°C. The linear variation of threshold voltage with temperature implies that temperature compensation of EEPROM is no more complicated than its conventional MOSFET counterpart. The drain current in the saturation region is found to be a quadratic function of drain voltage when the floating-gate-to-drain overlap capacitance is adequately large. A differential circuit that uses this property to generate the multiplication function required of neural net synapses is proposed     

一种内嵌EEPROM的双电源数字电位计设计

设计了一种基于嵌入式EEPROM工艺的双电源数字电位计。通过两线的I2C总线来控制电路内部EEPROM单元,调节数字电位计的输出电阻或电压。电路采用正负电源供电,同时集成了两路256个抽头可变电位计输出。由于内部集成了EEPROM单元,当电路突然掉电后依然保存抽头设置信息,重新上电后,自动恢复到掉电前电阻抽头的设定位置。该电路采用SMIC 0.18μm EEPROM工艺设计,版图面积为6.76 mm2,采用Hsim对整个电路进行仿真。仿真和测试结果表明,该电位计电路的整体非线性小于±1 LSB,级间非线性小于±0.5 LSB,输出电阻温度系数小于±100×10-6/℃,EEPROM上电恢复时间小于5 ms,可广泛应用于控制系统、参数调整和信号处理领域。     

Annealing characteristics of hot carrier induced damage in n-channel MOSFETs

The recovery process of hot carrier induced degraded device parameters in n-channel MOSFETs has been analysed by both isothermal and isochronal annealing. A wide distribution of activation energies of hot carrier induced damage, with a peak at around 0·9eV is observed. It can be seen that isochronal annealing has advantages over isothermal annealing in recovering the degraded device characteristics in comparatively less time. Bias annealing of the device reveals that initially the annealing of trapped oxide charges increases the interface state density, after reaching the peak value interface states anneal as a logarithmic function of time. The energy distribution of hot carrier induced interface states is similar to radiation induced interface states after a few hours of annealing at room temperature.     

A single-poly EEPROM cell in SIMOX technology for high-temperatureapplications up to 250°C

A thin-film SIMOX technology has been used for fabrication of a single-polysilicon EEPROM cell suitable for high-temperature applications. The two transistor cell is composed of a select transistor and a floating gate transistor with 10 nm tunnel oxide. The EEPROM process extension requires only a few steps suitable for embedded memory applications with low cost and turn around time. Endurance and data retention characteristics of the SIMOX EEPROM cell are presented for a temperature of 250°C. The problem of temperature induced leakage currents in the select transistor at elevated temperatures is investigated     

高兼容CMOS工艺嵌入EEPROM技术

电可擦除只读存储器是非易失性存储器。文章介绍了高兼容常规CMOS工艺的一种嵌入式电可擦除只读存储器设计与工艺技术,对电可擦除只读存储器单元、高压MOS器件的结构与技术进行了研究。研究结果表明,我们设计的0．8μm电可擦除只读存储器单元Vpp电压在13V～15V之间能够正常工作,擦写时间小于500μs,读出电流大于160μA／μm;在普通CMOS工艺基础上增加了BN＋埋层、隧道窗口工艺,成功应用于含嵌入电可擦除只读存储器的可编程电路的设计与制造。     

Evolution of Structure,Optoelectronic Properties,and Device Performance of Polythiophene:Fullerene Solar Cells During Thermal Annealing

We use spectroscopic ellipsometry to study the evolution of structure and optoelectronic properties of poly(3‐hexylthiophene) (P3HT) and [6,6]‐phenyl C61‐butyric acid methyl ester (PCBM) photovoltaic thin film blends upon thermal annealing. Four distinct processes are identified: the evaporation of residual solvent above the glass transition temperature of the blend, the relaxation of non‐equilibrium molecular conformation formed through spin‐casting, the crystallization of both P3HT and PCBM components, and the phase separation of the P3HT and PCBM domains. Devices annealed at 150 °C for between 10 and 60 min exhibit an average power conversion efficiency of around 4.0%. We find that the rate at which the P3HT/PCBM is returned to room temperature is more important in determining device efficiency than the duration of the isothermal annealing process. We conclude that the rapid quenching of a film from the annealing temperature to room temperature hampers the crystallization of the P3HT and can trap non‐equilibrium morphological states. Such states apparently impact on device short circuit current, fill factor and, thus, operational efficiency.     

A versatile stacked storage capacitor on FLOTOX cell for megabitNVRAM's

A versatile stacked storage capacitor on FLOTOX (SCF) structure is proposed for a megabit nonvolatile DRAM (NV-DRAM) cell that has all the features required for NVRAMs. The SCF structure realizes a 30.94-μm ² NV-DRAM cell with 0.8-μm design rules and allows an innovative flash store/recall (DRAM to EEPROM/EEPROM to DRAM) operation that does not disturb original data in DRAM or EEPROM. This store operation is completed in less than 10 ms. The single cell shows excellent reliability such as store endurance greater than 10⁶ cycles and EEPROM data retention in excess of 10 years under high storage temperatures of 150°C and DRAM write operation at 85°C. The SCF cell has been successfully implemented into the 1 Mb NVRAM     

Short-channel effects in MOSFET's at liquid-Nitrogen temperature

Short-channel or high-field effects in MOSFET devices are a continuing area of research in room-temperature devices. Much has been learned in the past several years about the physical origins of these effects, and new or modified device structures have been proposed to minimize them. Because of the improved device and circuit performance possible at liquid-nitrogen temperature (LN2), there has been considerable recent interest in low-temperature device physics. While large-geometry MOSFET behavior has been discussed in the literature at LN2, very little has been quantified regarding short-channel effects at low temperature. This paper addresses the physical origins of short-channel effects at these temperatures. It is concluded that while the physical mechanisms are similar to those at room temperature, quantitative differences exist that favor LN2operation.     

Oligothiophenes in organic thin film transistors – Morphology,stability and temperature operation

We have investigated a series of oligothiophenes in organic thin film transistors (TFTs), with special emphasis on their thin film morphology related to device performance and application requirements. The transistor performance was studied for devices fabricated at different substrate temperatures during semiconductor deposition (ranging from room temperature to 120 °C). A significant dependence of thin film morphology on the substrate temperature was observed, whereas the charge carrier mobility in devices occurs almost unaffected. We have tested the long-term stability of 78 transistor devices (shelf-life in ambient conditions) over a period up to 100 days. Only a small degradation in mobility by less than one order of magnitude was observed. Investigations at elevated temperatures during TFT operation (room temperature to 105 °C) show that devices with α,α′-hexylsexithiophene (Hex-6T-Hex) degrade in their charge carrier mobility by a factor of 8, but completely recover to their initial value of 0.7 cm²/Vs after a short period of storage at room temperature in ambient conditions.     

Light-emitting tunneling nanostructures based on quantum dots in a Si and GaAs matrix

InGaAs/GaAs and Ge/Si light-emitting heterostructures with active regions consisting of a system of different-size nanoobjects, i.e., quantum dot layers, quantum wells, and a tunneling barrier are studied. The exchange of carriers preceding their radiative recombination is considered in the context of the tunneling interaction of nanoobjects. For the quantum well-InGaAs quantum dot layer system, an exciton tunneling mechanism is established. In such structures with a barrier thinner than 6 nm, anomalously fast carrier (exciton) transfer from the quantum well is observed. The role of the above-barrier resonance of states, which provides “instantaneous” injection into quantum dots, is considered. In Ge/Si structures, Ge quantum dots with heights comparable to the Ge/Si interface broadening are fabricated. The strong luminescence at a wavelength of 1.55 μm in such structures is explained not only by the high island-array density. The model is based on (i) an increase in the exciton oscillator strength due to the tunnel penetration of electrons into the quantum dot core at low temperatures (T < 60 K) and (ii) a redistribution of electronic states in the Δ₂-Δ₄ subbands as the temperature is increased to room temperature. Light-emitting diodes are fabricated based on both types of studied structures. Configuration versions of the active region are tested. It is shown that selective pumping of the injector and the tunnel transfer of “cold” carriers (excitons) are more efficient than their direct trapping by the nanoemitter.     

InGaN/GaN多量子阱蓝光LED电学特性研究

对不同温度(120～363 K)下InGaN/GaN多量子阱(MQW)结构蓝光发光二极管(LED)的电学特性进行了测试与深入的研究.发现对数坐标下I-V特性曲线斜率随温度变化不大.分别用载流子扩散-复合模型和隧道复合模型对其进行计算,发现室温下其理想因子远大于2,并且随着温度的下降而升高;而隧穿能量参数随温度变化不大.这说明传统的扩散-复合载流子输运模型不再适用于InGaN/GaN MQW蓝光LED.分析指出由于晶格失配以及生长工艺的制约,外延层中具有较高的缺陷密度和界面能级密度,导致其主要输运机制为载流子的隧穿.     

Base profile design for high-performance operation of bipolartransistors at liquid-nitrogen temperature

Measurements of thin epitaxial-base polysilicon-emitter n-p-n transistors with increasing base doping show the effects of bandgap narrowing, mobility changes, and carrier freezeout. At room temperature the collector current at low injection is proportional to the integrated base charge, independent of the impurity distribution. At temperatures below 150 K, however, minority injection is dominated by the peak base doping because of the greater effectiveness of bandgap narrowing. When the peak doping in the base approaches 10¹⁹ cm^-3, the bandgap difference between emitter and base is sufficiently small that the current gain no longer monotonically decreases with lower temperature but instead shows a maximum as low as 180 K. The device design window appears limited at the low-current end by increased base-emitter leakage due to tunneling and by resistance control at the high-current end. Using the measured DC characteristics, circuit delay calculations are made to estimate the performance of an emitter-coupled logic ring oscillator at room and liquid-nitrogen temperatures. It is shown that if the base doping can be raised to 10¹⁹ cm^-3 while keeping the base thickness constant, the minimum delay at liquid-nitrogen temperature can approach the delay of optimized devices at room temperature