Prototyping of a reliable 3D flexible IC cube package by laser micromachining

A newly designed three-dimensional (3D) flexible circuit as a package with five IC chips has been invented, and the prototype of the 3D package using laser micromachining has been successfully demonstrated. Fabrication processes of the 3D package consist of (1) preparation of printed wiring on the flexible substrate, (2) selective polyimide material removing on contact pads using UV laser (3) component placing and soldering, and (4) preparation of bending windows by laser micromachining. The production of the so-called bending window is a unique application of laser material processing. These windows can be used in flexible circuits to define the exact position of deformation. It is done by reducing the thickness of the flexible substrate in a well-defined, narrow line. The unique feature of this newly developed package is the 2D design for a 3D structure. According to this design, 55% area reduction can be obtained without any designing and overheating problems, which usually occurs. Furthermore, the new 3D package design can simplify processes such as I/O redistribution, chip cooling, and package formation. It is proven that the mechanical integrity of the prototype 3D stacked package meets the requirements of the 85 °C/85% test.     

Design and optimization of thermo-mechanical reliability in wafer level packaging

In this paper, a variety of wafer level packaging (WLP) structures, including both fan-in and fan-out WLPs, are investigated for solder joint thermo-mechanical reliability performance, from a structural design point of view. The effects of redistribution layer (RDL), bump structural design/material selection, polymer-cored ball application, and PCB design/material selection are studied. The investigation focuses on four different WLP technologies: standard WLP (ball on I/O WLP), ball on polymer WLP without under bump metallurgy (UBM) layer, ball on polymer WLP with UBM layer, and encapsulated copper post WLP. Ball on I/O WLP, in which solder balls are directly attached to the metal pads on silicon wafer, is used as a benchmark for the analysis. 3-D finite element modeling is performed to investigate the effects of WLP structures, UBM layer, polymer film material properties (in ball on polymer WLP), and encapsulated epoxy material properties (in copper post WLP). Both ball on polymer and copper post WLPs have shown great reliability improvement in thermal cycling. For ball on polymer WLP structures, polymer film between silicon and solder balls creates a ‘cushion’ effect to reduce the stresses in solder joints. Such cushion effect can be achieved either by an extremely compliant film or a ‘hard’ film with a large coefficient of thermal expansion. Encapsulated copper post WLP shows the best thermo-mechanical performance among the four WLP structures. Furthermore, for a fan-out WLP, it has been found that the critical solder balls are the outermost solder balls under die-area, where the maximum thermal mismatch takes place. In a fan-out WLP package, chip size, other than package size, determines the limit of solder joint reliability. This paper also discusses the polymer-cored solder ball applications to enhance thermo-mechanical reliability of solder joints. Finally, both experimental and finite element analysis have demonstrated that making corner balls non-electrically connected can greatly improve the WLP thermo-mechanical reliability.     

Wafer level and flip chip design through solder prediction modelsand validation

In flip chip package applications, bumped dies are flip-chip assembled to substrate metal pads creating joints that serve electrically and mechanically. Resulting solder joint profiles are defined by the solder bump volume, the under bump metallurgy (LTBM) area, and the substrate metal pad size and shape. Solder bump height and diameter was predicted by the geometrical truncated sphere model and surface evolver model at the wafer level, using the known solder volume deposited by stencil printing method. The surface evolver model was used to predict the assembled solder joint height, gap height, collapse height, and maximum bump diameter of flip chip assemblies. In turn, substrate pads were fine-tuned to achieve required gap heights. Collapse heights provided the means to develop assembly tolerances and relative risk of bridging was determined from knowledge of resulting bump diameters. Through validated design of the stencil printing technology and prediction of realistic bump and assembly solder geometries, the results are improved processes and die level design and assembly. Optimized design parameters are incorporated and accurately represented in simulation and experimentally validated with assemblies     

Wafer level packaging of a tape flip-chip chip scale packages

The advent of chip scale packages (CSPs) within the semiconductor community has led to the development of wafer scale assembly (WSA) or wafer level packaging (WLP) manufacturing in order to raise assembly efficiencies and lower operating costs. Texas Instruments (TI) has developed a unique WLP process for forming flip-chip, ball grid array packages. The die inputs and outputs of the TI CSP are connected through solder bumps to a polyimide film interposer. Solder balls on the other side of the interposer complete the electrical connection to a customer’s printed circuit board. A wafer-sized array of interposers designed to match the pattern of dies on a wafer is aligned and reflowed to a bumped wafer. The TI WLP process is completed by singulating the CSPs from the wafer using standard wafer saw equipment.Attachment of the interposer to the die as well as applying the die and board level solder bumps are carried out in wafer form using a new bumping technology called Tacky Dots™. Tacky Dots uses an array of sticky dots formed in a photosensitive coating laminated to a polyimide film for transferring and attaching solder spheres to semiconductor substrates. A populated film containing one solder sphere per Tacky Dot is positioned over the wafer or interposer and lowered until the spheres contact the pads. A reflow process transfers the spheres from the film to the wafer or interposer and the film is removed once the spheres have frozen.This paper illustrates the process steps and custom equipment developed for forming the TI CSP. The strategic use of finite element modeling for optimizing the design of the package is outlined. The paper concludes by summarizing the current package level reliability results.     

一种基于TSV和激光刻蚀辅助互连的改进型CIS封装

提出了一种基于硅通孔(TSV)和激光刻蚀辅助互连的改进型CMOS图像传感器(CIS)圆片级封装方法.对CIS芯片电极背部引出的关键工艺,如锥形TSV形成、TSV绝缘隔离、重布线(RDL)等进行了研究.采用低温电感耦合等离子体增强型化学气相淀积(ICPECVD)的方法实现TSV内绝缘隔离;采用激光刻蚀开口和RDL方法实现CIS电极的背部引出;通过采用铝电极电镀镍层的方法解决了激光刻蚀工艺中聚合物溢出影响互连的问题,提高了互连可靠性.对锥形TSV刻蚀参数进行了优化.最终在4英寸(1英寸=2.54 cm)硅/玻璃键合圆片上实现了含有276个电极的CIS圆片级封装.电性能测试结果表明,CIS圆片级封装具有良好的互连导电性,两个相邻电极间平均电阻值约为7.6Ω.     

A Three-Dimensional Stacked-Chip Star-Wiring Interconnection for a Digital Noise-Free and Low-Jitter I/O Clock Distribution Network

Cascaded repeaters are indispensable circuit elements in conventional on-chip clock distribution networks due to heavy loss characteristics of on-chip global interconnections. However, cascaded repeaters cause significant jitter and skew problems in clock distribution networks when they are affected by power supply switching noise generated by digital logic blocks located on the same die. In this letter, we present a new three-dimensional (3-D) stacked-chip star-wiring interconnection scheme to make a clock distribution network free from both on-chip and package-level power supply noise coupling. The proposed clock distribution scheme provides an extremely low-jitter and low-skew clock signal by replacing the cascaded repeaters with lossless star-wiring interconnections on a 3-D stacked-chip package. We have demonstrated a 500-MHz input/output (I/O) clock delivery with 34-ps peak-to-peak jitter and a skew of 11ps, while a conventional I/O clock scheme exhibited a 146-ps peak-to-peak jitter and a 177-ps skew in the same power supply noise environment     

A wafer-scale 170000-gate FFT processor with built-in test circuits

The wafer-scale 170000-gate fast Fourier transform (FFT) processor described consists of individual repeatable building blocks, each of which contains a processing element (PE) and interconnection wiring. The PE consists of a multiplier accumulator and its built-in self-test circuits. The wafer system is reconfigured by connected active blocks after block self-diagnosis. Blocks are connected using a programmable contact-hole mask. The processor performs parallel 16-bit, eight-point complex FFTs and is implemented with 725 I/O pads in triple-metal 2.3-μm p-well CMOS technology on a 4-in. wafer. It is mounted by controlled-collapse bonding facedown on a 11.8×11.8-cm² substrate     

Mechanical and Electrical Reliability Assessment of Stacking of Ultrathin Chips on Si Interposer Using Back-to-Face Architecture

Chip-to-wafer stacking is a key enabling technology for two and half dimension (2.5D) as well as for three dimension (3D), with technological challenges driven by the increase of the die surface and the number of input/outputs (I/Os) and the reduction of the vertical dimensions. In our investigation, chips were assembled using a back-to-face approach on a silicon interposer containing copper through-silicon vias (TSVs). This technology is based on the realization of a high-topology redistribution layer passing over the dies bonded with the active face up on the interposer by using a polymer layer. This architecture is attractive because of the reduction of the chip thickness to an ultrathin dimension, and can offer substantial advantages in terms of design flexibility and technology cost. In this architecture, chip bonding strategies are compared: several bonding materials were tested either on the die side using die-attach film or on the bottom side of the interposer using wafer-level spin-coated polymers. Then, a novel brick (sequence) of processes consisting of high-topology encapsulation and metallization was fully developed to connect the top dies to the bottom wafer. The resulting structure has been modeled through the temperature cycles seen during fabrication using a thermomechanical finite element modeling (FEM) simulation for different geometries and materials. The results indicate a moderate level of stress in the stacked film layers with some concentration in localized regions of the topology. Electrical tests have also been completed at the wafer level, showing low resistances and high yield at front-side and at the back-side level after TSV exposure. Successful reliability tests have also been carried out and support the good mechanical behavior of this integration.     

Ultrathin wafer level chip size package

The ShellCase wafer-level packaging process uses commercial semiconductor wafer processing equipment. Dies are packaged and encapsulated into separate enclosures while still in wafer form. This wafer level chip size package (WLCSP) process encases the die in a solid die-size glass shell. The glass encapsulation prevents the silicon from being exposed and ensures excellent mechanical and environmental protection. A proprietary compliant polymer layer under the bumps provides on board reliability. Bumps are placed on the individual contact pads, are reflowed, and wafer singulation yields finished packaged devices. This WLCSP fully complies with Joint Electron Device Engineering Council (JEDEC) and surface mount technology (SMT) standards. Such chip scale packages (CSP's) measure 300-700 μm in thickness, a crucial factor for use in various size sensitive electronic products     

High-performance FCBGA based on multi-layer thin-substrate packaging technology

We developed a new concept flip-chip ball grid array (FCBGA) based on multi-layer thin-substrate (MLTS) packaging technology in order to meet the strong demand for high-density, high-performance, and low-cost LSI packages. The most important feature of MLTS packaging is that, only a high-density and high-performance MLTS remains by removing the metal plate after mounting an LSI chip. The MLTS packaging offers the advantages of (1) good registration accuracy, which makes higher-density and finer-pitch pattering possible; (2) an ideal multi-layer structure that is highly suitable for high-speed and high-frequency applications; (3) excellent flip-chip mounting reliability, which makes higher-pin-count and finer-pitch area array flip-chip interconnection possible; (4) excellent reliability, supported by use of high T_g (glass transition temperature) resin; and (5) a cost-effective design achieved as a result of fewer layers fabricated with fine-pitch patterning.We successfully produced a high-performance FCBGA prototype based on our MLTS packaging technology. The prototype comprises an LSI chip connected to approximately 2500 bonding pads arranged in 240 μm pitch area array, and 1296 I/O pads for BGA. The prototype FCBGA’s excellent long-term reliability was demonstrated through a series of tests conducted on it.     

Fine grain thermal modeling and experimental validation of 3D-ICs

3D die stacking is a promising technique to allow miniaturization and performance enhancement of electronic systems. Key technologies for realizing 3D interconnect schemes are the realization of vertical connections, either through the Si die or through the multilayer interconnections. The complexity of these structures combined with reduced thermal spreading in the thinned dies complicate the thermal analysis of a stacked die structure. In this paper a methodology is presented to perform a detailed thermal analysis of stacked die packages including the complete back end of line structure (BEOL), interconnection between the dies and the complete electrical design layout of all the stacked dies. The calculations are performed by 3D numerical techniques and the approach allows importing the full electrical design of all the dies in the stack. The methodology is demonstrated on a 2 stacked die structure in a BGA package. For this case the influence of through-Si vias (TSVs) on the temperature distribution is studied. The modeling results are experimentally validated with a dedicated test vehicle. A thermal test chip with integrated heaters and diodes as thermals sensors is used to successfully validate the detailed temperature profile of the hot spots in the top die of the die stack.     

Evolution of a unique flip-chip MCM-L package

Flip-chip (FC) packaging is gaining acceptance in the electronics packaging arena. More sources of bumped die and high density printed wiring boards (PWBs) laminates become available every day. Also, known good die (KGD) issues are being resolved by several companies, and design tools to perform FC packaging designs are becoming more available. This is the infrastructure FC packaging requires to become the packaging method of choice, particularly for >200 I/O applications. FC packages come in a variety of styles: FC plastic ball grid arrays (FC/PBGAs), FC plastic quad flat packs (PC/PQFPs), etc. Presently, the industry's drive is toward single chip packages on low cost laminates; i.e., organic substrates. Work is starting to occur in the area of multichip FC packages, due to the need to increase memory to microprocessor speed communication. In this article, a unique FC/MCM-L package is discussed. Part I will concentrate on the development and reliability testing of a one to four chip leadless FC/MCM-L package. Unlike traditional surface mount (SM) components that are attached to printed wiring boards (PWBs) with leads, the SM pads within the body of the package are used for attachment to a PWB. Collapsible eutectic solder domes are deposited on the SM pads by traditional screen printing. After reflow, these domes are used to connect the FC/MCM-L to the PWB. Challenges encountered during package design, PWB fabrication and first and second level assembly will be discussed. Part II of this article will focus on the extension of this FC/MCM-L package to a BGA second level interconnect. Change of FC attachment method, design enhancements, assembly, and reliability testing results will be presented     

超薄型圆片级芯片尺寸封装技术

ShellCase公司的圆片级封装技术工艺,采用商用半导体圆片加工设备,把芯片进行封装并包封到分离的腔体中后仍为圆片形式。圆片级芯片尺寸封装(WL-CSP)工艺是在固态芯片尺寸玻璃外壳中装入芯片。玻璃包封防止了硅片的外露,并确保了良好的机械性能及环境保护功能。凸点下面专用的聚合物顺从层提供了板级可靠性。把凸点置于单个接触焊盘上,并进行回流焊,圆片分离形成封装器件成品。WL-CSP封装完全符合JEDEC和SMT标准。这样的芯片规模封装(CSP),其测量厚度为300μm-700μm,这是各种尺寸敏感型电子产品使用的关键因素。     

An overview of experimental methodologies and their applications for die strength measurement

As the trends in semiconductor packages continue toward a decrease in overall package size and an increase in functionality and performance requirements, they bring challenges of processing, handling, and understanding smaller components and, in particular, thinner dies. In the meantime, high reliability remains a critical necessity. It is necessary to be able to appropriately characterize thinned dies in terms of their mechanical integrity and, equally important, in terms of the processes used to produce them. In practice, die strength can be adversely affected during various manufacturing processes, such as thinning and singulation. A realistic understanding of the significance of processing on die strength is gained through the study of the actual, processed component. This work outlines three methodologies that enable the measurement of die strength and demonstrates their application in three studies. Characterization of die damage, experimentation, and failure analysis are coupled to gain understanding of die strength with respect to processing conditions. The approaches demonstrated ultimately show the use of such information toward quantifying die strength, developing design criteria, selecting wafer processes, and optimizing processes.     

IC中的输入/输出电路设计

任何一种设计技术、版图结构都需要输入/输出单元。不论是门阵列结构、还是标准单元结构,现代设计理论提倡将IC的内部结构和外部信号接口分开设计,承担输入、输出信号接口的I/O单元就不再仅是焊盘,而是具有一定功能的功能块。这些功能块担负对外的驱动、内外的隔离、输入保护或其他接口功能。详细介绍了3种输入/输出电路的性能、原理和结构,并在此基础上提出了进行I/O电路设计的一般准则。     

一款系统级封装产品设计及失效分析

文中以一款两颗芯片、一颗压力传感器及一颗谐振器的集成封装为例,研究了堆栈芯片、PCB与引线框架粘结、长线弧键合、异质材料粘合等封装中的常见问题的解决方法,提出了优化设计方案。使用DOE试验找出各个工序的最佳参数,设计工艺流程,并使用生产设备制造出样品,验证了封装设计的可制造性及设计可靠性。对样品进行失效分析,找出设计中存在的不足,提出解决方案。     

A 54000-gate ECL array with substrate power supply

A sub-100-ps, 54000-gate ECL array with substrate power supply has been developed on a 64-mm/sup 2/ die. Gate density of 1160 gate/mm/sup 2/ is achieved by the newly developed 'CUBE' (Chip with Upside and Backside Electrodes) technology which enables a five-layer interconnection structure including heavily doped substrate and a polycide layer in addition to the conventional three metal layers. Gate delay of 96 ps with 2.4-mW power dissipation is obtained using double-polysilicon self-aligned transistor technology. The features of this technology are (1) high-density LSI resulting in improved interconnection delay and smaller chip size, (2) small voltage drops of power supply on the chip, and (3) an increased number of signal pads by eliminating V/sub EE/ pads from the top side of the chip.<>     

High-density 3-D packaging technology based on the sidewall interconnection method and its application for CCD micro-camera visual inspection system

High-density three-dimensional (3-D) packaging technology for a charge coupled device (CCD) micro-camera visual inspection system module has been developed by applying high-density interconnection stacked unit modules. The stacked unit modules have fine-pitch flip-chip interconnections within Cu-column-based solder bumps and high-aspect-ratio Cu sidewall footprints for vertical interconnections. Cu-column-based solder bump design and underfill encapsulation resin characteristics were optimized to reduce the strain in the bump so as to achieve fine-pitch flip-chip interconnection with high-reliability. High-aspect-ratio Cu sidewall footprints were realized by the Cu-filled stacked vias at the edge of the substrate. High-precision distribution of sidewall footprints was achieved by laminating the multiple stacked unit substrates simultaneously. The fabricated high-density 3-D packaging module has operated satisfactorily as the CCD imaging data transmission circuit. The technology was confirmed to be effective for incorporating many large scale integrated (LSI) devices of different sizes at far higher packaging density than it is possible to attain using conventional technology. This paper describes the high-density 3-D packaging technology which enables all of the CCD imaging data transmission circuit devices to be packaged into the restricted space of the CCD micro-camera visual inspection system interior.     

叠层CSP封装工艺仿真中的有限元应力分析

叠层CSP封装已日益成为实现高密度、三维封装的重要方法。在叠层CSP封装工艺中,封装体将承受多次热载荷。因此,如果封装材料之间的热错配过大,在芯片封装完成之前,热应力就会引起芯片开裂和分层。详细地研究了一种典型四层芯片叠层CSP封装产品的封装工艺流程对芯片开裂和分层问题的影响。采用有限元的方法分别分析了含有高温过程的主要封装工艺中产生的热应力对芯片开裂和分层问题的影响,这些封装工艺主要包括第一层芯片粘和剂固化、第二、三、四层芯片粘和剂固化和后成模固化。在模拟计算中发现:(1)比较三步工艺固化工艺对叠层CSP封装可靠性的影响,第二步固化工艺是最可能发生失效危险的;(2)经过第一、二步固化工艺,封装体中发现了明显的应力分布特点,而在第三步固化工艺中则不明显。     

Fracture strength characterization and failure analysis of silicon dies

This paper characterizes fracture strength of a silicon die as a first step to predict and prevent die cracking during package assembly, reliability tests, and operation life. Die strength is measured via the three-point bend test conducted using a micro-force tester. Strength reduction due to surface defects, such as tiny notches or micro-cracks that are introduced through wafer backside grinding is evaluated. It is observed that die strength strongly depends on the grinding patterns, i.e. minimum die strength in a wafer is found if the grinding mark is in parallel with the loading axis. Furthermore, fracture strength of dies with different wafer surface conditions like polishing and no treatment (grinding) are also examined. Polished wafers possess the highest silicon strength owing to its minimum surface flaws. On the other hand, untreated wafers contain the most severe surface defects; hence exhibit the lowest die strength. Geometrical factors (square vs. rectangular) and die thickness (4 vs. 6 mils) are probed as well, however these factors do not contribute to die strength degradation. Surface morphology and roughness studies of silicon dies via scanning electron microscope and atomic force microscope also confirmed that die strength degradation is mainly controlled by surface defect (roughness) levels. Observed fracture modes also correlate well with measured die strength.