Selective wet etch of a TaN metal gate with an amorphous-silicon hard mask

The appropriate wet etch process for the selective removal of TaN on the HfSiON dielectric with an amorphous-silicon(a-Si) hardmask is presented.SCI(NH_4OH:H_2O_2:H_2O),which can achieve reasonable etch rates for metal gates and very high selectivity to high-k dielectrics and hardmask materials,is chosen as the TaN etchant. Compared with the photoresist mask and the tetraethyl orthosilicate(TEOS) hardmask,the a-Si hardmask is a better choice to achieve selective removal of TaN on the HfSiON dielectric be...     

以非晶硅为硬掩膜的TaN金属栅的选择性湿法腐蚀

提出了一种在HfSiON介质上,采用非晶硅为硬掩膜的选择性去除TaN的湿法腐蚀工艺。由于SC1(NH4OH:H2O2:H2O)对金属栅具有合适的腐蚀速率且对硬掩膜和高K材料的选择比很高,所以选择它作为TaN的腐蚀溶液。与光刻胶掩膜和TEOS硬掩膜相比,因非晶硅硬掩膜不受SC1溶液的影响且很容易用NH4OH溶液去除（NH4OH溶液对TaN和HfSiON薄膜无损伤）,所以对于在HfSiON介质上实现TaN的选择性去除来说非晶硅硬掩膜是更好的选择。另外,在TaN金属栅湿法腐蚀和硬掩膜去除后, 高K介质的表面是光滑的,这可防止器件性能退化。因此,采用非晶硅为硬掩膜的TaN湿法腐蚀工艺可以应用于双金属栅集成,实现先淀积的TaN金属栅的选择性去除。     

先进CMOS器件中poly-Si/TaN/HfSiON栅结构的干法刻蚀研究

研究了先进CMOS器件中poly-Si/TaN/HfSiON栅结构的干法刻蚀工艺。对于poly-Si/TaN/HfSiON栅结构的刻蚀,我们采用的策略是对栅叠层中的每一层都进行高选择比地、陡直地刻蚀。首先,对于栅结构中poly-Si的刻蚀,开发了一种三步的等离子体刻蚀工艺,不仅得到了陡直的poly-Si刻蚀剖面而且该刻蚀可以可靠地停止在TaN金属栅上。然后,为了得到陡直的TaN刻蚀剖面,研究了多种BCl3基刻蚀气体对TaN金属栅的刻蚀,发现BCl3/Cl2/O2/Ar等离子体是合适的选择。而且,考虑到Cl2对Si衬底几乎没有选择比,采用优化的BCl3/Cl2/O2/Ar等离子体陡直地刻蚀掉TaN金属栅以后,我们采用BCl3/Ar等离子体刻蚀HfSiON高K介质,改善对Si衬底的选择比。最后,采用这些新的刻蚀工艺,成功地实现了poly-Si/TaN/HfSiON栅结构的刻蚀,该刻蚀不仅得到了陡直的刻蚀剖面且对Si衬底几乎没有损失。     

Wet etching characteristics of a HfSiON high-k dielectric in HF-based solutions

The wet etching properties of a HfSiON high-k dielectric in HF-based solutions are investigated. HF-based solutions are the most promising wet chemistries for the removal of HfSiON, and etch selectivity of HF-based solutions can be improved by the addition of an acid and/or an alcohol to the HF solution. Due to densification during annealing,the etch rate of HfSiON annealed at 900℃ for 30 s is significantly reduced compared with as-deposited HfSiON in HF-based solutions. After the HfSiON film has been completely removed by HF-based solutions, it is not possible to etch the interracial layer and the etched surface does not have a hydrophobic nature, since N diffuses to the interface layer or Si substrate formation of Si-N bonds that dissolves very slowly in HF-based solutions. Existing Si-N bonds at the interface between the new high-k dielectric deposit and the Si substrate may degrade the carrier mobility due to Coulomb scattering. In addition, we show that N2 plasma treatment before wet etching is not very effective in increasing the wet etch rate for a thin HfSiON film in our case.     

GaAs surface wet cleaning by a novel treatment in revolving ultrasonic atomization solution

A novel process for the wet cleaning of GaAs surface is presented. It is designed for technological simplicity and minimum damage generated within the GaAs surface. It combines GaAs cleaning with three conditions consisting of (1) removal of thermodynamically unstable species and (2) surface oxide layers must be completely removed after thermal cleaning, and (3) a smooth surface must be provided. Revolving ultrasonic atomization technology is adopted in the cleaning process. At first impurity removal is achieved by organic solvents; second NH_4OH : H_2O_2 : H_2O =1:1:10 solution and HCl : H_2O_2 : H_2O = 1:1:20 solution in succession to etch a very thin GaAs layer, the goal of the step is removing metallic contaminants and forming a very thin oxidation layer on the GaAs wafer surface;NH_4OH : H_2O =1:5 solution is used as the removed oxide layers in the end. The effectiveness of the process is demonstrated by the operation of the GaAs wafer. Characterization of the oxide composition was carried out by X-ray photoelectron spectroscopy. Metal-contamination and surface morphology was observed by a total reflection X-ray fluorescence spectroscopy and atomic force microscope. The research results show that the cleaned surface is without contamination or metal contamination. Also, the GaAs substrates surface is very smooth for epitaxial growth using the rotary ultrasonic atomization technology.     

The fabrication and dry etching of poly-Si/TaN/Mo gate stack in the metal inserted poly-Si stack structure

The Mo-based metal inserted poly-Si stack (MIPS) structure is an appropriate choice for metal gate and high-k integration in sub-45 nm gate-first CMOS device. A novel metal nitride layer of TaN or AlN with high thermal stability has been introduced between Mo and poly-Si as a barrier material to avoid any reaction of Mo during poly-Si deposition. After Mo-based MIPS structure is successfully prepared, dry etching of poly-Si/TaN/Mo gate stack is studied in detail. The three-step plasma etching using the Cl₂/HBr chemistry without soft landing step has been developed to attain a vertical poly-Si profile and a reliable etch-stop on the TaN/Mo metal gate. For the etching of TaN/Mo gate stack, two methods using BCl₃/Cl₂/O₂/Ar plasma are presented to get both vertical profile and smooth etched surface, and they are critical to get high selectivity to high-k dielectric and Si substrate. In addition, adding a little SF₆ to the BCl₃/O₂/Ar plasma under the optimized conditions is also found to be effective to smoothly etch the TaN/Mo gate stack with vertical profile.     

沉积、退火条件以及刻蚀液对PECVD氮化硅薄膜湿法刻蚀速率的影响

The influence of deposition, annealing conditions, and etchants on the wet etch rate of plasma enhanced chemical vapor deposition （PECVD） silicon nitride thin film is studied. The deposition source gas flow rate and annealing temperature were varied to decrease the etch rate of SiNx：H by HF solution. A low etch rate was achieved by increasing the SiH4 gas flow rate or annealing temperature, or decreasing the NH3 and N2 gas flow rate. Concentrated, buffered, and dilute hydrofluoric acid were utilized as etchants for Sit2 and SiNx：H. A high etching selectivity of Sit2 over SiNx：H was obtained using highly concentrated buffered HE     

用于悬浮纳米结构制作的氢氟酸气相刻蚀研究

针对纳米悬浮结构的制作,对不同温度和不同气相条件下的氢氟酸(HF)气相刻蚀进行了研究.利用自制的研究装置,使用HF/水混合气体和HF/乙醇混合气体分别进行了HF对PECVD SiO_2的气相刻蚀实验,同时测量了不同衬底温度下刻蚀速率的变化.研究结果表明,在常温常压下,HF/乙醇混合气体气相刻蚀速率约为7.6 nm/s,而HF/水混合气体气相刻蚀速率约为11.5 nm/s.在衬底温度分别为35,40和50℃时,HF/水混合气体的气相刻蚀速率分别为10.25,7.95和5.18 nm/s.利用HF气相腐蚀进行SiO_2牺牲层释放,得到了悬浮的纳米梁结构,梁与衬底的间距为400 nm.     

A study of the role of HBr and oxygen on the etch selectivity and the post-etch profile in a polysilicon/oxide etch using HBr/O2 based high density plasma for advanced DRAMs

The role of HBr and oxygen on the etch selectivity and the post-etch profile in a polysilicon/oxide etch using HBr/O₂ based high density plasma was studied. HBr/O₂-based polysilicon etch process used in this study seems to be highly selective to the underlying oxide and produce a dielectric fill-friendly post-etch profile depending on the flow rates of HBr and oxygen. When appropriate amounts of HBr and oxygen (∼30 sccm of HBr and ∼3 sccm of oxygen) are present in the etch plasma, brominated silicon oxide seems to be deposited on the original gate oxide and the gate stack sidewall from the reaction of SiBr_x (reaction product during polysilicon etch step) and oxygen during the HBr/O₂-based oxide etch process. The deposited brominated oxide on the thin gate oxide seems to make the HBr/O₂-based plasma etch process extremely selective to the thin gate oxide by protecting the underlying gate oxide. The deposited brominated oxide on the gate stack sidewall seems to prevent the notching by protecting the sidewall during gate stack etching. The etch rate of the brominated oxide seems to be much faster than that of the thermal oxide during the 200:1 diluted HF cleaning. However, the deposited brominated oxide on the thin gate oxide and the gate stack sidewall during the plasma etching survived the following 1 min 200:1 diluted HF cleaning, as was observed in a TEM micrograph (Fig. 2(a)).     

Plasma Etching for Sub-45-nm TaN Metal Gates on High-k Dielectrics

Etching of TaN gates on high-k dielectrics (HfO₂ or HfAlO) is investigated using HBr/Cl₂ chemistry in a decoupled plasma source (DPS). The patterning sequence includes 248-nm lithography, plasma photoresist trimming, etching of a SiN-SiO₂ hard mask, and photoresist stripping, followed by TaN etching. TaN etching is studied by design of experiment (DOE) with four variables using a linear model with interactions. It is found that at a fixed substrate temperature and wafer chuck power, etch critical dimensions (CD) gain decreases with decreasing HBr/Cl₂ flow rate ratio and pressure and with increasing source power and total gas flow rate. Based on these DOE findings, subsequent optimization is performed and a three-step etching process is developed; a main feature of the process is progressively increasing HBr/Cl₂ flow rate ratio. The optimized process provides etch CD gain within 2 nm and gate profile close to vertical and reliable etch-stop on high-k dielectric. This process is successfully applied to the fabrication of the 40-nm HfAlO/TaN gate stack p-MOSFETs with good electrical parameters     

Pyrex玻璃的湿法刻蚀研究

对Pyrex 7740玻璃的湿法刻蚀工艺进行了研究。实验中采用了几种不同的材料(光刻胶、Cr／Au、TiW／Au)作为刻蚀玻璃的掩膜，通过实验发现TiW／Au掩膜相对目前比较常用的Cr／Au掩膜有很多优点，如减少了玻璃的横向腐蚀，增加了深宽比，刻蚀图形边缘更加平滑等。还研究了腐蚀液成分配比对刻蚀结果的影响，发现刻蚀速率随HF浓度的增加而增加，且在HF浓度一定时，加入少量HNO3可以明显提高刻蚀速率。本文的实验结果对一些MEMS器件特别是微流体器件的制作有一定参考作用。     

Dry etching of poly-Si/TaN/HfSiON gate stack for advanced complementary metal-oxide-semiconductor devices

A novel dry etching process of a poly-Si/TaN/HfSiON gate stack for advanced complementary metal-oxide-semiconductor（CMOS） devices is investigated.Our strategy to process a poly-Si/TaN/HfSiON gate stack is that each layer of gate stack is selectively etched with a vertical profile.First,a three-step plasma etching process is developed to get a vertical poly-Si profile and a reliable etch-stop on a TaN metal gate.Then different BCl₃-based plasmas are applied to etch the TaN metal gate and find that BCl₃/Cl₂/O₂/Ar plasma is a suitable choice to get a vertical TaN profile.Moreover,considering that Cl₂ almost has no selectivity to Si substrate, BCl₃/Ar plasma is applied to etch HfSiON dielectric to improve the selectivity to Si substrate after the TaN metal gate is vertically etched off by the optimized BCl₃/Cl₂/O₂/Ar plasma.Finally,we have succeeded in etching a poly-Si/TaN/HfSiON stack with a vertical profile and almost no Si loss utilizing these new etching technologies.     

Structural and electrical characteristics of lanthanum oxide gate dielectric film on GaAs pHEMT technology

This paper investigates the feasibility of using a lanthanum oxide thin film (La_2O_3) with a high dielectric constant as a gate dielectric on GaAs pHEMTs to reduce gate leakage current and improve the gate to drain breakdown voltage relative to the conventional GaAs pHEMT. An E/D mode pHEMT in a single chip was realized by selecting the appropriate La_2O_3 thickness. The thin La_2O_3 film was characterized: its chemical composition and crystalline structure were determined by X-ray photoelectron spectroscopy and X-ray diffraction, respectively.La_2O_3 exhibited good thermal stability after post-deposition annealing at 200, 400 and 600 ℃ because of its high binding-energy (835.6 eV). Experimental results clearly demonstrated that the La_2O_3 thin film was thermally stable.The DC and RF characteristics of Pt/La_2O_3/Ti/Au gate and conventional Pt/Ti/Au gate pHEMTs were examined.The measurements indicated that the transistor with the Pt/La_2O_3/Ti/Au gate had a higher breakdown voltage and lower gate leakage current. Accordingly, the La_2O_3 thin film is a potential high-k material for use as a gate dielectric to improve electrical performance and the thermal effect in high-power applications.     

InP基一镜斜置三镜腔型光电探测器理论分析及实验研究

介绍了一种新型长波长InP基一镜斜置三镜腔型（OMITMiC）光电探测器，并对其进行了数值模拟。介绍了该光电探测器的两项关键制备工艺。首先，利用动态掩膜湿法腐蚀技术，通过调节HCl：HF：CrO3腐蚀溶液的选择比。在与InP晶格匹配的In0.72Ga0.28As0.6P0.4外延层上制备出了不同倾角的楔形结构。其次，利用选择性湿法腐蚀技术，通过FeCl3；H2O溶液对In0.53Ga0.47As牺牲层的腐蚀，制备出了具有InP／空气隙的高反射率分布式布拉格反射镜（DBR）。     

硅片背面铜污染的清洗

H2SO4/H2O2/H2O、HNO3/HF和HF/H2O2/H2O为半导体芯片生产过程中三种去除硅片背面铜污染的化学清洗液。在单片湿法清洗机上采用这三种化学液对直径300 mm具有类似于实际生产中铜污染的硅片进行了清洗,结果发现H2SO4/H2O2/H2O在清洗过程中不对硅片表面的Si3N4膜产生损伤,但铜污染的去除效率较低;HNO3/HF和HF/H2O2/H2O对Si3N4膜产生微量刻蚀,从而去除扩散至硅片内部铜污染,从而显示出较佳的去除效果。通过比较HF/H2O2/H2O中HF体积分数与Si3N4膜刻蚀深度和清洗后铜原子浓度,HF的体积分数为1.5%时,可以使硅片表面铜原子浓度降至1010cm-2以下,并且Si3N4膜厚的损失小于1 nm。     

Improved etching method for microelectronic devices with supercritical carbon dioxide

Aqueous etchants used in traditional wet etching for the production of integrated circuits and MEMS devices hinder the processes and pose environmental difficulties. Therefore, we developed an improved dry etching method with HF/Pyridine (7:3) in supercritical carbon dioxide. Etch rates of BPSG, P-TEOS, Thermal SiO₂ and SiN with dry etching method were several times higher than those in wet etching. Etch rates were found to be a function of temperature, HF concentration, and the kind of co-solvents. The presence of alcoholic co-solvents, especially IPA with HF/Pyridine etchant greatly increased the etch rate of BPSG. Etch selectivity could be controlled with the etchant concentration.     

铋基焦绿石薄膜的湿法刻蚀方法研究

介绍了一种能对铋基焦绿石薄膜进行湿法刻蚀的有效方法,研究了HF,NH4F和HNO3的水溶液对铌酸锌铋(Bi1.5Zn1.0Nb1.5O7,BZN)和铌酸镁铋(Bi1.5MgNb1.5O7,BMN)两种铋基焦绿石薄膜的刻蚀情况。结果表明,刻蚀配比V(HF)∶m(NH4F)∶V(HNO3)∶V(H2O)为10mL∶3g∶10mL∶10mL时,BZN和BMN薄膜能得到有效刻蚀,刻蚀速率分别为7nm/s和4nm/s,图形刻蚀精度高。最后讨论了该刻蚀液对铋基焦绿石薄膜的刻蚀机理,加入NH4F作为络合剂能避免刻蚀过程中三氟化铋BiF3难溶沉淀物的生成,加入HNO3作为助溶剂可以调节刻蚀速率,从而提高湿法刻蚀的图形精度。     

Interlevel dielectric via etch process monitoring by atomic forcemicroscopy

The use of AFM for in-line monitoring of an interlevel dielectric via plasma etching step is reported. By comparing etch depths, to via types contacting both Au- and W-based metals, the AFM can non-destructively determine whether micrometre-sized vias have been cleared. Owing to the etch selectivity of the SF₆/O₂ plasma, the Au-based ohmic metal acts as an etch stop whereas the W-based refractory gate contact continues to etch     

同步辐射光刻的X射线反射谱表征

采用X射线反射（XRR）谱对同步辐射导致的氧化物薄膜的刻蚀进行了在位测试,结果表明波长为0．154nm的单色X光在室温下可对MgO和Cr2O3产生轻微的刻蚀。与文献中大量报道的同步辐射X射线光刻及烧蚀不同．这是单色X射线光刻的首次报道。尽管刻蚀速率极慢,但利用XRR谱的高分辨率,成功地检测到了膜厚的减薄。     

A comparative study of wet and dry selective etching processes for GaAs/AIGaAs/lnGaAs pseudomorphic MODFETs

The etching characteristics of Al_xGa_1-xAs in citric acid/H₂O₂ solutions and SiCl₄/SiF₄ plasmas have been studied. Using a 4:1 solution of citric acid/H₂O₂ at 20° C, selectivities of 155, 260, and 1450 have been obtained for GaAs on Al_xGa_1-xAs withx = 0.3,x = 0.45, andx = 1.0, respectively. Etch rates of GaAs in this solution were found to be independent of line widths and crystal orientations for etched depths up to 1000?. GaAs etch profiles along [110] and [110] directions displayed different slope angles as expected. Selective reactive ion etching (SRIE) using SiCl₄/SiF₄ gas mixtures at 90 mTorr and -60 V self-biased voltage yielded selectivities between 200 and 500 forx values ranging from 0.17 to 1.0. SRIE etch rates for GaAs were relatively constant for etch depths of less than 1000?. At greater etch depths, etch rates varied by up to 76% for line widths between 0.3 and 1.0μm. Both selective wet etch and dry etch processes were applied to the fabrication of pseudomorphic GaAs/AIGaAs/lnGaAs MODFETs with gate lengths ranging from 0.3 to 2.5 μm on heterostructures with an embedded thin AlAs etch stop layer. A threshold voltage standard deviation of 13.5 mV for 0.3 μ gate-length MODFETs was achieved using a 4:1 citric acid/H₂O₂ solution for gate recessing. This result compares favorably with the 40 mV obtained using SRIE, and is much superior to the 230 mV achieved using the nonselective etch of 3:1:50 H₃PO₄: H₂O₂: H₂O. This shows that selective wet etching using citric acid/H₂O₂ solutions in conjunction with a thin Al_xGa_1-xAs(x ≥ 0.45) etch stop layer provides a reasonably simple, safe, and reliable process for gate recessing in the fabrication of pseudomorphic MODFETs.