Contactless electromodulation for the nondestructive,room-temperature analysis of wafer-sized semiconductor device structures

This paper reviews the use of the contactless, nondestructive electromodulation methods of photoreflectance and contactless electroreflectance for the room temperature characterization/qualification of semiconductor device structures, including heterojunction bipolar transistors (HBT's), pseudomorphic high electron mobility transistors, quantum-well lasers, vertical cavity surface-emitting lasers, multiple-quantum-well infrared detectors, and solar cells. Special attention is paid to some recent results on (a) the illumination dependence of the evaluated electric fields (and associated doping levels) in the emitter/base and collector/base regions of GaAs-GaAlAs HBT's and (b) a pseudomorphic InGaAs-GaAs-InGaP 0.98 μm single-quantum-well laser structure     

Advances in Linear Modeling of Microwave Transistors

Heterojunction field effect transistors (HFET) based on gallium nitride (AlGaN/GaN) and metal semiconductor field effect transistors (MESFETs) based on silicon carbide (SiC) are the preferred transistors for high-power amplifier circuit designs rather than MESFETs, high electron mobility transistors (HEMTs) and pseudomorphic HEMTs based on gallium arsenide (GaAs) or indium phosphide (InP) semiconductor technology. While AlGaN/GaN and SiC are good candidates for high-power applications, GaAs and InP semiconductor technologies are the preferred transistors in low-power, low-voltage, and low-noise applications [1].     

Fabrication of flat micro‐gap electrodes for molecular electronics

Recently, organic molecular electronic devices such as molecular thin‐film transistors have received considerable attention as possible candidates for next‐generation electronic and optical devices. This paper reports on fabrication technologies of flat metallic electrodes on insulating substrates with a micrometer separation for high‐performance molecular device evaluation. The key technologies of fabricating planar‐type electrodes are the liftoff method by the combination of bilayer photoresist with overhang profile, electron beam evaporation of thin metal (Ti and Au) films, and SiO₂‐CMP (Chemical Mechanical Polishing) method of CVD (Chemical Vapor Deposition)‐deposited TEOS (tetraethoxysilane)–SiO₂ layer. The raggedness of the electrode/insulator interface and the electrode surface of the micro‐gap electrodes were less than 3 nm. The isolation characteristics of fabricated electrodes were on the order of 10¹³ ohms at room temperature, which is sufficient for evaluating electronic properties of organic thin‐film devices. Finally, pentacene FET (Field Effect Transistor) characteristics are discussed fabricated on the micro‐gap flat electrodes. The mobility of this FET was 0.015 cm²/Vs, which was almost on the order of the previous results. These results suggest that high‐performance organic thin‐film transistors can be realized on these advanced electrode structures. © 2005 Wiley Periodicals, Inc. Electr Eng Jpn, 152(2): 39–46, 2005; Published online in Wiley InterScience ( www.interscience.wiley.com ). DOI 10.1002/eej.20152     

Numerical modeling of TeraHertz electronic devices

We investigate by means of Monte Carlo simulations the physical processes associated with the emission of TeraHertz radiation in different electronic devices. We analyze four alternative and complementary strategies which seem to be promising candidates to obtain the TeraHertz emission: (1) a nitride maser based on the optical-phonon transit-time resonance, (2) the high–order harmonic generation in bulk materials and nanometric Schottky-barrier diodes, (3) the excitation of coherent plasma oscillations in micron and submicron diodes, (4) the current instabilities and plasma oscillations in high electron mobility transistors (HEMT). The numerical results show that several physical mechanisms can be exploited to increase significantly the operating frequency of these devices and the best conditions to optimize the radiation emission in the TeraHertz range are studied in detail.     

An improved model to assess temperature-dependent DC characteristics of submicron GaN HEMTs

A modified analytical model for the current–voltage (I–V) characteristics of AlGaN/GaN high-electron-mobility transistors (HEMTs) is presented, considering the temperature-dependent: (a) Schottky barrier height, (b) energy bandgap discontinuity, (c) carrier mobility, and (d) saturation velocity. It is demonstrated that the Schottky barrier height and energy bandgap discontinuity decrease with increase of the temperature. The effective mobility of the two-dimensional electron gas (2-DEG) also decreases with increasing temperature, causing a reduction in the output current of the device. The model was tested over a wide range of temperatures (300–500 K) and bias, and it was observed that the developed model can successfully predict the I–V characteristic of the device with reasonable accuracy, especially at high temperatures (\(\sim 500\) K). It is shown that the developed model offers, on average, a 39 % improvement for the temperature variation, from 300–500 K, relative to the best model reported in literature.     

Modeling of some electrical parameters of a MOSFET under applied uniaxial stress

A semi analytical model describing the bulk mobility for electrons in strained-Si layers as a function of applied uniaxial strain applied at the gate has been developed in this paper. The uniaxial stress has been applied through the silicon nitride cap layer. The effects of uniaxial stress are understood on all the three components of mobility i.e. phonon, columbic and surface roughness mobility. The results show that the electron mobility is a strong rising function of applied uniaxial strain. Flatband voltage, Depletion Charge density, Inversion charge density, Energy gap and Effective surface electrical field have been analytically modeled. There is a sharp increase in the vertical electrical field and inversion charge density and decrease in the energy gap, depletion charge density and the flatband voltage when the uniaxial stress is applied. The electron mobility results have also been compared with the experimentally reported results and show good agreement.     

基于GaN HEMT的半桥LLC优化设计和损耗分析

较之于传统硅器件,新出现的增强型氮化镓晶体管GaN HEMTs(gallium nitride high electron mobility transistors)具有很高的开关速度和高功率密度的特性,可以为直流变换器提供有效的改进。为了解决GaN HEMT在硬开关应用场合下的波形振荡并提高功率密度和效率,采用半桥LLC谐振变换器为本次应用的拓扑结构。以减小损耗为目的,优化了LLC的谐振参数和死区时间。在400 V输入电压、开关频率300 kHz和输出电压18 V电流12 A的测试条件下,效率达到95.59%。最后对变换器的损耗来源进行分析,损耗的理论计算值接近实际测量值,证明了方法具有一定的实用性。     

A high output power and low phase noise GaN HEMT VCO with array of switchable inductors

This paper presents cross‐coupled voltage‐controlled oscillators (VCOs) involving array of switchable inductors (i.e., N  = 1 and N  = 2 switchable inductors) and implemented using gallium‐nitride high electron mobility transistors on Si substrate technology for worldwide interoperability for microwave access applications. Band selection and coarse frequency tuning were achieved using the array of switchable inductors, whereas fine tuning was controlled using varactors. Two bands were obtained using the one‐stage switchable inductor VCO operating in the ranges 3.41–3.57 GHz and 3.85–3.94 GHz. The VCO output power (P_out) was 21.8 dBm at 3.57 GHz from a 10‐V power supply. Four continuous bands were obtained using the two‐stage switchable inductors VCO operating in the range of 3.16–3.4, 3.25–3.64, 3.48–3.71 and 3.64–3.9 GHz, respectively. An additional band was generated by fine‐tuning the inductance through mutual coupling between the transmission line and one of the inductors. The proposed two‐stage switchable inductors VCO provided a 21% tuning range at frequencies ranging with a control voltage ranging from 12 to 20 V, a low phase noise of −123 dBc/Hz at a 1‐MHz offset from a 3.3‐GHz carrier and a P_out of 21 dBm at 3.5 GHz from a 10‐V power supply. Copyright © 2017 John Wiley & Sons, Ltd.     

Study of Electron Transport in SOI MOSFETs Using Monte Carlo Technique with Full-Band Modeling

Effects of conduction-band non-parabolicity on electron transport properties in silicon-on-insulator (SOI) metal-oxide-semiconductor field effect transistors (MOSFETs) are studied by performing Monte Carlo simulation with a full-band modeling. An empirical pseudo-potential method is adopted for evaluating the two-dimensional electronic states in SOI MOSFETs. SOI-film thickness dependence of phonon-limited mobility, drift-velocity and subband occupancy is calculated and the results are compared with those of a simple effective mass approximation. The non-parabolicity effects are found to play an important role in 4-fold valleys under higher applied electric fields or at higher temperatures.     

Stochastic modeling of bipolar resistive switching in metal-oxide based memory by Monte Carlo technique

A stochastic model of the resistive switching mechanism in bipolar metal-oxide based resistive random access memory (RRAM) is presented. The distribution of electron occupation probabilities obtained is in agreement with previous work. In particular, a low occupation region is formed near the cathode. Our simulations of the temperature dependence of the electron occupation probability near the anode and the cathode demonstrate a high robustness of the low occupation region. This result indicates that a decrease of the switching time with increasing temperature cannot be explained only by reduced occupations of the vacancies in the low occupation region, but is related to an increase of the mobility of the oxide ions. A hysteresis cycle of RRAM switching simulated with the stochastic model including the ion dynamics is in good agreement with experimental results.     

垂直结构氮化镓功率晶体管的材料与工艺问题

硅功率器件已接近其理论物理性能的极限。基于宽禁带半导体材料的电力电子系统能够实现更高的功率密度和电能转换效率,而具有高临界电场和载流子迁移率的氮化镓被认为是未来高功率、高频和高温应用的最有希望的候选者之一,而由品质因子给出的氮化镓基功率器件的综合性能具有大于1 000倍于硅器件的理论极限。目前已产业化的氮化镓功率晶体管主要基于水平结构,但垂直结构更有利于实现更高电压和更大电流。随着氮化镓衬底材料的逐渐成熟,近期垂直结构氮化镓功率器件成为了学术界和产业界的研究热点,并被认为是下一代650～3 300 V电力电子应用的候选器件。基于此,回顾了垂直结构氮化镓晶体管的最新进展,特别是与器件相关的材料和工艺问题,并总结了开发高性能垂直结构氮化镓功率晶体管的主要挑战。     

A novel efficiency‐enhancement topology: GaN high‐electron mobility transistors with waveform‐modulation structure composed of Schottky diodes

To improve the power‐added efficiency (PAE) of the gallium nitride (GaN) high‐electron mobility transistor (HEMT) in radio frequency applications, this paper studies the relationship between the nonlinearity of the gate capacitance and the PAE of the GaN HEMTs. The theoretical analysis and simulation results demonstrate that the nonlinearity of the gate capacitance modulates the signal phase at the GaN HEMT input and increases the average drain current, leading to increased power consumption and reduced PAE. Then, an efficiency‐enhancement topology for GaN HEMTs that employs the waveform‐modulation effect of Schottky diodes to reduce power consumption and improve efficiency is presented. The efficiency‐enhancement topology for a 4 × 100‐μm GaN HEMT with waveform‐modulation diodes is then fabricated. Results of load‐pull test demonstrate that the novel topology can increase the PAE of the 4 × 100‐μm GaN HEMT by more than 5% at 8 GHz. The novel efficiency‐enhancement topology for GaN HEMTs proposed in this paper will be suitable for applications that demand high‐efficiency GaN HEMTs or circuits.     

ANN modeling for design of a matched low noise pHEMT amplifier for mobile application

For high quality performance, future efficient wireless communication systems require a Broadband Amplifier in the frequency range under consideration. When such an amplifier is plugged into the measuring path it would enable the system to perceive even the weakest of signals. To achieve this, a new Scattering-parameter model that is valid for a wide frequency range has been developed for microwave analysis of a pseudomorphic high electron mobility transistors (pHEMT). The developed neural network model is used for designing a pHEMT power amplifier. The calculated S-parameters, gain and minimum noise figure from the artificial neural networks (ANN) model are the parameters used to design the low noise pHEMT power amplifier. The various gains so obtained from the S-parameters have been plotted with the frequency and it was found to yield a close fit to the simulated model. Neural network training has been done using Levenberg-Marqaurdt back propagation algorithm implemented in ANN toolbox of MATLAB software. All the results have been compared with the experimental data that showed a close agreement and validated our model. The calculated S-parameters, gain and minimum noise figure from the ANN model are the parameters used to design a stabilized and matched LNA.     

Modelling and design considerations on CML gates under high‐current effects

In this paper, the effect of the transit time degradation of bipolar transistors on the power‐delay trade‐off in CML gates and their design is dealt with. A delay model which accounts for the transit time increase due to the high bias current values used in high‐speed applications is derived by generalizing an approach previously proposed by the same authors (IEEE Trans. CAD 1999; 18 (9):1369–1375; Model and Design of Bipolar and MOS Current—Mode Logic (CML, ECL and SCL Digital Circuits), Kluwer Academic Publisher: Dordrecht, 2005). The resulting closed‐form delay expression is achieved by properly simplifying the SPICE model, and has an explicit dependence on the bias current which determines the power consumption of CML gates. Accordingly, the delay model is used to gain insight into the power‐delay trade‐off by considering the effect of the transit time degradation in high‐speed designs. In particular, the cases where such effects can be neglected are identified, to better understand how the transit time degradation affects the performance of CML gates for current bipolar technologies. The proposed model has a simple and compact expression, thus it turns out to be suitable for pencil‐and‐paper evaluations, as well as fast timing analysis. Simulations of CML circuits with a 20‐GHz bipolar process show that the model has a very good accuracy in a wide range of current and loading conditions. Copyright © 2005 John Wiley & Sons, Ltd.     

The compact d.c. electrothermal model of power MOSFETs for SPICE

This paper concerns the problem of modelling of power MOS transistors in SPICE. In the paper the new form of the electrothermal d.c. model (ETM) of the considered class of power devices is proposed. The ETM is based on the modified Shichman–Hodges model, in which the generation current, the breakdown voltage, the sub‐threshold region, the thermally dependent series resistances and self‐heating are included. The device inner temperature calculated from the thermal model is the sum of the ambient temperature and the product of the electrical power dissipated inside the device and its thermal resistance. The presented model has been verified experimentally. The results of calculations and measurements of MTD15N06V (ON Semiconductor) and IRF840 (International Rectifier) transistors are given as well. Copyright © 2009 John Wiley & Sons, Ltd.     

Statistical study of the effect of interface charge fluctuations in HEMTs using a 3D simulator

The intrinsic parameter fluctuations associated with the discreteness of charge and matter become an important factor when the semiconductor devices are scaled to nanometre dimensions. The interface charge in the recess regions of high electron mobility transistors (HEMTs) has a considerable effect on the overall device performance. We have employed a 3D parallel drift-diffusion device simulator to study the impact of interface charge fluctuations on the I-V characteristics of nanometre HEMTs. For this purpose, two devices have been analysed, a 120 nm gate length pseudomorphic HEMT with an In_0.2Ga_0.8As channel and a 50 nm gate length InP HEMT with an In_0.7Ga_0.3As channel.     

Bulk Grain Resistivity of ZnO-Based Varistors

We study the temperature dependence of grain resistivity in ZnO ceramic varistors (300–430 K), finding a positive temperature coefficient (PTC). We devise a high-frequency procedure that allow us to obtain the concentration and energy position of the shallow donor. The observed behavior is consistent with a shallow donor approaching complete ionization, and with an electron mobility mainly controlled by lattice (both optical and acoustical) scattering. The impact of this behavior on varistor performance under high-current pulse loads is discussed.     

3D Parallel Simulations of Fluctuation Effects in pHEMTs

The use of 3D simulations is essential in order to study the effects of fluctuations when devices are scaled to deep submicron dimensions. A 3D drift-diffusion device simulator has been developed to effectively simulate pseudomorphic high electron mobility transistors (pHEMTs) on a distributed memory multiprocessor computer. The drift-diffusion equations are discretized using a finite element method on an unstructured tetrahedral mesh. The obtained set of equations is solved in parallel on an arbitrary number of processors using the message-passing interface library. We have applied our simulator to a 120 nm pHEMT based on the Al_0.3Ga_0.7As/In_0.2Ga_0.8As interface and carried out a calibration to real experimental data.     

Electron mobility in silicon and germanium inversion layers: The role of remote phonon scattering

We calculate the electron mobility in Si and Ge inversion layers in single-gate metal-oxide-semiconductor field effect transistors. Scattering with bulk phonons, surface roughness and remote phonons is included in the mobility calculations. Various high-κ dielectric materials are considered for both Si and Ge substrates. Overall, Ge outperforms Si, but in general Ge is more affected by the use of high-κ dielectrics. HfO₂ degrades the mobility substantially compared to SiO₂ for Si substrates and may prohibitively degrade performance. HfO₂ with Ge yields an improvement over Si with a mobility enhancement ≈3× at an electron sheet density of 1×10¹³ cm⁻³.     

Modelling DC characteristics of GaAs MESFETs in a wide range of temperatures

In this paper, a new semiempirical DC thermal model of low‐ and high‐power GaAs MESFETs is proposed. The model takes into account the effect of device negative output conductance and simulates external thermal effects modelling the dependence on temperature of the device threshold voltage and the maximum saturation drain–source current. A number of GaAs MESFETs, very different from a geometrical and technological point of view, have been characterized as a function of temperature and modelled by our model with high accuracy. The CPU extraction time results are moderate in any example. Results have been compared with the Rodriguez–Tellez model, showing improvements of accuracy better than 30 per cent. The model can be successfully used n MMIC CAD applications. Copyright © 2001 John Wiley & Sons, Ltd.