利用激光微敷电子胶（LMCEP）在绝缘基板上直接制造电子元件

概述了利用激光微敷电子胶(LMCEP)在玻璃、陶瓷和有机层压板之类的绝缘基板上直接制造电子元件和导线的新方法。采用计算机辅助设计/计算机辅助制造(CAD/CAM)能力和无须掩模的这种技术,成功地制造了具有不同图形的导电性金属线和电阻器。     

An assessment of the applicability of embedded resistor trimming and rework

The successful use of embedded resistors in many applications will require that the fabricated resistors be trimmed prior to lamination into printed circuit boards to attain required design tolerances. Depending on the application, the economic value of the board being fabricated, and the process used to create the embedded resistors, it may also be prudent to consider reworking resistors that are incorrectly trimmed or with initial values that are too large (untrimmable resistors). This paper uses a model of the resistor/board yield coupled with a cost model of the trim and rework processes to identify conditions under which applications should neither trim nor rework, trim but not rework, or perform both trimming and rework of embedded resistors, as a function of the design tolerance for the resistors and the accuracy with which the embedded resistors can be fabricated. Example results are presented for several applications ranging from small boards with a high density of embedded resistors to large boards with a low density of embedded resistors. Distinct regions of trimming and rework applicability that are nearly application independent can be identified as a function of design tolerance, printing/plating/etching variation, and the characteristics of the trimming process.     

Quantitative Analysis of Resistance Variations in Nickel-Phosphorus (NiP) Resistors

Embedded resistors can be fabricated by plating resistive Nickel-Phosphorus (NiP) alloy to form resistors on circuit boards. As-deposited NiP alloy resistors typically have poor resistance tolerances and require tuning by costly laser trimming to meet specifications. The cost of the resistors can be reduced if the tolerances can be reduced without laser trimming. In this study, a group of parameters affecting patterning accuracies, plating and sheet resistivities were varied to evaluate their effects on the resistance tolerances of electroless-plated NiP resistors. The effect of the substrate on sheet resistivity variations was also characterized. Design guidelines to obtain NiP resistors with low tolerance without laser trimming arc discussed.     

镍-磷（Ni—P）电阻器的电阻变化的定量分析

在PCB上镀复形成电阻器的电阻性镍-磷（Ni-P）合金可以制造嵌入电阻器。这样沉积的Ni-P合金电阻器具有不良的电阻公差,要求采用旨在满足规格的昂贵的激光修整进行调节。如果无须激光调整即可降低公差,则可降低电阻器成本。本文中,变化影响图形精度、镀层和薄膜电阻率的一组参数,以评价它们对化学镀Ni-P电阻器的电阻公差的影响。还表征了基材对薄膜电阻率变化的影响。还讨论了无须激光调整可以获得低公差的Ni-P电阻器的设计指南。     

埋入电镀电阻在高速线路中的应用

埋入电阻是实现高频电路的重要方法之一。现已开发出在内层要求精确电镀上电阻元件的工艺,这意味着PCB制造厂可采用各种类型层压板材料,根据不同电镀时间得到从25 Ω到100 Ω范围内的方块电阻值(电阻率),而不是采用各种不同电阻值金属箔的基材来制备不同阻值的埋入电阻。采用常规PWB的活化和化学镀等制造步骤便可制作这种电阻,这种埋入电阻工艺是易于激光检修并层压到多层板内部是很稳定的。这种埋入电阻经过多层层压,温度变化或者显露于潮湿环境下表明电阻值是很小改变的,经过模拟电路运作具有好的稳定性。     

Lasers speed up board production

A technology for writing conductor patterns directly on photoresist simplifies the manufacture of printed-circuit boards and also multiplies yields. If a laser beam is switched on and off as it scans, it can be made to trace a pattern on a light-sensitive material directly, without intervening steps. There is no need to prepare a photonegative, or phototool, to block light from background regions, as is done at present in "printing" circuit boards. The laser can scan conductors directly on photoresist covering an embryonic copper-clad nonconductive circuit board; subsequent board processing remains conventional-developing the resist, exposing and etching part of the copper surface, and removing the rest of the resist. In this way, the up-and-coming laser direct imaging (LDI) systems eliminate the need for a phototool and thereby slash production time of circuit board prototypes by at least one half. So far, several manufacturers of prototypes and medium volumes of printed-circuit boards (about 100 m² per day) have adopted LDI. In contrast with older technologies, LDI can produce even large panels (up to 750 mm by 600 mm) with fine features (conductor lines and spaces, for example) at high yields     

新型聚酰亚胺多层印制电路板可靠性研究

随着电子产品向着更小更轻薄,且功能更强大的方向发展,各种类型的高密度电路板应运而生。“全聚酰亚胺IVH结构”多层电路板成为下一代电路板的候选,该类电路板由聚酰亚胺薄膜一次压合而成,与传统的玻璃布树脂板相比有以下特点：厚度薄（六层板厚小于300μm）、低介电常数、无卤、高阻燃。其另一特点是其内部互联结构,实现各金属层间互联的过孔由激光钻产生,并填入特殊导电胶。文章考察了高低温冲击实验（-25℃／125℃）过程中孔电阻更化情况,并通过数值模拟进行了验证。     

一种激光微细熔覆直写布线的新技术

激光直写技术因其不需要掩模就可以在绝缘基板表面直接制备各种高精度、复杂形状的导电层而受到广泛重视。但是，布线速度过低和工艺复杂一直是阻碍该技术工业化应用的瓶颈。提出了一种以导电金属粒子、有机成膜物质构成的复合导电浆料为熔覆物质，以有机环氧板为绝缘基板，采用CO2激光加热直接制备线路板的新工艺、新方法。所布导线宽度为350μm，布线速率为2～20mm／s，所用的激光功率为0～20W，光斑直径约为100μm。系统研究了激光直写导电层的组织结构特征、导线与基板的结合强度以及导线导电率的变化特征。结果表明，激光微细熔覆直写布线层与基材结合牢固，所布导线的电阻率与导电银颗粒的体积分数及激光功率的大小有关，工艺参数与材料配比合适时，导线电阻率可以达到10^-6Ωcm的数量级，能够满足工业应用的要求。最后，对普通环氧树脂板下激光微细熔覆金属导电浆料直写导线时导线的形成机理和导电机理进行了分析。     

激光微细熔覆柔性直写厚膜导带组织性能的研究

随着表面组装以及电子元器件的微型化和密集化程度增加．对内部互连导线微细化以及高质量高性能程度的要求日渐严格．而传统技术越米越不能满足这种快速发展的需求。采用激光微细熔覆柔性直写技术，在玻璃基板上直接制备高质量高性能的微细导带。通过控制各工艺参数的变化所引起组织形貌的变化判定形成导带的性能的好坏和质量的优劣，优化了工艺参数，并采用该参数进行实际图形的制备。结果表明．所制备的导带导电性好、结合强度高、焊接性好、表面平整度高，适合于产品的智能化批量生产和精微细图形的制作与修复。     

Application-specific economic analysis of integral passives inprinted circuit boards

This paper presents an application-specific economic analysis of the conversion of discrete passive components (resistors and capacitors) to integral passives that are embedded within a printed circuit board. In this study we assume that integral resistors are printed or plated directly onto wiring layers (as opposed to requiring a dedicated layer), that bypass capacitors, if present, are embedded by dielectric substitution into existing reference plane layers, and that singulated nonbypass capacitors, if present, are embedded using dedicated layer pair addition. The model presented performs three basic analyses. 1) Board size analysis is used to determine board sizes, layer counts, and the number of boards that can be fabricated on a panel. 2) Panel fabrication cost modeling including a cost of ownership model is used to determine the impact of throughput changes associated with fabricating integral passive panels. 3) Assembly modeling is used to determine the cost of assembling all discrete components, and their associated inspection and rework. The combination of these three analyses is used to evaluate size/cost tradeoffs for several example systems including the NEMI hand-held emulator, a picocell board, and a fiber channel card     

A new reliability prediction model for telecommunication hardware

An analysis of measured field failure rates of printed circuit boards has been performed. The “part count” method currently used for reliability predictions was evaluated. A new model for electronic reliability prediction has been proposed. It uses statistics from board and system tests performed at the production plant and the number of conductive layers on the board. The report shows that there is a correlation between production test statistics and field performance, for high-volume boards. The proposed model shows that a high production test yield indicates high field reliability. This means that if actual production test results are poor, actions can be taken to improve reliability before numerous boards are delivered to customers.     

Environmental Qualification Testing and Failure Analysis of Embedded Resistors

Embedding passive components (capacitors, resistors, and inductors) within printed wiring boards (PWBs) is one of a series of technology advances enabling performance increases, size and weight reductions, and potentially economic advantages in electronic systems. This paper explores the reliability testing and subsequent failure analysis for laser-trimmed Gould subtractive nickel chromium and MacDermid additive nickel phosphorous embedded resistor technologies within a PWB. Laser-trimmed resistors that have been “reworked” using an inkjet printing process to add material to their surface to reduce resistance have also been considered. Environmental qualification testing performed included: thermal characterization, stabilization bake, temperature cycling, thermal shock and temperature/humidity aging. In addition, a pre/post-lamination analysis was performed to determine the effects of the board manufacturing process on the embedded resistors. A failure analysis consisting of optical inspection, scanning acoustic microscope (SAM) and environmental scanning electron microscope (ESEM) imaging, and PWB cross-sectioning was employed to determine failure mechanisms. All the embedded resistors were trimmed and the test samples included resistors fabricated both parallel and perpendicular to the weave of the board dielectric material. Material stability assessment and a comparison with discrete resistor technologies was performed.     

High-density printed circuit board using B2itTM technology

We have developed the B²it^TM printed circuit board, and presented a related paper entitled, A High-density substrate with buried bump interconnection technology, at the IMC meeting in April 1996. Since then, we have been applying this technology to a variety of boards, and report here, on the application of B²it^TM to semiconductor packaging. The product has 0.1 to 0.2 diameter bumps (hereafter called fine bumps). To produce a multilayer high-density printed circuit board, we need to add conductive bumps to each layer over a base layer, which we call the en bloc laminating process. By repeating the en bloc laminating process multiple times, a multilayer stacked array can be fabricated. Signals can go down to internal layers directly from the surface pads via bumps, which is effective for a substrate such as a BGA type package. By using the B²it^TM method, it is possible to omit the outerlayer plating process. This is a advantageous for fine line patterning, because the circuit can be patterned by etching the copper foil alone. We introduced two types of liquid photo resist process, one is the ED method, and the other is the liquid photo-resist process which uses a spin coater     

Innovative circuit board level routing designs for BGA packages

Advances in the performance of electronic devices have resulted in high input/output counts both at the chip and the package level, which has led to the development of new packaging technologies that can accommodate these high counts. This paper presents and analyzes a novel method for the placement of ball grid array (BGA) bonding pads and routing wires on printed circuit boards to maximize signal density, which ultimately reduces the number of circuit board layers needed for routing. This method has been termed as the "balls shifted as needed" method and all the ball placement/trace routing designs shown in this paper are based on this method. We also present a performance metric defined as the number of balls routed out divided by the area of package footprint on the circuit board, and we compare various placement/routing schemes using this method.     

电子装备数字电路板自动检测仪设计

摘要：针对某电子装备数字电路板设计自动检测仪,采用单片机＋FPGA的技术方案,包括信号发生、信号采集、与上位机的USB通信以及连接被测板的接插件四大模块。对不同测试对象输入输出间的差异具有柔性适应能力,无须手工配线,操作简单。由上位PC机驱动运行,测试过程自动化程度高,可在1min内完成单板故障检测。     

印制电路板内埋薄膜电阻和聚合厚膜电阻的可靠性初步评估

多层印制板内埋无源元件,可以节省有源元件安装面积,减小印制板尺寸,提高设备功能、提升安全性,并降低制造成本。由于制作完成后内埋式无源元件不可替换,元件是否拥有长期稳定性和可靠性是制造商最关心的方面。文章给出了内埋NiP薄膜电阻和聚合厚膜电阻持续作业的可靠性测试结果,讨论了无铅焊接模拟和温度循环测试（一40℃～＋85℃）的温度对阻值的影响。     

The effect of epoxy/glass interfaces on CAF failures in printed circuit boards

Reductions in printed circuit board line spacing and via diameters and the increased density of vias with higher aspect ratios (ratio between the thickness of the board and the size of the drilled hole before plating) are making electronic products increasingly more susceptible to material and manufacturing defects. One failure mechanism of particular concern is conductive anodic filament (CAF) formation, which typically occurs in two steps: degradation of the resin/glass fiber bond followed by an electrochemical reaction. Bond degradation provides a path along which electrodeposition occurs due to electrochemical reactions. The path can result from poor glass treatment, from the hydrolysis of the silane glass finish, or from mechanical stresses. Once a path is formed, an aqueous layer, which enables the electrochemical reactions to take place, can develop through the adsorption, absorption, and capillary action of moisture at the resin/fiber interface. This paper describes the concerns with CAF and the methods used for analyzing low-resistance failures. A case study is then given which highlights problems that arose on a commercial circuit board material used by a major telecommunications provider.     

Putting passives in their place [PCB integration]

The next big thing in miniaturization is integrating resistors, capacitors, and inductors into circuit boards. These integrated passives would be a part of the circuit board itself, formed when the board was, so their overall cost would eventually be less than what manufacturers pay at present to buy and solder attach discrete devices. This article examines the advantages of this integration scheme, and looks at the difficulties involved.     

Damage predictions in a chip resistor solder joint on flexible circuit board

Flexible circuit boards are being widely used in the electronic packages. Solders are often used to assemble chip resistors and other components on them. In practice, solder alloys work in high homologous temperatures and experience cyclic temperature loadings. As a result, damage may accumulate in solder materials quickly and this will eventually lead to the failure of the solder joints. In this work, computer modelling technique has been used to predict such damage accumulations in chip resistor solder joints under a range of thermal cycling conditions. It has been documented that the higher and the lower dwell temperatures of a thermal cycle dominate the damages in solder joints. Both the ramp time and the cycle duration have strong influence on the damage accumulation. In general, faster ramp time and longer cycle duration cause more damages. The types of materials used to produce flexible circuit board have also significant impact on the damage accumulation. Polyimide (PI), Polyethylene Naphthalate (PEN) and Liquid Crystal Polymer (LCP) based flexible circuit boards have been compared for their effect on damage in solder joints and the results show that the highest damage could be found in the chip resistor solder joint on the PI-based flexible circuit boards and least damage could be found for the LCP based flexible circuit boards. The results also show that the thicknesses of the constituent layers of different materials in flexible circuit boards are linearly proportional to the damage accumulation in solder joints.     

Integrated capacitors for conductive lithographic film circuits

This paper reports on fabrication of low-value embedded capacitors in conductive lithographic film (CLF) circuit boards. The CLF process is a low-cost and high speed manufacturing technique for flexible circuits and systems. We report on the construction and electrical characteristics of CLF capacitor structures printed onto flexible substrates. These components comprise a single polyester dielectric layer, which separates the printed electrode films. Multilayer circuit boards with printed components and interconnect can be fabricated using this technique