一种抗老化消除浮空点并自锁存的老化预测传感器

随着集成电路芯片制造工艺进入纳米阶段,电路可靠性问题变得越来越严重,以负偏置温度不稳定性效应为代表的电路老化也逐渐成为影响其性能的重要因素.基于老化预测的精确性和传感器功能的多样性,提出了一种抗老化、可编程的老化预测传感器.其中稳定性检测器部分利用反馈回路解决了浮空点问题,同时整合了锁存器部分,实现了对老化预测结果的自动锁存,从而增加了老化预测的精确度,减小了一定的面积开销.最后通过HSPICE模拟器仿真验证了该传感器的优越性,且与经典结构相比降低了约21.43％的面积开销.     

一种可配置的老化预测传感器设计

随着工艺尺寸的缩减,老化导致的电路不稳定现象越来越严重。由于NBTI效应造成的老化是渐进的,因此老化是可预测的。由此提出了一种具有可配置延迟单元的老化预测电路,并将其中的稳定性校验器和锁存器的功能进行了整合。在老化的不同时期,针对老化程度,动态调节延迟单元的延迟大小,得到不同的保护带宽度,从而提高老化预测的准确率。并通过反馈电路达到对稳定性校验器的输出进行锁存的目的。与经典结构相比,电路在面积上平均节省20.6%左右,在功耗方面减少36%左右。Spice模拟器的仿真结果证实了电路的优越性。     

一种用于磁传感器读出电路的双斜率ADC

基于集成片上双斜率ADC结构简单,适用于低频小信号的转换的特点.提出了一种适合于磁场传感器读出电路的可编程双斜率ADC,能够将磁传感器输出的低频模拟小信号转换为高精度的数字信号.针对不同的应用对于转换时间和转换精度的不同要求,可对ADC的精度进行编程配置,有利于提高电路的工作效率.ADC的积分器部分采用差分型开关电容结构以减小芯片面积,并且对积分方式进行了改进,通过叠加积分增加正积分的积分斜率来提高ADC的有效位数.仿真结果显示,ADC的有效位数为11.96bit,在3.3V工作电压下,功耗仅为1.55mW,满足磁传感器小信号读出电路的要求.     

一种集成电路静态老化测试的输入矢量选取方法

在集成电路静态老化测试中,对被测电路持续施加特殊的固定测试矢量,使被测电路产生较大的漏电功耗,有利于其早期失效的发生,获得更好地老化效果.提出一种产生最大漏电功耗的测试矢量选取方法.在被测电路中设置合适的固定故障,通过ATPG方法获取较小的备选测试矢量集合.基于门电路的故障相关输入状态,设计了一种度量指标,可用于辅助在备选测试矢量集合中搜索目标矢量.该度量指标与电路漏电功耗总体上为正相关关系,可有效降低误选测试矢量的风险.     

基于关键路径延时检测的自适应电压缩减技术

为了减小传统的最差情况设计方法引入的电压裕量,提出了一种变化可知的自适应电压缩减(AVS)技术,通过调整电源电压来降低电路功耗.自适应电压缩减技术基于检测关键路径的延时变化,基于此设计了一款预错误原位延时检测电路,可以检测关键路径延时并输出预错误信号,进而控制单元可根据反馈回的预错误信号的个数调整系统电压.本芯片采用SMIC180 nm工艺设计验证,仿真分析表明,采用自适应电压缩减技术后,4个目标验证电路分别节省功耗12.4％,11.3％,10.4％和11.6％.     

开关信号理论与绝热CMOS电路设计

重新定义了钟控信号的表示方法,发展了适用于绝热电路的开关级设计理论.设计了实现全部钟控信号的基本单元电路,这些电路包括单轨和双轨结构,并给出了它们的多种级联方式.所提出电路的功耗与其他绝热电路相当,并工作于二相正弦功率时钟,因此可降低时钟电路的设计难度.这些电路可分别应用于需要基0信号和基1信号的绝热电路设计中.与以往大部分绝热电路不同的是,应用所提出的电路结构可以实现在同一时钟相位有多级电路同时参加运算.这一特性可以有效减少实现复杂逻辑电路时的等待时间以及实现流水结构时所需插入的缓冲器数目.通过对基0信号2∶1数据选择器     

大规模集成电路浮栅ROM器件总剂量辐射效应

提出了一种大规模集成电路总剂量效应测试方法:在监测器件和电路功能参数的同时,监测器件功耗电流的变化情况,分析数据错误和器件功耗电流与辐射总剂量的关系.根据该方法利用60Co γ射线进行了浮栅ROM集成电路(AT29C256)总剂量辐照实验,研究了功耗电流和出错数量在不同γ射线剂量率辐照下的总剂量效应,以及参数失效与功能失效时间随辐射剂量率的变化关系,并利用外推实验技术预估了电路在空间低剂量率环境下的失效时间.     

大规模集成电路浮栅ROM器件总剂量辐射效应

提出了一种大规模集成电路总剂量效应测试方法:在监测器件和电路功能参数的同时,监测器件功耗电流的变化情况,分析数据错误和器件功耗电流与辐射总剂量的关系.根据该方法利用60Co γ射线进行了浮栅ROM集成电路(AT29C256)总剂量辐照实验,研究了功耗电流和出错数量在不同γ射线剂量率辐照下的总剂量效应,以及参数失效与功能失效时间随辐射剂量率的变化关系,并利用外推实验技术预估了电路在空间低剂量率环境下的失效时间.     

用于1T1C型铁电存储器的一种可提高分辨窗口的非对称型分辨结构

本文提出了一种用于单管单电容型铁电存储器的新型非对称信号电流模分辨放大结构,该结构的创新点在于非对称的输入管及在灵敏放大器的参考信号端增加的NMOS反馈管。与参考文献[8]中的传统对称型电流模分辨放大结构相比,该结构可将读出电流的分辨窗口提高53.9%并将数据分辨放大过程的功耗降低14.1%,而分辨放大电路部分的面积仅因此增加7.89%。采用本文所提非对称结构的实验型原型样片基于0.35微米3层金属工艺已获得流片及功能验证成功。     

可用于CMOS图像传感器片上集成的电阻网络

为模仿视网膜中水平细胞对图像信息的处理方式,提出了一种能实现空间滤波功能的CMOS电阻网络,仅由水平电阻(HRES)和偏置电路两部分组成,其偏置电路既能提供偏置电压又可作为OTA电压跟随器.该电路结构简单、电路面积小、功耗低,更利于CMOS图像传感器的片上集成.在0.6μmDPDM标准数字CMOS工艺上完成了电路设计和性能仿真.     

一款消除浮空点并自锁存的老化预测传感器

针对负偏置温度不稳定性引起的组合逻辑电路老化,提出了一款消除浮空点并自锁存的老化预测传感器。该传感器不仅可以预测组合逻辑电路老化,而且能够通过传感器内部的反馈来锁存检测结果,同时解决稳定性校验器在锁存期间的浮空点问题,其延时单元为可控型延时单元,可以控制其工作状态。使用HSPICE软件进行仿真,验证了老化预测传感器的可行性,可以适用于多种环境中且不会影响传感器性能。与同类型结构相比,该传感器的稳定性校验器能够对检测结果进行自锁存,使用的晶体管数量减少了约8%,平均功耗降低了约20%。     

An Improved Global Shutter Pixel with Extended Output Range and Linearity of Compensation for CMOS Image Sensor

An improved global shutter pixel structure with extended output range and linearity of compensation is proposed for CMOS image sensor. The potential switching of the sample and hold capacitor bottom plate outside the array is used to solve the problem of the serious swing limitation, which will attenuate the dynamic range of the image sensor. The non-linear problem caused by the substrate bias effect in the output process of the pixel source follower is solved by using the mirror FD point negative feedback self-establishment technology outside the array. The approach proposed in this paper has been verified in a global shutter CMOS image sensor with a scale of 1024×1024 pixels. The test results show that the output range is expanded from 0.95V to 2V, and the error introduced by the nonlinearity is sharply reduced from 280mV to 0.3mV. Most importantly, the output range expansion circuit does not increase the additional pixel area and the power consumption. The power consumption of linearity correction circuit is only 23.1μW, accounting for less than 0.01％ of the whole chip power consumption.     

1.5 V Sub‐mW CMOS Interface Circuit for Capacitive Sensor Applications in Ubiquitous Sensor Networks

In this paper, a low‐power CMOS interface circuit is designed and demonstrated for capacitive sensor applications, which is implemented using a standard 0.35‐μm CMOS logic technology. To achieve low‐power performance, the low‐voltage capacitance‐to‐pulse‐width converter based on a self‐reset operation at a supply voltage of 1.5 V is designed and incorporated into a new interface circuit. Moreover, the external pulse signal for the reset operation is made unnecessary by the employment of the self‐reset operation. At a low supply voltage of 1.5 V, the new circuit requires a total power consumption of 0.47 mW with ultra‐low power dissipation of 157 μW of the interface‐circuit core. These results demonstrate that the new interface circuit with self‐reset operation successfully reduces power consumption. In addition, a prototype wireless sensor‐module with the proposed circuit is successfully implemented for practical applications. Consequently, the new CMOS interface circuit can be used for the sensor applications in ubiquitous sensor networks, where low‐power performance is essential.     

三值绝热多米诺文字运算电路开关级设计

通过对绝热多米诺电路和多值电路的研究,提出一种新颖的低功耗三值文字运算电路的开关级设计方案。该方案首先通过开关—信号理论推导出逻辑0和2的文字运算电路开关级结构式及电路;然后利用三种文字运算之间互斥与互补的约束关系得到逻辑1的文字运算输出信号,同时通过波形转换电路使电路的输出转换为较规则的缓变梯形波;最后利用Spice软件对所设计的电路进行仿真,结果显示所设计的三值绝热多米诺文字运算电路具有正确的逻辑功能,与常规多米诺三值文字运算电路相比,能耗节省约39%。     

A fault detection sensor for circuit aging using double-edge-triggered flip-flop

In nanoscale technology, transistor aging is one of the most critical problems that impact on the reliability of circuits. Aging sensor is a good online way to detect the circuit aging, which performs during the operating time with no influence of the normal operation of circuits. In this paper, a Double-edge-triggered Detection Sensor for circuit Aging (DSDA) is proposed, which employs data signal of logic circuits as its clock to control the sampling process. The simulation is done by Hspice using 45 nm technology. The results show that this technique is not sensitive to the process variations. The worst case of the detection precision is more than 80% under the different process variations. It can detect aging fault effectively with the 8% power cost and 30% performance cost.     

Delay sensing for long-term variations and defects monitoring in safety–critical applications

The impact of parametric variations on digital circuit performance is increasing in nanometer Integrated Circuits (IC), namely of Process, power supply Voltage and Temperature (PVT) variations. Moreover, circuit aging also impacts circuit performance, especially due to Negative Bias Temperature Instability (NBTI) effect. A growing number of physical defects manifest themselves as delay faults (at production, or during product lifetime). On-chip, on-line delay monitoring, as a circuit failure prediction technique, can be an attractive solution to guarantee correct operation in safety–critical applications. Safe operation can be monitored, by predictive delay fault detection. A delay monitoring methodology and a novel delay sensor (to be selectively inserted in key locations in the design and to be activated according to user’s requirements) is proposed, and a 65 nm design is presented. The proposed sensor is programmable, allowing delay monitoring for a wide range of delay values, and has been optimized to exhibit low sensitivity to PVT and aging-induced variations. Two MOSFET models—BPTM and ST—have been used. As abnormal delays can be monitored, regardless of their origin, both parametric variations and physical defects impact on circuit performance can be identified. Simulation results show that the sensor is effective in identifying such abnormal delays, due to NBTI-induced aging and to resistive open defects.     

A low-cost CMOS dual-mode AC/DC data converter for signal measuring technique

A low-cost CMOS dual-mode AC/DC data converter for signal measuring technique is newly proposed. Instead of traditional full wave rectification, the realized synchronous rectification circuit is more attractive due to the easier integration and lower cost. In this paper, the design strategies of implementing the signal processing of AC and DC modes in the integrated circuit are discussed completely. Proven through SIMULINK in system level and SPICE simulations in circuit level, simulation results show that the proposed dual-mode AC/DC data converter achieves 8-bit resolution in DC mode and 7-bit resolution in AC mode. Measurement results have successfully verified the correct functions and performance of the proposed data converter and confirmed it for AC/DC signal measuring technique. The area of this chip is 710 × 630 μm² and the measured power consumption is 5.1 mW. The proposed dual-mode AC/DC data converter is suitable for the system of analog and mixed-signal boundary scan.     

A novel change-detection scheduler for a network of depth sensors

In many monitoring applications such as smart home and surveillance, deployment of multiple depth sensors increases monitoring area and offers better occlusion handling which is not sensitive to illumination condition in comparison with RGB sensors. However, multiple sensors also increase the volume of data associated with signal processing alongside the associated computational complexity and power consumption. In order to address these drawbacks, this paper proposes a novel change detection algorithm that can be used as a part of a sensor scheduler in a centralized (e.g. star) network configuration. Initially, each sensor in the network performs a unique single scan of the common environment in order to detect any incremental changes in the sensed depth signal. This initial change detection is then used as a basis for several follow-up tasks such as foreground segmentation, background detection, target detection, and tracking for monitoring tasks. Here, instead of processing a complete depth frame, we proposed to utilize a collection of 1D scans of the depth frames. A confidence function is defined that can be used to estimate the reliability of the detected changes in each sensor and to reduce any false positive events which can be triggered by the noise and outliers. Analysis of the proposed confidence function is carried out through performance analysis in the presence of sensor noise and other parameters which can affect the reliability of the sensed data of each sensor. Finally, a score function is defined based on the confidence of the detected parameters and sensor resolution in order to rank and match sensors with the associated objects to be tracked. It results in tracking target(s) by a sensor (or sensors) that offer a high tracking score. This approach offers many advantages such as decreasing the overall system power consumption by placing the sensors with a low confidence value on standby mode and reducing the overall computational overheads.     

Design of a 16 gray scales 320×240 pixels OLED-on-silicon driving circuit

A 320×240 pixel organic-light-emitting-diode-on-silicon (OLEDoS) driving circuit is implemented using the standard 0.5 μm CMOS process of CSMC. It gives 16 gray scales with integrated 4 bit D/A converters. A three-transistor voltage-programmed OLED pixel driver is proposed, which can realize the very small current driving required for the OLEDoS microdisplay. Both the D/A converter and the pixel driver are implemented with pMOS devices. The pass-transistor and capacitance in the OLED pixel driver can be used to sample the output of the D/A converter. An additional pMOS is added to OLED pixel driver, which is used to control the D/A converter operating only when one row is on. This can reduce the circuit's power consumption. This driving circuit can work properly in a frame frequency of 50 Hz, and the final layout of this circuit is given. The pixel area is 28.4×28.4 μm2 and the display area is 10.7×8.0 mm2 (the diagonal is about 13 mm). The measured pixel gray scale voltage shows that the function of the driver circuit is correct, and the power consumption of the chip is about 350 mW.