High Performance Reconfigurable FIR Filter Architecture Using Optimized Multiplier

In mobile communication systems and multimedia applications, need for efficient reconfigurable digital finite impulse response (FIR) filters has been increasing tremendously because of the advantage of less area, low cost, low power and high speed of operation. This article presents a near optimum low- complexity, reconfigurable digital FIR filter architecture based on computation sharing multipliers (CSHM), constant shift method (CSM) and modified binary-based common sub-expression elimination (BCSE) method for different word-length filter coefficients. The CSHM identifies common computation steps and reuses them for different multiplications. The proposed reconfigurable FIR filter architecture reduces the adders cost and operates at high speed for low-complexity reconfigurable filtering applications such as channelization, channel equalization, matched filtering, pulse shaping, video convolution functions, signal preconditioning, and various other communication applications. The proposed architecture has been implemented and tested on a Virtex 2 xc2vp2-6fg256 field-programmable gate array (FPGA) with a precision of 8-bits, 12-bits, and 16-bits filter coefficients. The proposed novel reconfigurable FIR filter architecture using dynamically reconfigurable multiplier block offers good area and speed improvement compared to existing reconfigurable FIR filter implementations.     

Design of non-uniform filter bank transmultiplexer with canonical signed digit filter coefficients

Design of non-uniform filter bank transmultiplexer (NUFB TMUX) with canonical signed digit (CSD) coefficients is presented. NUFB TMUX is preferred in a multicarrier communication system when applications with different data rates are to be multiplexed. If the filter coefficients are represented in CSD format, the hardware complexity of the NUFB TMUX can be reduced. A continuous coefficient NUFB TMUX is designed and the coefficients of the filters are synthesised in CSD format using genetic algorithm (GA). Separate objective functions are formulated for the fitness evaluation of the filters. Chromosomes are encoded as ternary digit strings. New crossover and mutation techniques are introduced to preserve the canonical property of the signed power of two (SPT) representations. For the fast convergence of the GA, positiondependent probability of mutation is used. Simulation results show that the CSD coefficient NUFB TMUX designed using the proposed algorithm has better signal-to-interference ratio (SIR) than that of continuous coefficient NUFB TMUX and CSD coefficient NUFB TMUX obtained by rounding. Frequency responses of its filters are better than that of the filters in CSD coefficient NUFB TMUX obtained by rounding and comparable with that of continuous coefficient NUFB TMUX.     

Design of Linear Phase FIR Filters in Subexpression Space Using Mixed Integer Linear Programming

In this paper, a novel optimization technique is proposed to optimize filter coefficients of linear phase finite-impulse response (FIR) filter to share common subexpressions within and among coefficients. Existing approaches of common subexpression elimination optimize digital filters in two stages: first, an FIR filter is designed in a discrete space such as finite wordlength space or signed power-of-two (SPT) space to meet a given specification; in the second stage, an optimization algorithm is applied on the discrete coefficients to find and eliminate the common subexpressions. Such a two-stage optimization technique suffers from the problem that the search space in the second stage is limited by the finite wordlength or SPT coefficients obtained in the first stage optimization. The new proposed algorithm overcomes this problem by optimizing the filter coefficients directly in subexpression space for a given specification. Numerical examples of benchmark filters show that the required number of adders obtained using the proposed algorithm is much less than those obtained using two-stage optimization approaches.     

Complex coefficient fir digital filters

The complex FIR digital filter is a filter that has complex coefficients in itsZ-domain transfer function. The set of coefficients is determined, based on some criterion, to meet predefined requirements. On this basis, an algorithm is proposed for designing FIR digital filters with asymmetric amplitude response in conjunction with linear phase. Minimax approximation has been adopted for determining the set of coefficients, where the associated set of overdetermined linear equations is solved by using an efficient linear programming algorithm. Computer simulations show that, to meet prescribed specifications, the proposed design algorithm yields a complex FIR digital filter with the lowest order.     

一种低复杂度的稀疏FIR陷波滤波器的设计方法

FIR陷波滤波器具有线性相位、精度高、稳定性好等诸多优势,然而当陷波性能要求较高时,通常需要较高的阶数,导致FIR陷波滤波器硬件实现复杂度大大提高。该文基于稀疏FIR滤波器设计算法和共同子式消除的思想,提出一种低复杂度的FIR陷波滤波器设计方法。该方法首先采用稀疏滤波器设计算法得到满足频域性能设计要求的FIR陷波原始滤波器系数,然后对其进行CSD编码,并分析CSD编码量化系数集中所有的2项子式和孤子的灵敏度,最后根据灵敏度的大小依次选择合理的2项子式或孤子直接合成滤波器系数集。仿真结果表明,新算法设计实现的FIR陷波滤波器比已有的低复杂度设计方法最多可减少51%的加法器,有效地降低了硬件实现复杂度,大大节省了硬件资源。     

Multiplierless filter‐bank based multicarrier system by using canonical signed digit representation

The filter‐bank based multicarrier (FBMC) system is a candidate for designing the physical layer of a cognitive radio because of its spectral efficiency and the spectral containment. The main drawback of such a system compared with orthogonal frequency division multiplexing systems is its high computation complexity, because each subcarrier is shaped by a non‐rectangular prototype filter. Although poly‐phase decomposition is suggested to decrease the sampling rate of filtering, the number of filtering operations (multiplications) is dramatically increased by the growing number of subcarriers and the amount of the desired spectral containment. Hence, hardware implementation of the FBMC system faces challenges such as high electrical power consumption and large silicon area occupation. In order to reduce computational complexity, a multiplierless filter design based on the canonical signed digit (CSD) representation is proposed. In this technique, at first, a prototype filter is designed. Then a pre‐optimization step is employed to adapt the prototype filter coefficients to system objectives and produce an enriched initial seed for genetic algorithm (GA) optimization. Finally, a customized GA is employed to jointly optimize and synthesize filter coefficients into the finite precision CSD representation so that the system objectives such as intersymbol‐interference, interchannel‐interference, and stop‐band attenuation remain unchanged against the full‐precision representation of coefficients. Copyright © 2014 John Wiley & Sons, Ltd.     

应用于ΣΔADC的抽取滤波器的设计与实现

介绍了一种应用于ΣΔADC的抽取滤波器的设计和电路实现方法.通过对传统设计方法的分析,提出了一种可以节省10%硬件利用率的改进方法,同时提出了一种适用于半带滤波器的串并联结构,与传统的半带滤波器相比能够提高50%的硬件利用效率.在面积、速度和功耗的折衷的情况下,灵活应用CSD、CSE和多相分解结构,在0.18μm下实现了0.59 mm2的16位数字抽取滤波器.该滤波器与不应用串并联结构的滤波器相比能够节省18%左右的芯片面积.     

一种Σ-Δ A/D转换器抽取滤波器的设计

设计了一种Σ-ΔA/D转换器中的数字抽取滤波器。该滤波器应用于音频范围,采用多级多采样率的结构,由梳状滤波器、补偿滤波器以及两个半带滤波器组成。滤波器系数用标准符号编码实现,减少了乘法单元的使用。采用Simulink模拟过采样128倍的4位调制器输出;用Verilog编写用于测试的滤波器代码。在Matlab中分析滤波器输出码流,得到的信噪比为101 dB,能够满足高端音频A/D转换器的要求。     

Phase-Compensated Time-Varying Butterworth Filters

One of the important problems of signal processing is to design the filters which possess linear phase characteristics. This paper presents the concept of time-varying Butterworth filters with linear phase. The compensation of the phase characteristics is carried out with the aid of phase shifter which is cascade-connected to the structure of the original Butterworth filter given by the transfer function. The parameters of the phase shifter were calculated in this way that the group delay of the designed filter is possible constant in the filter pass–band. Time varying coefficients were introduced to the phase–compensated filter structure for the purpose of minimization of the filter transient state. This paper contains simulation results of proposed filters and comparison with classic circuits.     

An area-efficient and low-power 64-point pipeline Fast Fourier Transform for OFDM applications

In an orthogonal frequency division multiplexing (OFDM) based wireless systems, Fast Fourier Transform (FFT) is a critical block as it occupies large area and consumes more power. In this paper, we present an area-efficient and low power 16-bit word-width 64-point radix-2² and radix-2³ pipelined FFT architectures for an OFDM-based IEEE 802.11a wireless LAN baseband. The designs are derived from radix-2^k algorithm and adopt a Single-Path Delay Feedback (SDF) architecture for hardware implementation. To eliminate the complex multipliers and read-only memory (ROM) which is used for internal storage of twiddle factor coefficients, the proposed 64-point FFT employs a Canonical Signed Digit (CSD) complex constant multiplier using adders, multiplexers and shifters. The complex constant multiplier (CCM) is modified using common sub-expression sharing block that reduces the area of the design. The proposed radix-2² and radix-2³ pipelined FFT architectures are modeled and implemented using TSMC 180 nm CMOS technology with a supply voltage of 1.8 V. The implementation results show that the proposed architectures significantly reduces the hardware cost and power consumption in comparison to existing 64-point FFT architectures.     

基于MATLAB与CCS的FIR滤波器的C语言实现

为保证所设计的FIR数字低通滤波器具有严格的线性相位,在对几种FIR基本结构的比较之后,采用了线性相位FIR滤波器的直接型结构。使用Matlab内置函数计算出滤波器的系数和检验滤波器的频率响应特性。采用C语言实现数字滤波器的设计,并在集成开发环境代码调式器(Code Composer Studio,CCS)上进行仿真,仿真结果表明,所设计的数字低通滤波器能够满足系统实时性和不失真要求。     

A programmable FIR digital filter using CSD coefficients

An area-efficient programmable FIR digital filter using canonic signed-digit (CSD) coefficients was implemented that uses a switchable unit-delay to allocate the desired number of nonzero CSD coefficient digits to each filter tap. The prototype chip can allocate up to 16 pairs of nonzero CSD coefficient digits for a linear-phase filter, thus realizing filters with 32 linear-phase taps operating at 180 MHz with two nonzero CSD digits per filter tap. Additional nonzero CSD digits can be allocated to filter taps at the penalty of a reduced filter length and a reduced data-rate. The chip was implemented with 16-bit I/O in a die size of 5.9 mm by 3.4 mm using 1.0-μm CMOS technology     

A novel common-subexpression-elimination method for synthesizing fixed-point FIR filters

We propose a common-subexpression-elimination (CSE) method for the synthesis of fixed-point finite-impulse response (FIR) filters. The proposed CSE algorithm considers both the redundancy among the canonic-signed-digit (CSD) filter coefficients and the length of the critical path in the multiplier block of a transposed-form FIR filter. Therefore, the proposed CSE method can perform tradeoff designs between complexity and the throughput rate. The number of adders synthesized by our method is commensurate with that by the graph-dependence algorithms. On the other hand, our method can synthesize a high-order complicated FIR filter in a few seconds.     

自适应格型滤波器新算法及其在语音线性预测合成中的应用

本文从自适应格型滤波器导出自适应线谱对(LSP)滤波,提出了使用最小均方(LMS)型自适应算法逐级更新计算线谱对系数的方法。实验表明,该算法与其它算法比较,具有更高的收敛率和较低的失调。用该算法计算得到的LSP系数进行语音线性预测合成,获得比使用PARCOR系数更好的结果。     

Modified Metaheuristic Algorithms for the Optimal Design of Multiplier-Less Non-uniform Channel Filters

Reconfigurable non-uniform channel filters are now being widely used in software define radio (SDR). The hardware implementation of these filters requires low complexity, low chip area and low power consumption. The frequency response masking (FRM) approach is proved to be a good candidate for the realization of a sharp digital finite impulse response (FIR) filter with low complexity. To reduce the complexity further, this paper gives an optimal design method which makes the channel filters totally multiplier-less. This is done in two steps. The channel filters are designed using the FRM approach with continuous filter coefficients. To obtain multiplier-less design, these filter coefficients are converted to finite-precision coefficients using signed power of two (SPT) space and the filter coefficients are synthesized in the canonic signed-digit (CSD) format. But this may lead to degradation of the filter performance. Hence the filter coefficients synthesis in the CSD format is formulated as an optimization problem. Several meta-heuristic algorithms like Differential Evolution (DE), Artificial Bee Colony (ABC), Harmony Search Algorithm (HSA) and Gravitational Search Algorithm (GSA) are modified and deployed and the best one is selected.     

Design of linear combination of weighted medians

This paper introduces a novel nonlinear filtering structure: the linear combination of weighted medians (LCWM). The proposed filtering scheme is modeled on the structure and design procedure of the linear-phase FIR highpass (HP) filter in that the linear-phase FIR HP filter can be obtained by changing the sign of the filter coefficients of the FIR lowpass (LP) filter in the odd positions. The HP filter can be represented as the difference between two LP subfilters that have all positive coefficients. This representation of the FIR HP filter is analogous to the difference of estimates (DoE) such as the difference of medians (DoM). The DoM is essentially a nonlinear HP filter that is commonly used in edge detection. Based on this observation, we introduce a class of LCWM filters whose output is given by a linear combination of weighted medians of the input sequence. We propose a method of designing the 1-D and 2-D LCWM filters satisfying required frequency specifications. The proposed method adopts a transformation from the FIR filter to the LCWM filter. We show that the proposed LCWM filter can offer various frequency filtering characteristics including “LP,” “bandpass (BP),” and “HP” responses     

Discrete Lagrangian Methods for Designing Multiplierless Two-Channel PR-LP Filter Banks

In this paper, we present a new search method based on the theory of discrete Lagrange multipliers for designing multiplierless PR (perfect reconstruction) LP (linear phase) filter banks. To satisfy the PR constraints, we choose a lattice structure that, under certain conditions, can guarantee the resulting two filters to be a PR pair. Unlike the design of multiplierless QMF filter banks that represents filter coefficients directly using PO2 (powers-of-two) form (also called Canonical Signed Digit or CSD representation), we use PO2 forms to represent the parameters associated with the lattice structure. By representing these parameters as sums or differences of powers of two, multiplications can be carried out as additions, subtractions, and shifts. Using the lattice representation, we decompose the design problem into a sequence of four subproblems. The first two subproblems find a good starting point with continuous parameters using a single-objective, multi-constraint formulation. The last two subproblems first transform the continuous solution found by the second subproblem into a PO2 form, then search for a design in a mixed-integer space. We propose a new search method based on the theory of discrete Lagrange multipliers for finding good designs, and study methods to improve its convergence speed by adjusting dynamically the relative weights between the objective and the Lagrangian part. We show that our method can find good designs using at most four terms in PO2 form in each lattice parameter. Our approach is unique because our results are the first successful designs of multiplierless PR-LP filter banks. It is general because it is applicable to the design of other types of multiplierless filter banks.     

基于MATLAB及FPGA的高速FIR滤波器的设计

FIR滤波器是一种被广泛应用的基本的数字信号处理部件。现提出采用MATLAB的窗函数方法设计并在附上实现高速FIR滤波器的一种新的方案。这种结构采用流水线技术，通过对高速乘法器的合理分割并组合Wallace加法树阵列构成，可以方便地调整滤波器的阶数和系数，适合不同场合的应用。通过编程调试结果表明，该设计是可靠的，可作为高速数字滤波器设计的较好方案。     

A new method for designing multiplierless two-channel filterbank using shifted-Chebyshev polynomials

This paper presents an efficient design method for a digital multiplierless two-channel filterbank using the shifted-Chebyshev polynomials and common sub-expression elimination (CSE) algorithm for reducing hardware requirements such as adders and multipliers. For designing a two-channel filterbank, the design problem is constructed as minimization of integral mean square error between the desired and designed response of a prototype filter in the passband and stopband. For controlling the performance in passband and stopband, two parameters (K_P, and K_S) are used, whose optimum values are determined by swam optimization techniques such as differential evolution algorithm, artificial bee colony optimization, particle swarm optimizations, cuckoo search algorithm and hybrid method using a fitness function, constructed by perfect reconstruction condition of a filterbank. The number of polynomials used for approximation depends upon the order of a prototype filter. A new hybrid CSE is proposed for further reduction of hardware requirement. A comparative study of various CSE techniques such as horizontal, vertical and proposed hybrid CSE is also made. Numerical examples illustrate the effectiveness of the proposed algorithm in the reduction of adders with comparisons accomplished using existing methods. It has been found that almost 43% adder gain can be achieved when a filter is designed with N = 32 and wordlength (WL) as 12 using proposed methodology.